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1//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the SIMD extension instructions.10//11//===----------------------------------------------------------------------===//12 13def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,14 SDTCisInt<1>, SDTCisVec<1>,15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;16def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;17 18def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,19 SDTCisInt<1>, SDTCisVec<1>,20 SDTCisSameAs<0, 2>,21 SDTCisSameAs<2, 3>]>;22def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;24def SDT_LoongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,25 SDTCisSameAs<0,1>, SDTCisVT<2, GRLenVT>]>;26def SDT_LoongArchV2RUimm27 : SDTypeProfile<1, 3,28 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,29 SDTCisVT<3, GRLenVT>]>;30def SDT_LoongArchVreplgr2vr : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>]>;31def SDT_LoongArchVFRECIPE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;32def SDT_LoongArchVFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;33def SDT_LoongArchVLDREPL : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisPtrTy<1>]>;34def SDT_LoongArchVMSKCOND : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;35 36// Target nodes.37 38// Vector Shuffle39def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>;40 41// Vector comparisons42def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO",43 SDT_LoongArchVecCond>;44def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO",45 SDT_LoongArchVecCond>;46def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO",47 SDT_LoongArchVecCond>;48def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO",49 SDT_LoongArchVecCond>;50 51// Extended vector element extraction52def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT",53 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>;54def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT",55 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>;56 57// Vector Shuffle58def loongarch_vshuf: SDNode<"LoongArchISD::VSHUF", SDT_LoongArchVShuf>;59def loongarch_vpickev: SDNode<"LoongArchISD::VPICKEV", SDT_LoongArchV2R>;60def loongarch_vpickod: SDNode<"LoongArchISD::VPICKOD", SDT_LoongArchV2R>;61def loongarch_vpackev: SDNode<"LoongArchISD::VPACKEV", SDT_LoongArchV2R>;62def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>;63def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>;64def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>;65def loongarch_vandn: SDNode<"LoongArchISD::VANDN", SDT_LoongArchV2R>;66 67def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_LoongArchV1RUimm>;68def loongarch_vshuf4i_d : SDNode<"LoongArchISD::VSHUF4I_D", SDT_LoongArchV2RUimm>;69def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_LoongArchV1RUimm>;70def loongarch_vreplgr2vr: SDNode<"LoongArchISD::VREPLGR2VR", SDT_LoongArchVreplgr2vr>;71 72def loongarch_vfrecipe: SDNode<"LoongArchISD::FRECIPE", SDT_LoongArchVFRECIPE>;73def loongarch_vfrsqrte: SDNode<"LoongArchISD::FRSQRTE", SDT_LoongArchVFRSQRTE>;74 75// Vector logicial left / right shift by immediate76def loongarch_vslli : SDNode<"LoongArchISD::VSLLI", SDT_LoongArchV1RUimm>;77def loongarch_vsrli : SDNode<"LoongArchISD::VSRLI", SDT_LoongArchV1RUimm>;78 79// Vector byte logicial left / right shift80def loongarch_vbsll : SDNode<"LoongArchISD::VBSLL", SDT_LoongArchV1RUimm>;81def loongarch_vbsrl : SDNode<"LoongArchISD::VBSRL", SDT_LoongArchV1RUimm>;82 83// Vector Horizontal Addition with Widening84def loongarch_vhaddw : SDNode<"LoongArchISD::VHADDW", SDT_LoongArchV2R>;85 86// Scalar load broadcast to vector87def loongarch_vldrepl88 : SDNode<"LoongArchISD::VLDREPL",89 SDT_LoongArchVLDREPL, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;90 91// Vector mask set by condition92def loongarch_vmskltz: SDNode<"LoongArchISD::VMSKLTZ", SDT_LoongArchVMSKCOND>;93def loongarch_vmskgez: SDNode<"LoongArchISD::VMSKGEZ", SDT_LoongArchVMSKCOND>;94def loongarch_vmskeqz: SDNode<"LoongArchISD::VMSKEQZ", SDT_LoongArchVMSKCOND>;95def loongarch_vmsknez: SDNode<"LoongArchISD::VMSKNEZ", SDT_LoongArchVMSKCOND>;96 97def immZExt1 : ImmLeaf<GRLenVT, [{return isUInt<1>(Imm);}]>;98def immZExt2 : ImmLeaf<GRLenVT, [{return isUInt<2>(Imm);}]>;99def immZExt3 : ImmLeaf<GRLenVT, [{return isUInt<3>(Imm);}]>;100def immZExt4 : ImmLeaf<GRLenVT, [{return isUInt<4>(Imm);}]>;101def immZExt8 : ImmLeaf<GRLenVT, [{return isUInt<8>(Imm);}]>;102 103class VecCond<SDPatternOperator OpNode, ValueType TyNode,104 RegisterClass RC = LSX128>105 : Pseudo<(outs GPR:$rd), (ins RC:$vj),106 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> {107 let hasSideEffects = 0;108 let mayLoad = 0;109 let mayStore = 0;110 let usesCustomInserter = 1;111}112 113def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{114 APInt Imm;115 EVT EltTy = N->getValueType(0).getVectorElementType();116 117 if (N->getOpcode() == ISD::BITCAST)118 N = N->getOperand(0).getNode();119 120 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&121 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;122}]>;123 124def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{125 APInt Imm;126 EVT EltTy = N->getValueType(0).getVectorElementType();127 128 if (N->getOpcode() == ISD::BITCAST)129 N = N->getOperand(0).getNode();130 131 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&132 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7;133}]>;134def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{135 APInt Imm;136 EVT EltTy = N->getValueType(0).getVectorElementType();137 138 if (N->getOpcode() == ISD::BITCAST)139 N = N->getOperand(0).getNode();140 141 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&142 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15;143}]>;144def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{145 APInt Imm;146 EVT EltTy = N->getValueType(0).getVectorElementType();147 148 if (N->getOpcode() == ISD::BITCAST)149 N = N->getOperand(0).getNode();150 151 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&152 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31;153}]>;154def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{155 APInt Imm;156 EVT EltTy = N->getValueType(0).getVectorElementType();157 158 if (N->getOpcode() == ISD::BITCAST)159 N = N->getOperand(0).getNode();160 161 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&162 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;163}]>;164 165def vsplatf32_fpimm_eq_1166 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))),167 (bitconvert (v8i32 (build_vector)))], [{168 APInt Imm;169 EVT EltTy = N->getValueType(0).getVectorElementType();170 N = N->getOperand(0).getNode();171 172 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&173 Imm.getBitWidth() == 32 &&174 Imm.getBitWidth() == EltTy.getSizeInBits() &&175 Imm == APFloat(+1.0f).bitcastToAPInt();176}]>;177def vsplatf64_fpimm_eq_1178 : PatFrags<(ops), [(bitconvert (v2i64 (build_vector))),179 (bitconvert (v4i64 (build_vector)))], [{180 APInt Imm;181 EVT EltTy = N->getValueType(0).getVectorElementType();182 N = N->getOperand(0).getNode();183 184 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&185 Imm.getBitWidth() == EltTy.getSizeInBits() &&186 Imm == APFloat(+1.0).bitcastToAPInt();187}]>;188 189def vsplati8imm7 : PatFrag<(ops node:$reg),190 (and node:$reg, vsplati8_imm_eq_7)>;191def vsplati16imm15 : PatFrag<(ops node:$reg),192 (and node:$reg, vsplati16_imm_eq_15)>;193def vsplati32imm31 : PatFrag<(ops node:$reg),194 (and node:$reg, vsplati32_imm_eq_31)>;195def vsplati64imm63 : PatFrag<(ops node:$reg),196 (and node:$reg, vsplati64_imm_eq_63)>;197 198foreach N = [3, 4, 5, 6, 8] in199 def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">",200 [build_vector, bitconvert], [], 2>;201 202foreach N = [5] in203 def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>",204 [build_vector, bitconvert]>;205 206def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",207 [build_vector, bitconvert]>;208 209def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",210 [build_vector, bitconvert]>;211 212def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk),213 (add node:$vd, (mul node:$vj, node:$vk))>;214 215def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk),216 (sub node:$vd, (mul node:$vj, node:$vk))>;217 218def lsxsplati8 : PatFrag<(ops node:$e0),219 (v16i8 (build_vector node:$e0, node:$e0,220 node:$e0, node:$e0,221 node:$e0, node:$e0,222 node:$e0, node:$e0,223 node:$e0, node:$e0,224 node:$e0, node:$e0,225 node:$e0, node:$e0,226 node:$e0, node:$e0))>;227def lsxsplati16 : PatFrag<(ops node:$e0),228 (v8i16 (build_vector node:$e0, node:$e0,229 node:$e0, node:$e0,230 node:$e0, node:$e0,231 node:$e0, node:$e0))>;232def lsxsplati32 : PatFrag<(ops node:$e0),233 (v4i32 (build_vector node:$e0, node:$e0,234 node:$e0, node:$e0))>;235def lsxsplati64 : PatFrag<(ops node:$e0),236 (v2i64 (build_vector node:$e0, node:$e0))>;237def lsxsplatf32 : PatFrag<(ops node:$e0),238 (v4f32 (build_vector node:$e0, node:$e0,239 node:$e0, node:$e0))>;240def lsxsplatf64 : PatFrag<(ops node:$e0),241 (v2f64 (build_vector node:$e0, node:$e0))>;242 243def to_valid_timm : SDNodeXForm<timm, [{244 auto CN = cast<ConstantSDNode>(N);245 return CurDAG->getSignedTargetConstant(CN->getSExtValue(), SDLoc(N),246 Subtarget->getGRLenVT());247}]>;248 249// FP immediate of VLDI patterns.250def f32imm_vldi : PatLeaf<(fpimm), [{251 const auto &TLI =252 *static_cast<const LoongArchTargetLowering*>(getTargetLowering());253 return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f32);254}]>;255def f64imm_vldi : PatLeaf<(fpimm), [{256 const auto &TLI =257 *static_cast<const LoongArchTargetLowering*>(getTargetLowering());258 return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f64);259}]>;260 261def to_f32imm_vldi : SDNodeXForm<fpimm, [{262 uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();263 x = (0b11011 << 8) | (((x >> 24) & 0xc0) ^ 0x40) | ((x >> 19) & 0x3f);264 return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),265 MVT::i32);266}]>;267def to_f64imm_vldi : SDNodeXForm<fpimm, [{268 uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();269 x = (0b11100 << 8) | (((x >> 56) & 0xc0) ^ 0x40) | ((x >> 48) & 0x3f);270 return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),271 MVT::i32);272}]>;273 274//===----------------------------------------------------------------------===//275// Instruction class templates276//===----------------------------------------------------------------------===//277 278class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13>279 : Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">;280 281class LSX2R_VV<bits<32> op>282 : Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">;283 284class LSX2R_VR<bits<32> op>285 : Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">;286 287class LSX2R_CV<bits<32> op>288 : Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">;289 290class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1>291 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1),292 "$vd, $vj, $imm1">;293 294class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1>295 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1),296 "$rd, $vj, $imm1">;297 298class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2>299 : Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2),300 "$vd, $vj, $imm2">;301 302class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2>303 : Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2),304 "$rd, $vj, $imm2">;305 306class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3>307 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3),308 "$vd, $vj, $imm3">;309 310class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3>311 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3),312 "$rd, $vj, $imm3">;313 314class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4>315 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4),316 "$vd, $vj, $imm4">;317 318class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4>319 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4),320 "$rd, $vj, $imm4">;321 322class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5>323 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5),324 "$vd, $vj, $imm5">;325 326class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6>327 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6),328 "$vd, $vj, $imm6">;329 330class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8>331 : Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8),332 "$vd, $vj, $imm8">;333 334class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8,335 Operand IdxOpnd = uimm1>336 : Fmt2RI8I1_VRII<op, (outs),337 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1),338 "$vd, $rj, $imm8, $imm1">;339class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8,340 Operand IdxOpnd = uimm2>341 : Fmt2RI8I2_VRII<op, (outs),342 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2),343 "$vd, $rj, $imm8, $imm2">;344class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8,345 Operand IdxOpnd = uimm3>346 : Fmt2RI8I3_VRII<op, (outs),347 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),348 "$vd, $rj, $imm8, $imm3">;349class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8,350 Operand IdxOpnd = uimm4>351 : Fmt2RI8I4_VRII<op, (outs),352 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),353 "$vd, $rj, $imm8, $imm4">;354 355class LSX3R_VVV<bits<32> op>356 : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk),357 "$vd, $vj, $vk">;358 359class LSX3R_VVR<bits<32> op>360 : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk),361 "$vd, $vj, $rk">;362 363class LSX4R_VVVV<bits<32> op>364 : Fmt4R_VVVV<op, (outs LSX128:$vd),365 (ins LSX128:$vj, LSX128:$vk, LSX128:$va),366 "$vd, $vj, $vk, $va">;367 368let Constraints = "$vd = $dst" in {369 370class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1>371 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1),372 "$vd, $rj, $imm1">;373class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2>374 : Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2),375 "$vd, $rj, $imm2">;376class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3>377 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3),378 "$vd, $rj, $imm3">;379class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4>380 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4),381 "$vd, $rj, $imm4">;382 383class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4>384 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4),385 "$vd, $vj, $imm4">;386class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5>387 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5),388 "$vd, $vj, $imm5">;389class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6>390 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6),391 "$vd, $vj, $imm6">;392class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7>393 : Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7),394 "$vd, $vj, $imm7">;395 396class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8>397 : Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8),398 "$vd, $vj, $imm8">;399 400class LSX3R_VVVV<bits<32> op>401 : Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk),402 "$vd, $vj, $vk">;403 404} // Constraints = "$vd = $dst"405 406class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3>407 : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9),408 "$vd, $rj, $imm9">;409class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2>410 : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10),411 "$vd, $rj, $imm10">;412class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1>413 : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11),414 "$vd, $rj, $imm11">;415class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12_addlike>416 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12),417 "$vd, $rj, $imm12">;418class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12_addlike>419 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12),420 "$vd, $rj, $imm12">;421 422class LSX3R_Load<bits<32> op>423 : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk),424 "$vd, $rj, $rk">;425class LSX3R_Store<bits<32> op>426 : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk),427 "$vd, $rj, $rk">;428 429//===----------------------------------------------------------------------===//430// Instructions431//===----------------------------------------------------------------------===//432 433let hasSideEffects = 0, Predicates = [HasExtLSX] in {434 435let mayLoad = 0, mayStore = 0 in {436 437def VADD_B : LSX3R_VVV<0x700a0000>;438def VADD_H : LSX3R_VVV<0x700a8000>;439def VADD_W : LSX3R_VVV<0x700b0000>;440def VADD_D : LSX3R_VVV<0x700b8000>;441def VADD_Q : LSX3R_VVV<0x712d0000>;442 443def VSUB_B : LSX3R_VVV<0x700c0000>;444def VSUB_H : LSX3R_VVV<0x700c8000>;445def VSUB_W : LSX3R_VVV<0x700d0000>;446def VSUB_D : LSX3R_VVV<0x700d8000>;447def VSUB_Q : LSX3R_VVV<0x712d8000>;448 449def VADDI_BU : LSX2RI5_VVI<0x728a0000>;450def VADDI_HU : LSX2RI5_VVI<0x728a8000>;451def VADDI_WU : LSX2RI5_VVI<0x728b0000>;452def VADDI_DU : LSX2RI5_VVI<0x728b8000>;453 454def VSUBI_BU : LSX2RI5_VVI<0x728c0000>;455def VSUBI_HU : LSX2RI5_VVI<0x728c8000>;456def VSUBI_WU : LSX2RI5_VVI<0x728d0000>;457def VSUBI_DU : LSX2RI5_VVI<0x728d8000>;458 459def VNEG_B : LSX2R_VV<0x729c3000>;460def VNEG_H : LSX2R_VV<0x729c3400>;461def VNEG_W : LSX2R_VV<0x729c3800>;462def VNEG_D : LSX2R_VV<0x729c3c00>;463 464def VSADD_B : LSX3R_VVV<0x70460000>;465def VSADD_H : LSX3R_VVV<0x70468000>;466def VSADD_W : LSX3R_VVV<0x70470000>;467def VSADD_D : LSX3R_VVV<0x70478000>;468def VSADD_BU : LSX3R_VVV<0x704a0000>;469def VSADD_HU : LSX3R_VVV<0x704a8000>;470def VSADD_WU : LSX3R_VVV<0x704b0000>;471def VSADD_DU : LSX3R_VVV<0x704b8000>;472 473def VSSUB_B : LSX3R_VVV<0x70480000>;474def VSSUB_H : LSX3R_VVV<0x70488000>;475def VSSUB_W : LSX3R_VVV<0x70490000>;476def VSSUB_D : LSX3R_VVV<0x70498000>;477def VSSUB_BU : LSX3R_VVV<0x704c0000>;478def VSSUB_HU : LSX3R_VVV<0x704c8000>;479def VSSUB_WU : LSX3R_VVV<0x704d0000>;480def VSSUB_DU : LSX3R_VVV<0x704d8000>;481 482def VHADDW_H_B : LSX3R_VVV<0x70540000>;483def VHADDW_W_H : LSX3R_VVV<0x70548000>;484def VHADDW_D_W : LSX3R_VVV<0x70550000>;485def VHADDW_Q_D : LSX3R_VVV<0x70558000>;486def VHADDW_HU_BU : LSX3R_VVV<0x70580000>;487def VHADDW_WU_HU : LSX3R_VVV<0x70588000>;488def VHADDW_DU_WU : LSX3R_VVV<0x70590000>;489def VHADDW_QU_DU : LSX3R_VVV<0x70598000>;490 491def VHSUBW_H_B : LSX3R_VVV<0x70560000>;492def VHSUBW_W_H : LSX3R_VVV<0x70568000>;493def VHSUBW_D_W : LSX3R_VVV<0x70570000>;494def VHSUBW_Q_D : LSX3R_VVV<0x70578000>;495def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>;496def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>;497def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>;498def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>;499 500def VADDWEV_H_B : LSX3R_VVV<0x701e0000>;501def VADDWEV_W_H : LSX3R_VVV<0x701e8000>;502def VADDWEV_D_W : LSX3R_VVV<0x701f0000>;503def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>;504def VADDWOD_H_B : LSX3R_VVV<0x70220000>;505def VADDWOD_W_H : LSX3R_VVV<0x70228000>;506def VADDWOD_D_W : LSX3R_VVV<0x70230000>;507def VADDWOD_Q_D : LSX3R_VVV<0x70238000>;508 509def VSUBWEV_H_B : LSX3R_VVV<0x70200000>;510def VSUBWEV_W_H : LSX3R_VVV<0x70208000>;511def VSUBWEV_D_W : LSX3R_VVV<0x70210000>;512def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>;513def VSUBWOD_H_B : LSX3R_VVV<0x70240000>;514def VSUBWOD_W_H : LSX3R_VVV<0x70248000>;515def VSUBWOD_D_W : LSX3R_VVV<0x70250000>;516def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>;517 518def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>;519def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>;520def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>;521def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>;522def VADDWOD_H_BU : LSX3R_VVV<0x70320000>;523def VADDWOD_W_HU : LSX3R_VVV<0x70328000>;524def VADDWOD_D_WU : LSX3R_VVV<0x70330000>;525def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>;526 527def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>;528def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>;529def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>;530def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>;531def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>;532def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>;533def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>;534def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>;535 536def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>;537def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>;538def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>;539def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>;540def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>;541def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>;542def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>;543def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>;544 545def VAVG_B : LSX3R_VVV<0x70640000>;546def VAVG_H : LSX3R_VVV<0x70648000>;547def VAVG_W : LSX3R_VVV<0x70650000>;548def VAVG_D : LSX3R_VVV<0x70658000>;549def VAVG_BU : LSX3R_VVV<0x70660000>;550def VAVG_HU : LSX3R_VVV<0x70668000>;551def VAVG_WU : LSX3R_VVV<0x70670000>;552def VAVG_DU : LSX3R_VVV<0x70678000>;553def VAVGR_B : LSX3R_VVV<0x70680000>;554def VAVGR_H : LSX3R_VVV<0x70688000>;555def VAVGR_W : LSX3R_VVV<0x70690000>;556def VAVGR_D : LSX3R_VVV<0x70698000>;557def VAVGR_BU : LSX3R_VVV<0x706a0000>;558def VAVGR_HU : LSX3R_VVV<0x706a8000>;559def VAVGR_WU : LSX3R_VVV<0x706b0000>;560def VAVGR_DU : LSX3R_VVV<0x706b8000>;561 562def VABSD_B : LSX3R_VVV<0x70600000>;563def VABSD_H : LSX3R_VVV<0x70608000>;564def VABSD_W : LSX3R_VVV<0x70610000>;565def VABSD_D : LSX3R_VVV<0x70618000>;566def VABSD_BU : LSX3R_VVV<0x70620000>;567def VABSD_HU : LSX3R_VVV<0x70628000>;568def VABSD_WU : LSX3R_VVV<0x70630000>;569def VABSD_DU : LSX3R_VVV<0x70638000>;570 571def VADDA_B : LSX3R_VVV<0x705c0000>;572def VADDA_H : LSX3R_VVV<0x705c8000>;573def VADDA_W : LSX3R_VVV<0x705d0000>;574def VADDA_D : LSX3R_VVV<0x705d8000>;575 576def VMAX_B : LSX3R_VVV<0x70700000>;577def VMAX_H : LSX3R_VVV<0x70708000>;578def VMAX_W : LSX3R_VVV<0x70710000>;579def VMAX_D : LSX3R_VVV<0x70718000>;580def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>;581def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>;582def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>;583def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>;584def VMAX_BU : LSX3R_VVV<0x70740000>;585def VMAX_HU : LSX3R_VVV<0x70748000>;586def VMAX_WU : LSX3R_VVV<0x70750000>;587def VMAX_DU : LSX3R_VVV<0x70758000>;588def VMAXI_BU : LSX2RI5_VVI<0x72940000>;589def VMAXI_HU : LSX2RI5_VVI<0x72948000>;590def VMAXI_WU : LSX2RI5_VVI<0x72950000>;591def VMAXI_DU : LSX2RI5_VVI<0x72958000>;592 593def VMIN_B : LSX3R_VVV<0x70720000>;594def VMIN_H : LSX3R_VVV<0x70728000>;595def VMIN_W : LSX3R_VVV<0x70730000>;596def VMIN_D : LSX3R_VVV<0x70738000>;597def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>;598def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>;599def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>;600def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>;601def VMIN_BU : LSX3R_VVV<0x70760000>;602def VMIN_HU : LSX3R_VVV<0x70768000>;603def VMIN_WU : LSX3R_VVV<0x70770000>;604def VMIN_DU : LSX3R_VVV<0x70778000>;605def VMINI_BU : LSX2RI5_VVI<0x72960000>;606def VMINI_HU : LSX2RI5_VVI<0x72968000>;607def VMINI_WU : LSX2RI5_VVI<0x72970000>;608def VMINI_DU : LSX2RI5_VVI<0x72978000>;609 610def VMUL_B : LSX3R_VVV<0x70840000>;611def VMUL_H : LSX3R_VVV<0x70848000>;612def VMUL_W : LSX3R_VVV<0x70850000>;613def VMUL_D : LSX3R_VVV<0x70858000>;614 615def VMUH_B : LSX3R_VVV<0x70860000>;616def VMUH_H : LSX3R_VVV<0x70868000>;617def VMUH_W : LSX3R_VVV<0x70870000>;618def VMUH_D : LSX3R_VVV<0x70878000>;619def VMUH_BU : LSX3R_VVV<0x70880000>;620def VMUH_HU : LSX3R_VVV<0x70888000>;621def VMUH_WU : LSX3R_VVV<0x70890000>;622def VMUH_DU : LSX3R_VVV<0x70898000>;623 624def VMULWEV_H_B : LSX3R_VVV<0x70900000>;625def VMULWEV_W_H : LSX3R_VVV<0x70908000>;626def VMULWEV_D_W : LSX3R_VVV<0x70910000>;627def VMULWEV_Q_D : LSX3R_VVV<0x70918000>;628def VMULWOD_H_B : LSX3R_VVV<0x70920000>;629def VMULWOD_W_H : LSX3R_VVV<0x70928000>;630def VMULWOD_D_W : LSX3R_VVV<0x70930000>;631def VMULWOD_Q_D : LSX3R_VVV<0x70938000>;632def VMULWEV_H_BU : LSX3R_VVV<0x70980000>;633def VMULWEV_W_HU : LSX3R_VVV<0x70988000>;634def VMULWEV_D_WU : LSX3R_VVV<0x70990000>;635def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>;636def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>;637def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>;638def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>;639def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>;640def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>;641def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>;642def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>;643def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>;644def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>;645def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>;646def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>;647def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>;648 649def VMADD_B : LSX3R_VVVV<0x70a80000>;650def VMADD_H : LSX3R_VVVV<0x70a88000>;651def VMADD_W : LSX3R_VVVV<0x70a90000>;652def VMADD_D : LSX3R_VVVV<0x70a98000>;653 654def VMSUB_B : LSX3R_VVVV<0x70aa0000>;655def VMSUB_H : LSX3R_VVVV<0x70aa8000>;656def VMSUB_W : LSX3R_VVVV<0x70ab0000>;657def VMSUB_D : LSX3R_VVVV<0x70ab8000>;658 659def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>;660def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>;661def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>;662def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>;663def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>;664def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>;665def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>;666def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>;667def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>;668def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>;669def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>;670def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>;671def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>;672def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>;673def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>;674def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>;675def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>;676def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>;677def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>;678def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>;679def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>;680def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>;681def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>;682def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>;683 684def VDIV_B : LSX3R_VVV<0x70e00000>;685def VDIV_H : LSX3R_VVV<0x70e08000>;686def VDIV_W : LSX3R_VVV<0x70e10000>;687def VDIV_D : LSX3R_VVV<0x70e18000>;688def VDIV_BU : LSX3R_VVV<0x70e40000>;689def VDIV_HU : LSX3R_VVV<0x70e48000>;690def VDIV_WU : LSX3R_VVV<0x70e50000>;691def VDIV_DU : LSX3R_VVV<0x70e58000>;692 693def VMOD_B : LSX3R_VVV<0x70e20000>;694def VMOD_H : LSX3R_VVV<0x70e28000>;695def VMOD_W : LSX3R_VVV<0x70e30000>;696def VMOD_D : LSX3R_VVV<0x70e38000>;697def VMOD_BU : LSX3R_VVV<0x70e60000>;698def VMOD_HU : LSX3R_VVV<0x70e68000>;699def VMOD_WU : LSX3R_VVV<0x70e70000>;700def VMOD_DU : LSX3R_VVV<0x70e78000>;701 702def VSAT_B : LSX2RI3_VVI<0x73242000>;703def VSAT_H : LSX2RI4_VVI<0x73244000>;704def VSAT_W : LSX2RI5_VVI<0x73248000>;705def VSAT_D : LSX2RI6_VVI<0x73250000>;706def VSAT_BU : LSX2RI3_VVI<0x73282000>;707def VSAT_HU : LSX2RI4_VVI<0x73284000>;708def VSAT_WU : LSX2RI5_VVI<0x73288000>;709def VSAT_DU : LSX2RI6_VVI<0x73290000>;710 711def VEXTH_H_B : LSX2R_VV<0x729ee000>;712def VEXTH_W_H : LSX2R_VV<0x729ee400>;713def VEXTH_D_W : LSX2R_VV<0x729ee800>;714def VEXTH_Q_D : LSX2R_VV<0x729eec00>;715def VEXTH_HU_BU : LSX2R_VV<0x729ef000>;716def VEXTH_WU_HU : LSX2R_VV<0x729ef400>;717def VEXTH_DU_WU : LSX2R_VV<0x729ef800>;718def VEXTH_QU_DU : LSX2R_VV<0x729efc00>;719 720def VSIGNCOV_B : LSX3R_VVV<0x712e0000>;721def VSIGNCOV_H : LSX3R_VVV<0x712e8000>;722def VSIGNCOV_W : LSX3R_VVV<0x712f0000>;723def VSIGNCOV_D : LSX3R_VVV<0x712f8000>;724 725def VMSKLTZ_B : LSX2R_VV<0x729c4000>;726def VMSKLTZ_H : LSX2R_VV<0x729c4400>;727def VMSKLTZ_W : LSX2R_VV<0x729c4800>;728def VMSKLTZ_D : LSX2R_VV<0x729c4c00>;729 730def VMSKGEZ_B : LSX2R_VV<0x729c5000>;731 732def VMSKNZ_B : LSX2R_VV<0x729c6000>;733 734let isReMaterializable = 1, isAsCheapAsAMove = 1 in {735def VLDI : LSX1RI13_VI<0x73e00000>;736}737 738def VAND_V : LSX3R_VVV<0x71260000>;739def VOR_V : LSX3R_VVV<0x71268000>;740def VXOR_V : LSX3R_VVV<0x71270000>;741def VNOR_V : LSX3R_VVV<0x71278000>;742def VANDN_V : LSX3R_VVV<0x71280000>;743def VORN_V : LSX3R_VVV<0x71288000>;744 745def VANDI_B : LSX2RI8_VVI<0x73d00000>;746def VORI_B : LSX2RI8_VVI<0x73d40000>;747def VXORI_B : LSX2RI8_VVI<0x73d80000>;748def VNORI_B : LSX2RI8_VVI<0x73dc0000>;749 750def VSLL_B : LSX3R_VVV<0x70e80000>;751def VSLL_H : LSX3R_VVV<0x70e88000>;752def VSLL_W : LSX3R_VVV<0x70e90000>;753def VSLL_D : LSX3R_VVV<0x70e98000>;754def VSLLI_B : LSX2RI3_VVI<0x732c2000>;755def VSLLI_H : LSX2RI4_VVI<0x732c4000>;756def VSLLI_W : LSX2RI5_VVI<0x732c8000>;757def VSLLI_D : LSX2RI6_VVI<0x732d0000>;758 759def VSRL_B : LSX3R_VVV<0x70ea0000>;760def VSRL_H : LSX3R_VVV<0x70ea8000>;761def VSRL_W : LSX3R_VVV<0x70eb0000>;762def VSRL_D : LSX3R_VVV<0x70eb8000>;763def VSRLI_B : LSX2RI3_VVI<0x73302000>;764def VSRLI_H : LSX2RI4_VVI<0x73304000>;765def VSRLI_W : LSX2RI5_VVI<0x73308000>;766def VSRLI_D : LSX2RI6_VVI<0x73310000>;767 768def VSRA_B : LSX3R_VVV<0x70ec0000>;769def VSRA_H : LSX3R_VVV<0x70ec8000>;770def VSRA_W : LSX3R_VVV<0x70ed0000>;771def VSRA_D : LSX3R_VVV<0x70ed8000>;772def VSRAI_B : LSX2RI3_VVI<0x73342000>;773def VSRAI_H : LSX2RI4_VVI<0x73344000>;774def VSRAI_W : LSX2RI5_VVI<0x73348000>;775def VSRAI_D : LSX2RI6_VVI<0x73350000>;776 777def VROTR_B : LSX3R_VVV<0x70ee0000>;778def VROTR_H : LSX3R_VVV<0x70ee8000>;779def VROTR_W : LSX3R_VVV<0x70ef0000>;780def VROTR_D : LSX3R_VVV<0x70ef8000>;781def VROTRI_B : LSX2RI3_VVI<0x72a02000>;782def VROTRI_H : LSX2RI4_VVI<0x72a04000>;783def VROTRI_W : LSX2RI5_VVI<0x72a08000>;784def VROTRI_D : LSX2RI6_VVI<0x72a10000>;785 786def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>;787def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>;788def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>;789def VEXTL_Q_D : LSX2R_VV<0x73090000>;790def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>;791def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>;792def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>;793def VEXTL_QU_DU : LSX2R_VV<0x730d0000>;794 795def VSRLR_B : LSX3R_VVV<0x70f00000>;796def VSRLR_H : LSX3R_VVV<0x70f08000>;797def VSRLR_W : LSX3R_VVV<0x70f10000>;798def VSRLR_D : LSX3R_VVV<0x70f18000>;799def VSRLRI_B : LSX2RI3_VVI<0x72a42000>;800def VSRLRI_H : LSX2RI4_VVI<0x72a44000>;801def VSRLRI_W : LSX2RI5_VVI<0x72a48000>;802def VSRLRI_D : LSX2RI6_VVI<0x72a50000>;803 804def VSRAR_B : LSX3R_VVV<0x70f20000>;805def VSRAR_H : LSX3R_VVV<0x70f28000>;806def VSRAR_W : LSX3R_VVV<0x70f30000>;807def VSRAR_D : LSX3R_VVV<0x70f38000>;808def VSRARI_B : LSX2RI3_VVI<0x72a82000>;809def VSRARI_H : LSX2RI4_VVI<0x72a84000>;810def VSRARI_W : LSX2RI5_VVI<0x72a88000>;811def VSRARI_D : LSX2RI6_VVI<0x72a90000>;812 813def VSRLN_B_H : LSX3R_VVV<0x70f48000>;814def VSRLN_H_W : LSX3R_VVV<0x70f50000>;815def VSRLN_W_D : LSX3R_VVV<0x70f58000>;816def VSRAN_B_H : LSX3R_VVV<0x70f68000>;817def VSRAN_H_W : LSX3R_VVV<0x70f70000>;818def VSRAN_W_D : LSX3R_VVV<0x70f78000>;819 820def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>;821def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>;822def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>;823def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>;824def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>;825def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>;826def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>;827def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>;828 829def VSRLRN_B_H : LSX3R_VVV<0x70f88000>;830def VSRLRN_H_W : LSX3R_VVV<0x70f90000>;831def VSRLRN_W_D : LSX3R_VVV<0x70f98000>;832def VSRARN_B_H : LSX3R_VVV<0x70fa8000>;833def VSRARN_H_W : LSX3R_VVV<0x70fb0000>;834def VSRARN_W_D : LSX3R_VVV<0x70fb8000>;835 836def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>;837def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>;838def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>;839def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>;840def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>;841def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>;842def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>;843def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>;844 845def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>;846def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>;847def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>;848def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>;849def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>;850def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>;851def VSSRLN_BU_H : LSX3R_VVV<0x71048000>;852def VSSRLN_HU_W : LSX3R_VVV<0x71050000>;853def VSSRLN_WU_D : LSX3R_VVV<0x71058000>;854def VSSRAN_BU_H : LSX3R_VVV<0x71068000>;855def VSSRAN_HU_W : LSX3R_VVV<0x71070000>;856def VSSRAN_WU_D : LSX3R_VVV<0x71078000>;857 858def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>;859def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>;860def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>;861def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>;862def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>;863def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>;864def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>;865def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>;866def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>;867def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>;868def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>;869def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>;870def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>;871def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>;872def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>;873def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>;874 875def VSSRLRN_B_H : LSX3R_VVV<0x71008000>;876def VSSRLRN_H_W : LSX3R_VVV<0x71010000>;877def VSSRLRN_W_D : LSX3R_VVV<0x71018000>;878def VSSRARN_B_H : LSX3R_VVV<0x71028000>;879def VSSRARN_H_W : LSX3R_VVV<0x71030000>;880def VSSRARN_W_D : LSX3R_VVV<0x71038000>;881def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>;882def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>;883def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>;884def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>;885def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>;886def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>;887 888def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>;889def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>;890def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>;891def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>;892def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>;893def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>;894def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>;895def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>;896def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>;897def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>;898def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>;899def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>;900def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>;901def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>;902def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>;903def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>;904 905def VCLO_B : LSX2R_VV<0x729c0000>;906def VCLO_H : LSX2R_VV<0x729c0400>;907def VCLO_W : LSX2R_VV<0x729c0800>;908def VCLO_D : LSX2R_VV<0x729c0c00>;909def VCLZ_B : LSX2R_VV<0x729c1000>;910def VCLZ_H : LSX2R_VV<0x729c1400>;911def VCLZ_W : LSX2R_VV<0x729c1800>;912def VCLZ_D : LSX2R_VV<0x729c1c00>;913 914def VPCNT_B : LSX2R_VV<0x729c2000>;915def VPCNT_H : LSX2R_VV<0x729c2400>;916def VPCNT_W : LSX2R_VV<0x729c2800>;917def VPCNT_D : LSX2R_VV<0x729c2c00>;918 919def VBITCLR_B : LSX3R_VVV<0x710c0000>;920def VBITCLR_H : LSX3R_VVV<0x710c8000>;921def VBITCLR_W : LSX3R_VVV<0x710d0000>;922def VBITCLR_D : LSX3R_VVV<0x710d8000>;923def VBITCLRI_B : LSX2RI3_VVI<0x73102000>;924def VBITCLRI_H : LSX2RI4_VVI<0x73104000>;925def VBITCLRI_W : LSX2RI5_VVI<0x73108000>;926def VBITCLRI_D : LSX2RI6_VVI<0x73110000>;927 928def VBITSET_B : LSX3R_VVV<0x710e0000>;929def VBITSET_H : LSX3R_VVV<0x710e8000>;930def VBITSET_W : LSX3R_VVV<0x710f0000>;931def VBITSET_D : LSX3R_VVV<0x710f8000>;932def VBITSETI_B : LSX2RI3_VVI<0x73142000>;933def VBITSETI_H : LSX2RI4_VVI<0x73144000>;934def VBITSETI_W : LSX2RI5_VVI<0x73148000>;935def VBITSETI_D : LSX2RI6_VVI<0x73150000>;936 937def VBITREV_B : LSX3R_VVV<0x71100000>;938def VBITREV_H : LSX3R_VVV<0x71108000>;939def VBITREV_W : LSX3R_VVV<0x71110000>;940def VBITREV_D : LSX3R_VVV<0x71118000>;941def VBITREVI_B : LSX2RI3_VVI<0x73182000>;942def VBITREVI_H : LSX2RI4_VVI<0x73184000>;943def VBITREVI_W : LSX2RI5_VVI<0x73188000>;944def VBITREVI_D : LSX2RI6_VVI<0x73190000>;945 946def VFRSTP_B : LSX3R_VVVV<0x712b0000>;947def VFRSTP_H : LSX3R_VVVV<0x712b8000>;948def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>;949def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>;950 951def VFADD_S : LSX3R_VVV<0x71308000>;952def VFADD_D : LSX3R_VVV<0x71310000>;953def VFSUB_S : LSX3R_VVV<0x71328000>;954def VFSUB_D : LSX3R_VVV<0x71330000>;955def VFMUL_S : LSX3R_VVV<0x71388000>;956def VFMUL_D : LSX3R_VVV<0x71390000>;957def VFDIV_S : LSX3R_VVV<0x713a8000>;958def VFDIV_D : LSX3R_VVV<0x713b0000>;959 960def VFMADD_S : LSX4R_VVVV<0x09100000>;961def VFMADD_D : LSX4R_VVVV<0x09200000>;962def VFMSUB_S : LSX4R_VVVV<0x09500000>;963def VFMSUB_D : LSX4R_VVVV<0x09600000>;964def VFNMADD_S : LSX4R_VVVV<0x09900000>;965def VFNMADD_D : LSX4R_VVVV<0x09a00000>;966def VFNMSUB_S : LSX4R_VVVV<0x09d00000>;967def VFNMSUB_D : LSX4R_VVVV<0x09e00000>;968 969def VFMAX_S : LSX3R_VVV<0x713c8000>;970def VFMAX_D : LSX3R_VVV<0x713d0000>;971def VFMIN_S : LSX3R_VVV<0x713e8000>;972def VFMIN_D : LSX3R_VVV<0x713f0000>;973 974def VFMAXA_S : LSX3R_VVV<0x71408000>;975def VFMAXA_D : LSX3R_VVV<0x71410000>;976def VFMINA_S : LSX3R_VVV<0x71428000>;977def VFMINA_D : LSX3R_VVV<0x71430000>;978 979def VFLOGB_S : LSX2R_VV<0x729cc400>;980def VFLOGB_D : LSX2R_VV<0x729cc800>;981 982def VFCLASS_S : LSX2R_VV<0x729cd400>;983def VFCLASS_D : LSX2R_VV<0x729cd800>;984 985def VFSQRT_S : LSX2R_VV<0x729ce400>;986def VFSQRT_D : LSX2R_VV<0x729ce800>;987def VFRECIP_S : LSX2R_VV<0x729cf400>;988def VFRECIP_D : LSX2R_VV<0x729cf800>;989def VFRSQRT_S : LSX2R_VV<0x729d0400>;990def VFRSQRT_D : LSX2R_VV<0x729d0800>;991def VFRECIPE_S : LSX2R_VV<0x729d1400>;992def VFRECIPE_D : LSX2R_VV<0x729d1800>;993def VFRSQRTE_S : LSX2R_VV<0x729d2400>;994def VFRSQRTE_D : LSX2R_VV<0x729d2800>;995 996def VFCVTL_S_H : LSX2R_VV<0x729de800>;997def VFCVTH_S_H : LSX2R_VV<0x729dec00>;998def VFCVTL_D_S : LSX2R_VV<0x729df000>;999def VFCVTH_D_S : LSX2R_VV<0x729df400>;1000def VFCVT_H_S : LSX3R_VVV<0x71460000>;1001def VFCVT_S_D : LSX3R_VVV<0x71468000>;1002 1003def VFRINTRNE_S : LSX2R_VV<0x729d7400>;1004def VFRINTRNE_D : LSX2R_VV<0x729d7800>;1005def VFRINTRZ_S : LSX2R_VV<0x729d6400>;1006def VFRINTRZ_D : LSX2R_VV<0x729d6800>;1007def VFRINTRP_S : LSX2R_VV<0x729d5400>;1008def VFRINTRP_D : LSX2R_VV<0x729d5800>;1009def VFRINTRM_S : LSX2R_VV<0x729d4400>;1010def VFRINTRM_D : LSX2R_VV<0x729d4800>;1011def VFRINT_S : LSX2R_VV<0x729d3400>;1012def VFRINT_D : LSX2R_VV<0x729d3800>;1013 1014def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>;1015def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>;1016def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>;1017def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>;1018def VFTINTRP_W_S : LSX2R_VV<0x729e4000>;1019def VFTINTRP_L_D : LSX2R_VV<0x729e4400>;1020def VFTINTRM_W_S : LSX2R_VV<0x729e3800>;1021def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>;1022def VFTINT_W_S : LSX2R_VV<0x729e3000>;1023def VFTINT_L_D : LSX2R_VV<0x729e3400>;1024def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>;1025def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>;1026def VFTINT_WU_S : LSX2R_VV<0x729e5800>;1027def VFTINT_LU_D : LSX2R_VV<0x729e5c00>;1028 1029def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>;1030def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>;1031def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>;1032def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>;1033def VFTINT_W_D : LSX3R_VVV<0x71498000>;1034 1035def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>;1036def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>;1037def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>;1038def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>;1039def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>;1040def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>;1041def VFTINTRML_L_S : LSX2R_VV<0x729e8800>;1042def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>;1043def VFTINTL_L_S : LSX2R_VV<0x729e8000>;1044def VFTINTH_L_S : LSX2R_VV<0x729e8400>;1045 1046def VFFINT_S_W : LSX2R_VV<0x729e0000>;1047def VFFINT_D_L : LSX2R_VV<0x729e0800>;1048def VFFINT_S_WU : LSX2R_VV<0x729e0400>;1049def VFFINT_D_LU : LSX2R_VV<0x729e0c00>;1050def VFFINTL_D_W : LSX2R_VV<0x729e1000>;1051def VFFINTH_D_W : LSX2R_VV<0x729e1400>;1052def VFFINT_S_L : LSX3R_VVV<0x71480000>;1053 1054def VSEQ_B : LSX3R_VVV<0x70000000>;1055def VSEQ_H : LSX3R_VVV<0x70008000>;1056def VSEQ_W : LSX3R_VVV<0x70010000>;1057def VSEQ_D : LSX3R_VVV<0x70018000>;1058def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>;1059def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>;1060def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>;1061def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>;1062 1063def VSLE_B : LSX3R_VVV<0x70020000>;1064def VSLE_H : LSX3R_VVV<0x70028000>;1065def VSLE_W : LSX3R_VVV<0x70030000>;1066def VSLE_D : LSX3R_VVV<0x70038000>;1067def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>;1068def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>;1069def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>;1070def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>;1071 1072def VSLE_BU : LSX3R_VVV<0x70040000>;1073def VSLE_HU : LSX3R_VVV<0x70048000>;1074def VSLE_WU : LSX3R_VVV<0x70050000>;1075def VSLE_DU : LSX3R_VVV<0x70058000>;1076def VSLEI_BU : LSX2RI5_VVI<0x72840000>;1077def VSLEI_HU : LSX2RI5_VVI<0x72848000>;1078def VSLEI_WU : LSX2RI5_VVI<0x72850000>;1079def VSLEI_DU : LSX2RI5_VVI<0x72858000>;1080 1081def VSLT_B : LSX3R_VVV<0x70060000>;1082def VSLT_H : LSX3R_VVV<0x70068000>;1083def VSLT_W : LSX3R_VVV<0x70070000>;1084def VSLT_D : LSX3R_VVV<0x70078000>;1085def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>;1086def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>;1087def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>;1088def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>;1089 1090def VSLT_BU : LSX3R_VVV<0x70080000>;1091def VSLT_HU : LSX3R_VVV<0x70088000>;1092def VSLT_WU : LSX3R_VVV<0x70090000>;1093def VSLT_DU : LSX3R_VVV<0x70098000>;1094def VSLTI_BU : LSX2RI5_VVI<0x72880000>;1095def VSLTI_HU : LSX2RI5_VVI<0x72888000>;1096def VSLTI_WU : LSX2RI5_VVI<0x72890000>;1097def VSLTI_DU : LSX2RI5_VVI<0x72898000>;1098 1099def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>;1100def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>;1101def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>;1102def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>;1103def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>;1104def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>;1105def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>;1106def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>;1107def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>;1108def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>;1109def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>;1110def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>;1111def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>;1112def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>;1113def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>;1114def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>;1115def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>;1116def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>;1117def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>;1118def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>;1119def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>;1120def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>;1121 1122def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>;1123def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>;1124def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>;1125def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>;1126def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>;1127def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>;1128def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>;1129def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>;1130def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>;1131def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>;1132def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>;1133def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>;1134def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>;1135def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>;1136def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>;1137def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>;1138def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>;1139def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>;1140def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>;1141def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>;1142def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>;1143def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>;1144 1145def VBITSEL_V : LSX4R_VVVV<0x0d100000>;1146 1147def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>;1148 1149def VSETEQZ_V : LSX2R_CV<0x729c9800>;1150def VSETNEZ_V : LSX2R_CV<0x729c9c00>;1151def VSETANYEQZ_B : LSX2R_CV<0x729ca000>;1152def VSETANYEQZ_H : LSX2R_CV<0x729ca400>;1153def VSETANYEQZ_W : LSX2R_CV<0x729ca800>;1154def VSETANYEQZ_D : LSX2R_CV<0x729cac00>;1155def VSETALLNEZ_B : LSX2R_CV<0x729cb000>;1156def VSETALLNEZ_H : LSX2R_CV<0x729cb400>;1157def VSETALLNEZ_W : LSX2R_CV<0x729cb800>;1158def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>;1159 1160def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>;1161def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>;1162def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>;1163def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>;1164def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>;1165def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>;1166def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>;1167def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>;1168def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>;1169def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>;1170def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>;1171def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>;1172 1173def VREPLGR2VR_B : LSX2R_VR<0x729f0000>;1174def VREPLGR2VR_H : LSX2R_VR<0x729f0400>;1175def VREPLGR2VR_W : LSX2R_VR<0x729f0800>;1176def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>;1177 1178def VREPLVE_B : LSX3R_VVR<0x71220000>;1179def VREPLVE_H : LSX3R_VVR<0x71228000>;1180def VREPLVE_W : LSX3R_VVR<0x71230000>;1181def VREPLVE_D : LSX3R_VVR<0x71238000>;1182def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>;1183def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>;1184def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>;1185def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>;1186 1187def VBSLL_V : LSX2RI5_VVI<0x728e0000>;1188def VBSRL_V : LSX2RI5_VVI<0x728e8000>;1189 1190def VPACKEV_B : LSX3R_VVV<0x71160000>;1191def VPACKEV_H : LSX3R_VVV<0x71168000>;1192def VPACKEV_W : LSX3R_VVV<0x71170000>;1193def VPACKEV_D : LSX3R_VVV<0x71178000>;1194def VPACKOD_B : LSX3R_VVV<0x71180000>;1195def VPACKOD_H : LSX3R_VVV<0x71188000>;1196def VPACKOD_W : LSX3R_VVV<0x71190000>;1197def VPACKOD_D : LSX3R_VVV<0x71198000>;1198 1199def VPICKEV_B : LSX3R_VVV<0x711e0000>;1200def VPICKEV_H : LSX3R_VVV<0x711e8000>;1201def VPICKEV_W : LSX3R_VVV<0x711f0000>;1202def VPICKEV_D : LSX3R_VVV<0x711f8000>;1203def VPICKOD_B : LSX3R_VVV<0x71200000>;1204def VPICKOD_H : LSX3R_VVV<0x71208000>;1205def VPICKOD_W : LSX3R_VVV<0x71210000>;1206def VPICKOD_D : LSX3R_VVV<0x71218000>;1207 1208def VILVL_B : LSX3R_VVV<0x711a0000>;1209def VILVL_H : LSX3R_VVV<0x711a8000>;1210def VILVL_W : LSX3R_VVV<0x711b0000>;1211def VILVL_D : LSX3R_VVV<0x711b8000>;1212def VILVH_B : LSX3R_VVV<0x711c0000>;1213def VILVH_H : LSX3R_VVV<0x711c8000>;1214def VILVH_W : LSX3R_VVV<0x711d0000>;1215def VILVH_D : LSX3R_VVV<0x711d8000>;1216 1217def VSHUF_B : LSX4R_VVVV<0x0d500000>;1218 1219def VSHUF_H : LSX3R_VVVV<0x717a8000>;1220def VSHUF_W : LSX3R_VVVV<0x717b0000>;1221def VSHUF_D : LSX3R_VVVV<0x717b8000>;1222 1223def VSHUF4I_B : LSX2RI8_VVI<0x73900000>;1224def VSHUF4I_H : LSX2RI8_VVI<0x73940000>;1225def VSHUF4I_W : LSX2RI8_VVI<0x73980000>;1226def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>;1227 1228def VPERMI_W : LSX2RI8_VVVI<0x73e40000>;1229 1230def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>;1231def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>;1232def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>;1233def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>;1234} // mayLoad = 0, mayStore = 01235 1236let mayLoad = 1, mayStore = 0 in {1237def VLD : LSX2RI12_Load<0x2c000000>;1238def VLDX : LSX3R_Load<0x38400000>;1239 1240def VLDREPL_B : LSX2RI12_Load<0x30800000>;1241def VLDREPL_H : LSX2RI11_Load<0x30400000>;1242def VLDREPL_W : LSX2RI10_Load<0x30200000>;1243def VLDREPL_D : LSX2RI9_Load<0x30100000>;1244} // mayLoad = 1, mayStore = 01245 1246let mayLoad = 0, mayStore = 1 in {1247def VST : LSX2RI12_Store<0x2c400000>;1248def VSTX : LSX3R_Store<0x38440000>;1249 1250def VSTELM_B : LSX2RI8I4_VRII<0x31800000>;1251def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>;1252def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>;1253def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>;1254} // mayLoad = 0, mayStore = 11255 1256} // hasSideEffects = 0, Predicates = [HasExtLSX]1257 1258/// Pseudo-instructions1259 1260let Predicates = [HasExtLSX] in {1261 1262let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,1263 isAsmParserOnly = 1 in {1264def PseudoVREPLI_B : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [],1265 "vrepli.b", "$vd, $imm">;1266def PseudoVREPLI_H : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [],1267 "vrepli.h", "$vd, $imm">;1268def PseudoVREPLI_W : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [],1269 "vrepli.w", "$vd, $imm">;1270def PseudoVREPLI_D : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [],1271 "vrepli.d", "$vd, $imm">;1272}1273 1274def PseudoVBNZ_B : VecCond<loongarch_vall_nonzero, v16i8>;1275def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>;1276def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>;1277def PseudoVBNZ_D : VecCond<loongarch_vall_nonzero, v2i64>;1278def PseudoVBNZ : VecCond<loongarch_vany_nonzero, v16i8>;1279 1280def PseudoVBZ_B : VecCond<loongarch_vall_zero, v16i8>;1281def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>;1282def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>;1283def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>;1284def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>;1285 1286let usesCustomInserter = 1 in1287def PseudoCTPOP : Pseudo<(outs GPR:$rd), (ins GPR:$rj),1288 [(set GPR:$rd, (ctpop GPR:$rj))]>;1289 1290let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {1291def PseudoVMSKLTZ_B : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1292def PseudoVMSKLTZ_H : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1293def PseudoVMSKLTZ_W : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1294def PseudoVMSKLTZ_D : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1295def PseudoVMSKGEZ_B : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1296def PseudoVMSKEQZ_B : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1297def PseudoVMSKNEZ_B : Pseudo<(outs GPR:$rd), (ins LSX128:$vj)>;1298} // usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 01299 1300} // Predicates = [HasExtLSX]1301 1302multiclass PatVr<SDPatternOperator OpNode, string Inst> {1303 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))),1304 (!cast<LAInst>(Inst#"_B") LSX128:$vj)>;1305 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))),1306 (!cast<LAInst>(Inst#"_H") LSX128:$vj)>;1307 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))),1308 (!cast<LAInst>(Inst#"_W") LSX128:$vj)>;1309 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))),1310 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>;1311}1312 1313multiclass PatVrF<SDPatternOperator OpNode, string Inst> {1314 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))),1315 (!cast<LAInst>(Inst#"_S") LSX128:$vj)>;1316 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))),1317 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>;1318}1319 1320multiclass PatVrVr<SDPatternOperator OpNode, string Inst> {1321 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),1322 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;1323 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),1324 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;1325 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),1326 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;1327 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),1328 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;1329}1330 1331multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> {1332 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)),1333 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>;1334 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)),1335 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;1336}1337 1338multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> {1339 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),1340 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>;1341 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),1342 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>;1343 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),1344 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>;1345 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),1346 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>;1347}1348 1349multiclass PatVrSimm5<SDPatternOperator OpNode, string Inst> {1350 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_simm5 simm5:$imm))),1351 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>;1352 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))),1353 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>;1354 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))),1355 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>;1356 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_simm5 simm5:$imm))),1357 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>;1358}1359 1360multiclass PatVrUimm5<SDPatternOperator OpNode, string Inst> {1361 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm5 uimm5:$imm))),1362 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>;1363 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))),1364 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>;1365 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))),1366 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>;1367 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm5 uimm5:$imm))),1368 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>;1369}1370 1371multiclass PatVrVrVr<SDPatternOperator OpNode, string Inst> {1372 def : Pat<(OpNode (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),1373 (!cast<LAInst>(Inst#"_B") LSX128:$vd, LSX128:$vj, LSX128:$vk)>;1374 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),1375 (!cast<LAInst>(Inst#"_H") LSX128:$vd, LSX128:$vj, LSX128:$vk)>;1376 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),1377 (!cast<LAInst>(Inst#"_W") LSX128:$vd, LSX128:$vj, LSX128:$vk)>;1378 def : Pat<(OpNode (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),1379 (!cast<LAInst>(Inst#"_D") LSX128:$vd, LSX128:$vj, LSX128:$vk)>;1380}1381 1382multiclass PatVrVrW<SDPatternOperator OpNode, string Inst> {1383 def : Pat<(OpNode(v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),1384 (!cast<LAInst>(Inst#"_H_B") LSX128:$vj, LSX128:$vk)>;1385 def : Pat<(OpNode(v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),1386 (!cast<LAInst>(Inst#"_W_H") LSX128:$vj, LSX128:$vk)>;1387 def : Pat<(OpNode(v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),1388 (!cast<LAInst>(Inst#"_D_W") LSX128:$vj, LSX128:$vk)>;1389 def : Pat<(OpNode(v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),1390 (!cast<LAInst>(Inst#"_Q_D") LSX128:$vj, LSX128:$vk)>;1391}1392 1393multiclass PatShiftVrVr<SDPatternOperator OpNode, string Inst> {1394 def : Pat<(OpNode (v16i8 LSX128:$vj), (and vsplati8_imm_eq_7,1395 (v16i8 LSX128:$vk))),1396 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;1397 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15,1398 (v8i16 LSX128:$vk))),1399 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;1400 def : Pat<(OpNode (v4i32 LSX128:$vj), (and vsplati32_imm_eq_31,1401 (v4i32 LSX128:$vk))),1402 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;1403 def : Pat<(OpNode (v2i64 LSX128:$vj), (and vsplati64_imm_eq_63,1404 (v2i64 LSX128:$vk))),1405 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;1406}1407 1408multiclass PatShiftVrSplatUimm<SDPatternOperator OpNode, string Inst> {1409 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm3 uimm3:$imm))),1410 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>;1411 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))),1412 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>;1413 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))),1414 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>;1415 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm6 uimm6:$imm))),1416 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>;1417}1418 1419multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> {1420 def : Pat<(OpNode(v16i8 LSX128:$vj), uimm3:$imm),1421 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>;1422 def : Pat<(OpNode(v8i16 LSX128:$vj), uimm4:$imm),1423 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>;1424 def : Pat<(OpNode(v4i32 LSX128:$vj), uimm5:$imm),1425 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>;1426 def : Pat<(OpNode(v2i64 LSX128:$vj), uimm6:$imm),1427 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>;1428}1429 1430multiclass PatCCVrSimm5<CondCode CC, string Inst> {1431 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),1432 (v16i8 (SplatPat_simm5 simm5:$imm)), CC)),1433 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>;1434 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),1435 (v8i16 (SplatPat_simm5 simm5:$imm)), CC)),1436 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>;1437 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),1438 (v4i32 (SplatPat_simm5 simm5:$imm)), CC)),1439 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>;1440 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),1441 (v2i64 (SplatPat_simm5 simm5:$imm)), CC)),1442 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>;1443}1444 1445multiclass PatCCVrUimm5<CondCode CC, string Inst> {1446 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),1447 (v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)),1448 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>;1449 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),1450 (v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)),1451 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>;1452 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),1453 (v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)),1454 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>;1455 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),1456 (v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)),1457 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>;1458}1459 1460multiclass PatCCVrVr<CondCode CC, string Inst> {1461 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),1462 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;1463 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),1464 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;1465 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),1466 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;1467 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),1468 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;1469}1470 1471multiclass PatCCVrVrU<CondCode CC, string Inst> {1472 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),1473 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>;1474 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),1475 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>;1476 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),1477 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>;1478 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),1479 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>;1480}1481 1482multiclass PatCCVrVrF<CondCode CC, string Inst> {1483 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)),1484 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>;1485 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)),1486 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;1487}1488 1489multiclass VldreplPat<ValueType vt, LAInst Inst, Operand ImmOpnd> {1490 def : Pat<(vt(loongarch_vldrepl BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;1491 def : Pat<(vt(loongarch_vldrepl(AddrConstant GPR:$rj, ImmOpnd:$imm))),1492 (Inst GPR:$rj, ImmOpnd:$imm)>;1493 def : Pat<(vt(loongarch_vldrepl(AddLike BaseAddr:$rj, ImmOpnd:$imm))),1494 (Inst BaseAddr:$rj, ImmOpnd:$imm)>;1495}1496 1497multiclass VstelmPat<PatFrag StoreOp, ValueType vt, LAInst Inst,1498 Operand ImmOpnd, Operand IdxOpnd, ValueType elt = GRLenVT> {1499 def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)), BaseAddr:$rj),1500 (Inst vt:$vd, BaseAddr:$rj, 0, IdxOpnd:$idx)>;1501 1502 def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)),1503 (AddrConstant GPR:$rj, ImmOpnd:$imm)),1504 (Inst vt:$vd, GPR:$rj, ImmOpnd:$imm, IdxOpnd:$idx)>;1505 1506 def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)),1507 (AddLike BaseAddr:$rj, ImmOpnd:$imm)),1508 (Inst vt:$vd, BaseAddr:$rj, ImmOpnd:$imm, IdxOpnd:$idx)>;1509}1510 1511multiclass InsertExtractPatV4<ValueType vecty, ValueType elemty> {1512 foreach imm1 = 0...3 in {1513 foreach imm2 = 0...3 in {1514 defvar Imm = !or(!shl(imm2, 4), imm1);1515 def : Pat<(vector_insert vecty:$vd,1516 (elemty (vector_extract vecty:$vj, imm1)), imm2),1517 (VEXTRINS_W $vd, $vj, Imm)>;1518 }1519 }1520}1521 1522multiclass InsertExtractPatV2<ValueType vecty, ValueType elemty> {1523 foreach imm1 = 0...1 in {1524 foreach imm2 = 0...1 in {1525 defvar Imm = !or(!shl(imm2, 4), imm1);1526 def : Pat<(vector_insert vecty:$vd,1527 (elemty (vector_extract vecty:$vj, imm1)), imm2),1528 (VEXTRINS_D $vd, $vj, Imm)>;1529 }1530 }1531}1532 1533multiclass VAvgPat<SDPatternOperator OpNode, string Inst, ValueType vt> {1534 def : Pat<(OpNode (vt (add vt:$vj, vt:$vk)), (vt (vsplat_imm_eq_1))),1535 (!cast<LAInst>(Inst) vt:$vj, vt:$vk)>;1536}1537 1538multiclass VAvgrPat<SDPatternOperator OpNode, string Inst, ValueType vt> {1539 def : Pat<(OpNode (vt (add (vt (add vt:$vj, vt:$vk)),1540 (vt (vsplat_imm_eq_1)))),1541 (vt (vsplat_imm_eq_1))),1542 (!cast<LAInst>(Inst) vt:$vj, vt:$vk)>;1543}1544 1545let Predicates = [HasExtLSX] in {1546 1547// VADD_{B/H/W/D}1548defm : PatVrVr<add, "VADD">;1549// VSUB_{B/H/W/D}1550defm : PatVrVr<sub, "VSUB">;1551 1552// VADDI_{B/H/W/D}U1553defm : PatVrUimm5<add, "VADDI">;1554// VSUBI_{B/H/W/D}U1555defm : PatVrUimm5<sub, "VSUBI">;1556 1557// VNEG_{B/H/W/D}1558def : Pat<(sub immAllZerosV, (v16i8 LSX128:$vj)), (VNEG_B LSX128:$vj)>;1559def : Pat<(sub immAllZerosV, (v8i16 LSX128:$vj)), (VNEG_H LSX128:$vj)>;1560def : Pat<(sub immAllZerosV, (v4i32 LSX128:$vj)), (VNEG_W LSX128:$vj)>;1561def : Pat<(sub immAllZerosV, (v2i64 LSX128:$vj)), (VNEG_D LSX128:$vj)>;1562 1563// VMAX[I]_{B/H/W/D}[U]1564defm : PatVrVr<smax, "VMAX">;1565defm : PatVrVrU<umax, "VMAX">;1566defm : PatVrSimm5<smax, "VMAXI">;1567defm : PatVrUimm5<umax, "VMAXI">;1568 1569// VMIN[I]_{B/H/W/D}[U]1570defm : PatVrVr<smin, "VMIN">;1571defm : PatVrVrU<umin, "VMIN">;1572defm : PatVrSimm5<smin, "VMINI">;1573defm : PatVrUimm5<umin, "VMINI">;1574 1575// VMUL_{B/H/W/D}1576defm : PatVrVr<mul, "VMUL">;1577 1578// VMUH_{B/H/W/D}[U]1579defm : PatVrVr<mulhs, "VMUH">;1580defm : PatVrVrU<mulhu, "VMUH">;1581 1582// VMADD_{B/H/W/D}1583defm : PatVrVrVr<muladd, "VMADD">;1584// VMSUB_{B/H/W/D}1585defm : PatVrVrVr<mulsub, "VMSUB">;1586 1587// VDIV_{B/H/W/D}[U]1588defm : PatVrVr<sdiv, "VDIV">;1589defm : PatVrVrU<udiv, "VDIV">;1590 1591// VMOD_{B/H/W/D}[U]1592defm : PatVrVr<srem, "VMOD">;1593defm : PatVrVrU<urem, "VMOD">;1594 1595// VAND_V1596foreach vt = [v16i8, v8i16, v4i32, v2i64] in1597def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)),1598 (VAND_V LSX128:$vj, LSX128:$vk)>;1599// VOR_V1600foreach vt = [v16i8, v8i16, v4i32, v2i64] in1601def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)),1602 (VOR_V LSX128:$vj, LSX128:$vk)>;1603// VXOR_V1604foreach vt = [v16i8, v8i16, v4i32, v2i64] in1605def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)),1606 (VXOR_V LSX128:$vj, LSX128:$vk)>;1607// VNOR_V1608foreach vt = [v16i8, v8i16, v4i32, v2i64] in1609def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))),1610 (VNOR_V LSX128:$vj, LSX128:$vk)>;1611// VANDN_V1612foreach vt = [v16i8, v8i16, v4i32, v2i64] in1613def : Pat<(loongarch_vandn (vt LSX128:$vj), (vt LSX128:$vk)),1614 (VANDN_V LSX128:$vj, LSX128:$vk)>;1615// VORN_V1616foreach vt = [v16i8, v8i16, v4i32, v2i64] in1617def : Pat<(or (vt LSX128:$vj), (vt (vnot LSX128:$vk))),1618 (VORN_V LSX128:$vj, LSX128:$vk)>;1619 1620// VANDI_B1621def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))),1622 (VANDI_B LSX128:$vj, uimm8:$imm)>;1623// VORI_B1624def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))),1625 (VORI_B LSX128:$vj, uimm8:$imm)>;1626// VXORI_B1627def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))),1628 (VXORI_B LSX128:$vj, uimm8:$imm)>;1629// VNORI_B1630def : Pat<(vnot (or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm)))),1631 (VNORI_B LSX128:$vj, uimm8:$imm)>;1632 1633// VBSLL_V1634foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32,1635 v2f64] in def : Pat<(loongarch_vbsll(vt LSX128:$vj), uimm5:$imm),1636 (VBSLL_V LSX128:$vj, uimm5:$imm)>;1637 1638// VBSRL_V1639foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32,1640 v2f64] in def : Pat<(loongarch_vbsrl(vt LSX128:$vj), uimm5:$imm),1641 (VBSRL_V LSX128:$vj, uimm5:$imm)>;1642 1643// VSLL[I]_{B/H/W/D}1644defm : PatVrVr<shl, "VSLL">;1645defm : PatShiftVrVr<shl, "VSLL">;1646defm : PatShiftVrSplatUimm<shl, "VSLLI">;1647defm : PatShiftVrUimm<loongarch_vslli, "VSLLI">;1648 1649// VSRL[I]_{B/H/W/D}1650defm : PatVrVr<srl, "VSRL">;1651defm : PatShiftVrVr<srl, "VSRL">;1652defm : PatShiftVrSplatUimm<srl, "VSRLI">;1653defm : PatShiftVrUimm<loongarch_vsrli, "VSRLI">;1654 1655// VSRA[I]_{B/H/W/D}1656defm : PatVrVr<sra, "VSRA">;1657defm : PatShiftVrVr<sra, "VSRA">;1658defm : PatShiftVrSplatUimm<sra, "VSRAI">;1659 1660// VROTR[I]_{B/H/W/D}1661defm : PatVrVr<rotr, "VROTR">;1662defm : PatShiftVrVr<rotr, "VROTR">;1663defm : PatShiftVrSplatUimm<rotr, "VROTRI">;1664 1665// VCLZ_{B/H/W/D}1666defm : PatVr<ctlz, "VCLZ">;1667 1668// VPCNT_{B/H/W/D}1669defm : PatVr<ctpop, "VPCNT">;1670 1671// VBITCLR_{B/H/W/D}1672def : Pat<(loongarch_vandn (v16i8 (shl vsplat_imm_eq_1, v16i8:$vk)), v16i8:$vj),1673 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>;1674def : Pat<(loongarch_vandn (v8i16 (shl vsplat_imm_eq_1, v8i16:$vk)), v8i16:$vj),1675 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>;1676def : Pat<(loongarch_vandn (v4i32 (shl vsplat_imm_eq_1, v4i32:$vk)), v4i32:$vj),1677 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>;1678def : Pat<(loongarch_vandn (v2i64 (shl vsplat_imm_eq_1, v2i64:$vk)), v2i64:$vj),1679 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>;1680def : Pat<(loongarch_vandn (v16i8 (shl vsplat_imm_eq_1,1681 (vsplati8imm7 v16i8:$vk))), v16i8:$vj),1682 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>;1683def : Pat<(loongarch_vandn (v8i16 (shl vsplat_imm_eq_1,1684 (vsplati16imm15 v8i16:$vk))), v8i16:$vj),1685 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>;1686def : Pat<(loongarch_vandn (v4i32 (shl vsplat_imm_eq_1,1687 (vsplati32imm31 v4i32:$vk))), v4i32:$vj),1688 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>;1689def : Pat<(loongarch_vandn (v2i64 (shl vsplat_imm_eq_1,1690 (vsplati64imm63 v2i64:$vk))), v2i64:$vj),1691 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>;1692 1693// VBITCLRI_{B/H/W/D}1694def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_inv_pow2 uimm3:$imm))),1695 (VBITCLRI_B LSX128:$vj, uimm3:$imm)>;1696def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))),1697 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>;1698def : Pat<(and (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_inv_pow2 uimm5:$imm))),1699 (VBITCLRI_W LSX128:$vj, uimm5:$imm)>;1700def : Pat<(and (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_inv_pow2 uimm6:$imm))),1701 (VBITCLRI_D LSX128:$vj, uimm6:$imm)>;1702 1703// VBITSET_{B/H/W/D}1704def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)),1705 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>;1706def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)),1707 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>;1708def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)),1709 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>;1710def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)),1711 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>;1712def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))),1713 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>;1714def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))),1715 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>;1716def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))),1717 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>;1718def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))),1719 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>;1720 1721// VBITSETI_{B/H/W/D}1722def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))),1723 (VBITSETI_B LSX128:$vj, uimm3:$imm)>;1724def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))),1725 (VBITSETI_H LSX128:$vj, uimm4:$imm)>;1726def : Pat<(or (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))),1727 (VBITSETI_W LSX128:$vj, uimm5:$imm)>;1728def : Pat<(or (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))),1729 (VBITSETI_D LSX128:$vj, uimm6:$imm)>;1730 1731// VBITREV_{B/H/W/D}1732def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)),1733 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>;1734def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)),1735 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>;1736def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)),1737 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>;1738def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)),1739 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>;1740def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))),1741 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>;1742def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))),1743 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>;1744def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))),1745 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>;1746def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))),1747 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>;1748 1749// VBITREVI_{B/H/W/D}1750def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))),1751 (VBITREVI_B LSX128:$vj, uimm3:$imm)>;1752def : Pat<(xor (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))),1753 (VBITREVI_H LSX128:$vj, uimm4:$imm)>;1754def : Pat<(xor (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))),1755 (VBITREVI_W LSX128:$vj, uimm5:$imm)>;1756def : Pat<(xor (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))),1757 (VBITREVI_D LSX128:$vj, uimm6:$imm)>;1758 1759// Vector bswaps1760def : Pat<(bswap (v8i16 LSX128:$vj)), (VSHUF4I_B LSX128:$vj, 0b10110001)>;1761def : Pat<(bswap (v4i32 LSX128:$vj)), (VSHUF4I_B LSX128:$vj, 0b00011011)>;1762def : Pat<(bswap (v2i64 LSX128:$vj)),1763 (VSHUF4I_W (VSHUF4I_B LSX128:$vj, 0b00011011), 0b10110001)>;1764 1765// VHADDW_{H_B/W_H/D_W/Q_D}1766defm : PatVrVrW<loongarch_vhaddw, "VHADDW">;1767 1768// VFADD_{S/D}1769defm : PatVrVrF<fadd, "VFADD">;1770 1771// VFSUB_{S/D}1772defm : PatVrVrF<fsub, "VFSUB">;1773 1774// VFMUL_{S/D}1775defm : PatVrVrF<fmul, "VFMUL">;1776 1777// VFDIV_{S/D}1778defm : PatVrVrF<fdiv, "VFDIV">;1779 1780// VFMAX_{S/D}, VFMIN_{S/D}1781defm : PatVrVrF<fmaxnum, "VFMAX">;1782defm : PatVrVrF<fminnum, "VFMIN">;1783 1784// VFMADD_{S/D}1785def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va),1786 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1787def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va),1788 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1789 1790// VFMSUB_{S/D}1791def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)),1792 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1793def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)),1794 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1795 1796// VFNMADD_{S/D}1797def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)),1798 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1799def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)),1800 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1801def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)),1802 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1803def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)),1804 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1805 1806// VFNMSUB_{S/D}1807def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))),1808 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1809def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))),1810 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1811def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va),1812 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;1813def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va),1814 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;1815 1816// VFSQRT_{S/D}1817defm : PatVrF<fsqrt, "VFSQRT">;1818 1819// VFLOGB_{S/D}1820defm : PatVrF<flog2, "VFLOGB">;1821 1822// VFRECIP_{S/D}1823def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj),1824 (VFRECIP_S v4f32:$vj)>;1825def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj),1826 (VFRECIP_D v2f64:$vj)>;1827 1828// VFRSQRT_{S/D}1829def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)),1830 (VFRSQRT_S v4f32:$vj)>;1831def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)),1832 (VFRSQRT_D v2f64:$vj)>;1833 1834// VSEQ[I]_{B/H/W/D}1835defm : PatCCVrSimm5<SETEQ, "VSEQI">;1836defm : PatCCVrVr<SETEQ, "VSEQ">;1837 1838// VSLE[I]_{B/H/W/D}[U]1839defm : PatCCVrSimm5<SETLE, "VSLEI">;1840defm : PatCCVrUimm5<SETULE, "VSLEI">;1841defm : PatCCVrVr<SETLE, "VSLE">;1842defm : PatCCVrVrU<SETULE, "VSLE">;1843 1844// VSLT[I]_{B/H/W/D}[U]1845defm : PatCCVrSimm5<SETLT, "VSLTI">;1846defm : PatCCVrUimm5<SETULT, "VSLTI">;1847defm : PatCCVrVr<SETLT, "VSLT">;1848defm : PatCCVrVrU<SETULT, "VSLT">;1849 1850// VFCMP.cond.{S/D}1851defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">;1852defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">;1853defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">;1854 1855defm : PatCCVrVrF<SETLE, "VFCMP_CLE">;1856defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">;1857defm : PatCCVrVrF<SETULE, "VFCMP_CULE">;1858 1859defm : PatCCVrVrF<SETLT, "VFCMP_CLT">;1860defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">;1861defm : PatCCVrVrF<SETULT, "VFCMP_CULT">;1862 1863defm : PatCCVrVrF<SETNE, "VFCMP_CNE">;1864defm : PatCCVrVrF<SETONE, "VFCMP_CNE">;1865defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">;1866 1867defm : PatCCVrVrF<SETO, "VFCMP_COR">;1868defm : PatCCVrVrF<SETUO, "VFCMP_CUN">;1869 1870// Insert element extracted from vector into vector.1871// VPICKVE2GR_{B/H/W/D} + VINSGR2VR_{B/H/W/D} -> VEXTRINS_{B/H/W/D}1872foreach imm1 = 0...15 in {1873 foreach imm2 = 0...15 in {1874 defvar Imm = !or(!shl(imm2, 4), imm1);1875 def : Pat<(vector_insert v16i8:$vd,1876 (GRLenVT (vector_extract v16i8:$vj, imm1)), imm2),1877 (VEXTRINS_B $vd, $vj, Imm)>;1878 }1879}1880 1881foreach imm1 = 0...7 in {1882 foreach imm2 = 0...7 in {1883 defvar Imm = !or(!shl(imm2, 4), imm1);1884 def : Pat<(vector_insert v8i16:$vd,1885 (GRLenVT (vector_extract v8i16:$vj, imm1)), imm2),1886 (VEXTRINS_H $vd, $vj, Imm)>;1887 }1888}1889 1890defm : InsertExtractPatV4<v4i32, GRLenVT>;1891defm : InsertExtractPatV4<v4f32, f32>;1892defm : InsertExtractPatV2<v2i64, GRLenVT>;1893defm : InsertExtractPatV2<v2f64, f64>;1894 1895// VINSGR2VR_{B/H/W/D}1896def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm),1897 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>;1898def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm),1899 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>;1900def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm),1901 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>;1902def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm),1903 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>;1904def : Pat<(vector_insert v4f32:$vd, (loongarch_movgr2fr_w_la64 GPR:$rj), uimm2:$imm),1905 (VINSGR2VR_W $vd, $rj, uimm2:$imm)>;1906def : Pat<(vector_insert v2f64:$vd, (f64 (bitconvert i64:$rj)), uimm1:$imm),1907 (VINSGR2VR_D $vd, $rj, uimm1:$imm)>;1908 1909// VEXTRINS_{W/D}1910foreach imm = 0...3 in {1911 defvar Imm = !shl(imm, 4);1912 def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, imm),1913 (VEXTRINS_W $vd, (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), Imm)>;1914}1915 1916foreach imm = 0...1 in {1917 defvar Imm = !shl(imm, 4);1918 def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, imm),1919 (VEXTRINS_D $vd, (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), Imm)>;1920}1921 1922// scalar_to_vector1923def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)),1924 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;1925def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)),1926 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;1927 1928// VPICKVE2GR_{B/H/W}[U]1929def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8),1930 (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>;1931def : Pat<(loongarch_vpick_sext_elt v8i16:$vd, uimm3:$imm, i16),1932 (VPICKVE2GR_H v8i16:$vd, uimm3:$imm)>;1933def : Pat<(loongarch_vpick_sext_elt v4i32:$vd, uimm2:$imm, i32),1934 (VPICKVE2GR_W v4i32:$vd, uimm2:$imm)>;1935 1936def : Pat<(loongarch_vpick_zext_elt v16i8:$vd, uimm4:$imm, i8),1937 (VPICKVE2GR_BU v16i8:$vd, uimm4:$imm)>;1938def : Pat<(loongarch_vpick_zext_elt v8i16:$vd, uimm3:$imm, i16),1939 (VPICKVE2GR_HU v8i16:$vd, uimm3:$imm)>;1940def : Pat<(loongarch_vpick_zext_elt v4i32:$vd, uimm2:$imm, i32),1941 (VPICKVE2GR_WU v4i32:$vd, uimm2:$imm)>;1942 1943// VREPLGR2VR_{B/H/W/D}1944def : Pat<(lsxsplati8 GPR:$rj), (VREPLGR2VR_B GPR:$rj)>;1945def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>;1946def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>;1947def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>;1948 1949def : Pat<(v16i8 (loongarch_vreplgr2vr GRLenVT:$rj)),1950 (v16i8 (VREPLGR2VR_B GRLenVT:$rj))>;1951def : Pat<(v8i16 (loongarch_vreplgr2vr GRLenVT:$rj)),1952 (v8i16 (VREPLGR2VR_H GRLenVT:$rj))>;1953def : Pat<(v4i32 (loongarch_vreplgr2vr GRLenVT:$rj)),1954 (v4i32 (VREPLGR2VR_W GRLenVT:$rj))>;1955def : Pat<(v2i64 (loongarch_vreplgr2vr GRLenVT:$rj)),1956 (v2i64 (VREPLGR2VR_D GRLenVT:$rj))>;1957 1958// VREPLVE_{B/H/W/D}1959def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk),1960 (VREPLVE_B v16i8:$vj, GRLenVT:$rk)>;1961def : Pat<(loongarch_vreplve v8i16:$vj, GRLenVT:$rk),1962 (VREPLVE_H v8i16:$vj, GRLenVT:$rk)>;1963def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk),1964 (VREPLVE_W v4i32:$vj, GRLenVT:$rk)>;1965def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk),1966 (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>;1967 1968// VSHUF_{B/H/W/D}1969def : Pat<(loongarch_vshuf v16i8:$va, v16i8:$vj, v16i8:$vk),1970 (VSHUF_B v16i8:$vj, v16i8:$vk, v16i8:$va)>;1971def : Pat<(loongarch_vshuf v8i16:$vd, v8i16:$vj, v8i16:$vk),1972 (VSHUF_H v8i16:$vd, v8i16:$vj, v8i16:$vk)>;1973def : Pat<(loongarch_vshuf v4i32:$vd, v4i32:$vj, v4i32:$vk),1974 (VSHUF_W v4i32:$vd, v4i32:$vj, v4i32:$vk)>;1975def : Pat<(loongarch_vshuf v2i64:$vd, v2i64:$vj, v2i64:$vk),1976 (VSHUF_D v2i64:$vd, v2i64:$vj, v2i64:$vk)>;1977def : Pat<(loongarch_vshuf v4i32:$vd, v4f32:$vj, v4f32:$vk),1978 (VSHUF_W v4i32:$vd, v4f32:$vj, v4f32:$vk)>;1979def : Pat<(loongarch_vshuf v2i64:$vd, v2f64:$vj, v2f64:$vk),1980 (VSHUF_D v2i64:$vd, v2f64:$vj, v2f64:$vk)>;1981 1982// VPICKEV_{B/H/W/D}1983def : Pat<(loongarch_vpickev v16i8:$vj, v16i8:$vk),1984 (VPICKEV_B v16i8:$vj, v16i8:$vk)>;1985def : Pat<(loongarch_vpickev v8i16:$vj, v8i16:$vk),1986 (VPICKEV_H v8i16:$vj, v8i16:$vk)>;1987def : Pat<(loongarch_vpickev v4i32:$vj, v4i32:$vk),1988 (VPICKEV_W v4i32:$vj, v4i32:$vk)>;1989def : Pat<(loongarch_vpickev v2i64:$vj, v2i64:$vk),1990 (VPICKEV_D v2i64:$vj, v2i64:$vk)>;1991def : Pat<(loongarch_vpickev v4f32:$vj, v4f32:$vk),1992 (VPICKEV_W v4f32:$vj, v4f32:$vk)>;1993def : Pat<(loongarch_vpickev v2f64:$vj, v2f64:$vk),1994 (VPICKEV_D v2f64:$vj, v2f64:$vk)>;1995 1996// VPICKOD_{B/H/W/D}1997def : Pat<(loongarch_vpickod v16i8:$vj, v16i8:$vk),1998 (VPICKOD_B v16i8:$vj, v16i8:$vk)>;1999def : Pat<(loongarch_vpickod v8i16:$vj, v8i16:$vk),2000 (VPICKOD_H v8i16:$vj, v8i16:$vk)>;2001def : Pat<(loongarch_vpickod v4i32:$vj, v4i32:$vk),2002 (VPICKOD_W v4i32:$vj, v4i32:$vk)>;2003def : Pat<(loongarch_vpickod v2i64:$vj, v2i64:$vk),2004 (VPICKOD_D v2i64:$vj, v2i64:$vk)>;2005def : Pat<(loongarch_vpickod v4f32:$vj, v4f32:$vk),2006 (VPICKOD_W v4f32:$vj, v4f32:$vk)>;2007def : Pat<(loongarch_vpickod v2f64:$vj, v2f64:$vk),2008 (VPICKOD_D v2f64:$vj, v2f64:$vk)>;2009 2010// VPACKEV_{B/H/W/D}2011def : Pat<(loongarch_vpackev v16i8:$vj, v16i8:$vk),2012 (VPACKEV_B v16i8:$vj, v16i8:$vk)>;2013def : Pat<(loongarch_vpackev v8i16:$vj, v8i16:$vk),2014 (VPACKEV_H v8i16:$vj, v8i16:$vk)>;2015def : Pat<(loongarch_vpackev v4i32:$vj, v4i32:$vk),2016 (VPACKEV_W v4i32:$vj, v4i32:$vk)>;2017def : Pat<(loongarch_vpackev v2i64:$vj, v2i64:$vk),2018 (VPACKEV_D v2i64:$vj, v2i64:$vk)>;2019def : Pat<(loongarch_vpackev v4f32:$vj, v4f32:$vk),2020 (VPACKEV_W v4f32:$vj, v4f32:$vk)>;2021def : Pat<(loongarch_vpackev v2f64:$vj, v2f64:$vk),2022 (VPACKEV_D v2f64:$vj, v2f64:$vk)>;2023 2024// VPACKOD_{B/H/W/D}2025def : Pat<(loongarch_vpackod v16i8:$vj, v16i8:$vk),2026 (VPACKOD_B v16i8:$vj, v16i8:$vk)>;2027def : Pat<(loongarch_vpackod v8i16:$vj, v8i16:$vk),2028 (VPACKOD_H v8i16:$vj, v8i16:$vk)>;2029def : Pat<(loongarch_vpackod v4i32:$vj, v4i32:$vk),2030 (VPACKOD_W v4i32:$vj, v4i32:$vk)>;2031def : Pat<(loongarch_vpackod v2i64:$vj, v2i64:$vk),2032 (VPACKOD_D v2i64:$vj, v2i64:$vk)>;2033def : Pat<(loongarch_vpackod v4f32:$vj, v4f32:$vk),2034 (VPACKOD_W v4f32:$vj, v4f32:$vk)>;2035def : Pat<(loongarch_vpackod v2f64:$vj, v2f64:$vk),2036 (VPACKOD_D v2f64:$vj, v2f64:$vk)>;2037 2038// VILVL_{B/H/W/D}2039def : Pat<(loongarch_vilvl v16i8:$vj, v16i8:$vk),2040 (VILVL_B v16i8:$vj, v16i8:$vk)>;2041def : Pat<(loongarch_vilvl v8i16:$vj, v8i16:$vk),2042 (VILVL_H v8i16:$vj, v8i16:$vk)>;2043def : Pat<(loongarch_vilvl v4i32:$vj, v4i32:$vk),2044 (VILVL_W v4i32:$vj, v4i32:$vk)>;2045def : Pat<(loongarch_vilvl v2i64:$vj, v2i64:$vk),2046 (VILVL_D v2i64:$vj, v2i64:$vk)>;2047def : Pat<(loongarch_vilvl v4f32:$vj, v4f32:$vk),2048 (VILVL_W v4f32:$vj, v4f32:$vk)>;2049def : Pat<(loongarch_vilvl v2f64:$vj, v2f64:$vk),2050 (VILVL_D v2f64:$vj, v2f64:$vk)>;2051 2052// VILVH_{B/H/W/D}2053def : Pat<(loongarch_vilvh v16i8:$vj, v16i8:$vk),2054 (VILVH_B v16i8:$vj, v16i8:$vk)>;2055def : Pat<(loongarch_vilvh v8i16:$vj, v8i16:$vk),2056 (VILVH_H v8i16:$vj, v8i16:$vk)>;2057def : Pat<(loongarch_vilvh v4i32:$vj, v4i32:$vk),2058 (VILVH_W v4i32:$vj, v4i32:$vk)>;2059def : Pat<(loongarch_vilvh v2i64:$vj, v2i64:$vk),2060 (VILVH_D v2i64:$vj, v2i64:$vk)>;2061def : Pat<(loongarch_vilvh v4f32:$vj, v4f32:$vk),2062 (VILVH_W v4f32:$vj, v4f32:$vk)>;2063def : Pat<(loongarch_vilvh v2f64:$vj, v2f64:$vk),2064 (VILVH_D v2f64:$vj, v2f64:$vk)>;2065 2066// VSHUF4I_{B/H/W/D}2067def : Pat<(loongarch_vshuf4i v16i8:$vj, immZExt8:$ui8),2068 (VSHUF4I_B v16i8:$vj, immZExt8:$ui8)>;2069def : Pat<(loongarch_vshuf4i v8i16:$vj, immZExt8:$ui8),2070 (VSHUF4I_H v8i16:$vj, immZExt8:$ui8)>;2071def : Pat<(loongarch_vshuf4i v4i32:$vj, immZExt8:$ui8),2072 (VSHUF4I_W v4i32:$vj, immZExt8:$ui8)>;2073def : Pat<(loongarch_vshuf4i v4f32:$vj, immZExt8:$ui8),2074 (VSHUF4I_W v4f32:$vj, immZExt8:$ui8)>;2075def : Pat<(loongarch_vshuf4i_d v2i64:$vj, v2i64:$vk, immZExt8:$ui8),2076 (VSHUF4I_D v2i64:$vj, v2i64:$vk, immZExt8:$ui8)>;2077def : Pat<(loongarch_vshuf4i_d v2f64:$vj, v2f64:$vk, immZExt8:$ui8),2078 (VSHUF4I_D v2f64:$vj, v2f64:$vk, immZExt8:$ui8)>;2079 2080// VREPLVEI_{B/H/W/D}2081def : Pat<(loongarch_vreplvei v16i8:$vj, immZExt4:$ui4),2082 (VREPLVEI_B v16i8:$vj, immZExt4:$ui4)>;2083def : Pat<(loongarch_vreplvei v8i16:$vj, immZExt3:$ui3),2084 (VREPLVEI_H v8i16:$vj, immZExt3:$ui3)>;2085def : Pat<(loongarch_vreplvei v4i32:$vj, immZExt2:$ui2),2086 (VREPLVEI_W v4i32:$vj, immZExt2:$ui2)>;2087def : Pat<(loongarch_vreplvei v2i64:$vj, immZExt1:$ui1),2088 (VREPLVEI_D v2i64:$vj, immZExt1:$ui1)>;2089def : Pat<(loongarch_vreplvei v4f32:$vj, immZExt2:$ui2),2090 (VREPLVEI_W v4f32:$vj, immZExt2:$ui2)>;2091def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1),2092 (VREPLVEI_D v2f64:$vj, immZExt1:$ui1)>;2093 2094// VREPLVEI_{W/D}2095def : Pat<(lsxsplatf32 FPR32:$fj),2096 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>;2097def : Pat<(lsxsplatf64 FPR64:$fj),2098 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>;2099 2100defm : VstelmPat<truncstorei8, v16i8, VSTELM_B, simm8, uimm4>;2101defm : VstelmPat<truncstorei16, v8i16, VSTELM_H, simm8_lsl1, uimm3>;2102defm : VstelmPat<truncstorei32, v4i32, VSTELM_W, simm8_lsl2, uimm2>;2103defm : VstelmPat<store, v2i64, VSTELM_D, simm8_lsl3, uimm1>;2104defm : VstelmPat<store, v4f32, VSTELM_W, simm8_lsl2, uimm2, f32>;2105defm : VstelmPat<store, v2f64, VSTELM_D, simm8_lsl3, uimm1, f64>;2106 2107// Loads/Stores2108foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {2109 defm : LdPat<load, VLD, vt>;2110 def : RegRegLdPat<load, VLDX, vt>;2111 defm : StPat<store, VST, LSX128, vt>;2112 def : RegRegStPat<store, VSTX, LSX128, vt>;2113}2114 2115// Bitcast float/double element extracted from vector to integer.2116def : Pat<(loongarch_movfr2gr_s_la64 (f32 (vector_extract v4f32:$vj, uimm2:$imm))),2117 (VPICKVE2GR_W v4f32:$vj, uimm2:$imm)>;2118def : Pat<(i64 (bitconvert (f64 (vector_extract v2f64:$vj, uimm1:$imm)))),2119 (VPICKVE2GR_D v2f64:$vj, uimm1:$imm)>;2120 2121// Vector extraction with constant index.2122def : Pat<(GRLenVT (vector_extract v16i8:$vj, uimm4:$imm)),2123 (VPICKVE2GR_B v16i8:$vj, uimm4:$imm)>;2124def : Pat<(GRLenVT (vector_extract v8i16:$vj, uimm3:$imm)),2125 (VPICKVE2GR_H v8i16:$vj, uimm3:$imm)>;2126def : Pat<(GRLenVT (vector_extract v4i32:$vj, uimm2:$imm)),2127 (VPICKVE2GR_W v4i32:$vj, uimm2:$imm)>;2128def : Pat<(i64 (vector_extract v2i64:$vj, uimm1:$imm)),2129 (VPICKVE2GR_D v2i64:$vj, uimm1:$imm)>;2130def : Pat<(f32 (vector_extract v4f32:$vj, uimm2:$imm)),2131 (f32 (EXTRACT_SUBREG (VREPLVEI_W v4f32:$vj, uimm2:$imm), sub_32))>;2132def : Pat<(f64 (vector_extract v2f64:$vj, uimm1:$imm)),2133 (f64 (EXTRACT_SUBREG (VREPLVEI_D v2f64:$vj, uimm1:$imm), sub_64))>;2134 2135// Vector extraction with variable index.2136def : Pat<(GRLenVT (vector_extract v16i8:$vj, GRLenVT:$rk)),2137 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_B v16i8:$vj,2138 GRLenVT:$rk),2139 sub_32)),2140 GPR), (GRLenVT 24))>;2141def : Pat<(GRLenVT (vector_extract v8i16:$vj, GRLenVT:$rk)),2142 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_H v8i16:$vj,2143 GRLenVT:$rk),2144 sub_32)),2145 GPR), (GRLenVT 16))>;2146def : Pat<(GRLenVT (vector_extract v4i32:$vj, GRLenVT:$rk)),2147 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_W v4i32:$vj, GRLenVT:$rk),2148 sub_32)),2149 GPR)>;2150def : Pat<(GRLenVT (vector_extract v2i64:$vj, GRLenVT:$rk)),2151 (COPY_TO_REGCLASS (f64 (EXTRACT_SUBREG (VREPLVE_D v2i64:$vj, GRLenVT:$rk),2152 sub_64)),2153 GPR)>;2154def : Pat<(f32 (vector_extract v4f32:$vj, GRLenVT:$rk)),2155 (f32 (EXTRACT_SUBREG (VREPLVE_W v4f32:$vj, GRLenVT:$rk), sub_32))>;2156def : Pat<(f64 (vector_extract v2f64:$vj, GRLenVT:$rk)),2157 (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, GRLenVT:$rk), sub_64))>;2158 2159// vselect2160def : Pat<(v16i8 (vselect LSX128:$vd, (v16i8 (SplatPat_uimm8 uimm8:$imm)),2161 LSX128:$vj)),2162 (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>;2163foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in2164 def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)),2165 (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>;2166 2167// fneg2168def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>;2169def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>;2170 2171// VFFINT_{S_W/D_L}2172def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>;2173def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>;2174 2175// VFFINT_{S_WU/D_LU}2176def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>;2177def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>;2178 2179// VFTINTRZ_{W_S/L_D}2180def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>;2181def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>;2182 2183// VFTINTRZ_{W_SU/L_DU}2184def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>;2185def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>;2186 2187// Vector loads floating-point constants2188def : Pat<(f32 f32imm_vldi:$in),2189 (f32 (EXTRACT_SUBREG (VLDI (to_f32imm_vldi f32imm_vldi:$in)), sub_32))>;2190def : Pat<(f64 f64imm_vldi:$in),2191 (f64 (EXTRACT_SUBREG (VLDI (to_f64imm_vldi f64imm_vldi:$in)), sub_64))>;2192 2193// VAVG_{B/H/W/D/BU/HU/WU/DU}, VAVGR_{B/H/W/D/BU/HU/WU/DU}2194defm : VAvgPat<sra, "VAVG_B", v16i8>;2195defm : VAvgPat<sra, "VAVG_H", v8i16>;2196defm : VAvgPat<sra, "VAVG_W", v4i32>;2197defm : VAvgPat<sra, "VAVG_D", v2i64>;2198defm : VAvgPat<srl, "VAVG_BU", v16i8>;2199defm : VAvgPat<srl, "VAVG_HU", v8i16>;2200defm : VAvgPat<srl, "VAVG_WU", v4i32>;2201defm : VAvgPat<srl, "VAVG_DU", v2i64>;2202defm : VAvgrPat<sra, "VAVGR_B", v16i8>;2203defm : VAvgrPat<sra, "VAVGR_H", v8i16>;2204defm : VAvgrPat<sra, "VAVGR_W", v4i32>;2205defm : VAvgrPat<sra, "VAVGR_D", v2i64>;2206defm : VAvgrPat<srl, "VAVGR_BU", v16i8>;2207defm : VAvgrPat<srl, "VAVGR_HU", v8i16>;2208defm : VAvgrPat<srl, "VAVGR_WU", v4i32>;2209defm : VAvgrPat<srl, "VAVGR_DU", v2i64>;2210 2211// abs2212def : Pat<(abs v16i8:$vj), (VSIGNCOV_B v16i8:$vj, v16i8:$vj)>;2213def : Pat<(abs v8i16:$vj), (VSIGNCOV_H v8i16:$vj, v8i16:$vj)>;2214def : Pat<(abs v4i32:$vj), (VSIGNCOV_W v4i32:$vj, v4i32:$vj)>;2215def : Pat<(abs v2i64:$vj), (VSIGNCOV_D v2i64:$vj, v2i64:$vj)>;2216 2217// VABSD_{B/H/W/D}[U]2218defm : PatVrVr<abds, "VABSD">;2219defm : PatVrVrU<abdu, "VABSD">;2220 2221// VADDA_{B/H/W/D}2222def : Pat<(add (v16i8 (abs v16i8:$vj)), (v16i8 (abs v16i8:$vk))),2223 (VADDA_B v16i8:$vj, v16i8:$vk)>;2224def : Pat<(add (v8i16 (abs v8i16:$vj)), (v8i16 (abs v8i16:$vk))),2225 (VADDA_H v8i16:$vj, v8i16:$vk)>;2226def : Pat<(add (v4i32 (abs v4i32:$vj)), (v4i32 (abs v4i32:$vk))),2227 (VADDA_W v4i32:$vj, v4i32:$vk)>;2228def : Pat<(add (v2i64 (abs v2i64:$vj)), (v2i64 (abs v2i64:$vk))),2229 (VADDA_D v2i64:$vj, v2i64:$vk)>;2230 2231// VSADD_{B/H/W/D}[U], VSSUB_{B/H/W/D}[U]2232defm : PatVrVr<saddsat, "VSADD">;2233defm : PatVrVr<ssubsat, "VSSUB">;2234defm : PatVrVrU<uaddsat, "VSADD">;2235defm : PatVrVrU<usubsat, "VSSUB">;2236 2237// Vector mask set by condition2238def : Pat<(loongarch_vmskltz (v16i8 LSX128:$vj)), (PseudoVMSKLTZ_B LSX128:$vj)>;2239def : Pat<(loongarch_vmskltz (v8i16 LSX128:$vj)), (PseudoVMSKLTZ_H LSX128:$vj)>;2240def : Pat<(loongarch_vmskltz (v4i32 LSX128:$vj)), (PseudoVMSKLTZ_W LSX128:$vj)>;2241def : Pat<(loongarch_vmskltz (v2i64 LSX128:$vj)), (PseudoVMSKLTZ_D LSX128:$vj)>;2242def : Pat<(loongarch_vmskgez (v16i8 LSX128:$vj)), (PseudoVMSKGEZ_B LSX128:$vj)>;2243def : Pat<(loongarch_vmskeqz (v16i8 LSX128:$vj)), (PseudoVMSKEQZ_B LSX128:$vj)>;2244def : Pat<(loongarch_vmsknez (v16i8 LSX128:$vj)), (PseudoVMSKNEZ_B LSX128:$vj)>;2245 2246} // Predicates = [HasExtLSX]2247 2248/// Intrinsic pattern2249 2250class deriveLSXIntrinsic<string Inst> {2251 Intrinsic ret = !cast<Intrinsic>(!tolower("int_loongarch_lsx_"#Inst));2252}2253 2254let Predicates = [HasExtLSX] in {2255 2256// vty: v16i8/v8i16/v4i32/v2i642257// Pat<(Intrinsic vty:$vj, vty:$vk),2258// (LAInst vty:$vj, vty:$vk)>;2259foreach Inst = ["VSADD_B", "VSADD_BU", "VSSUB_B", "VSSUB_BU",2260 "VHADDW_H_B", "VHADDW_HU_BU", "VHSUBW_H_B", "VHSUBW_HU_BU",2261 "VADDWEV_H_B", "VADDWOD_H_B", "VSUBWEV_H_B", "VSUBWOD_H_B",2262 "VADDWEV_H_BU", "VADDWOD_H_BU", "VSUBWEV_H_BU", "VSUBWOD_H_BU",2263 "VADDWEV_H_BU_B", "VADDWOD_H_BU_B",2264 "VAVG_B", "VAVG_BU", "VAVGR_B", "VAVGR_BU",2265 "VABSD_B", "VABSD_BU", "VADDA_B", "VMUH_B", "VMUH_BU",2266 "VMULWEV_H_B", "VMULWOD_H_B", "VMULWEV_H_BU", "VMULWOD_H_BU",2267 "VMULWEV_H_BU_B", "VMULWOD_H_BU_B", "VSIGNCOV_B",2268 "VANDN_V", "VORN_V", "VROTR_B", "VSRLR_B", "VSRAR_B",2269 "VSEQ_B", "VSLE_B", "VSLE_BU", "VSLT_B", "VSLT_BU",2270 "VPACKEV_B", "VPACKOD_B", "VPICKEV_B", "VPICKOD_B",2271 "VILVL_B", "VILVH_B"] in2272 def : Pat<(deriveLSXIntrinsic<Inst>.ret2273 (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),2274 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2275foreach Inst = ["VSADD_H", "VSADD_HU", "VSSUB_H", "VSSUB_HU",2276 "VHADDW_W_H", "VHADDW_WU_HU", "VHSUBW_W_H", "VHSUBW_WU_HU",2277 "VADDWEV_W_H", "VADDWOD_W_H", "VSUBWEV_W_H", "VSUBWOD_W_H",2278 "VADDWEV_W_HU", "VADDWOD_W_HU", "VSUBWEV_W_HU", "VSUBWOD_W_HU",2279 "VADDWEV_W_HU_H", "VADDWOD_W_HU_H",2280 "VAVG_H", "VAVG_HU", "VAVGR_H", "VAVGR_HU",2281 "VABSD_H", "VABSD_HU", "VADDA_H", "VMUH_H", "VMUH_HU",2282 "VMULWEV_W_H", "VMULWOD_W_H", "VMULWEV_W_HU", "VMULWOD_W_HU",2283 "VMULWEV_W_HU_H", "VMULWOD_W_HU_H", "VSIGNCOV_H", "VROTR_H",2284 "VSRLR_H", "VSRAR_H", "VSRLN_B_H", "VSRAN_B_H", "VSRLRN_B_H",2285 "VSRARN_B_H", "VSSRLN_B_H", "VSSRAN_B_H", "VSSRLN_BU_H",2286 "VSSRAN_BU_H", "VSSRLRN_B_H", "VSSRARN_B_H", "VSSRLRN_BU_H",2287 "VSSRARN_BU_H",2288 "VSEQ_H", "VSLE_H", "VSLE_HU", "VSLT_H", "VSLT_HU",2289 "VPACKEV_H", "VPACKOD_H", "VPICKEV_H", "VPICKOD_H",2290 "VILVL_H", "VILVH_H"] in2291 def : Pat<(deriveLSXIntrinsic<Inst>.ret2292 (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),2293 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2294foreach Inst = ["VSADD_W", "VSADD_WU", "VSSUB_W", "VSSUB_WU",2295 "VHADDW_D_W", "VHADDW_DU_WU", "VHSUBW_D_W", "VHSUBW_DU_WU",2296 "VADDWEV_D_W", "VADDWOD_D_W", "VSUBWEV_D_W", "VSUBWOD_D_W",2297 "VADDWEV_D_WU", "VADDWOD_D_WU", "VSUBWEV_D_WU", "VSUBWOD_D_WU",2298 "VADDWEV_D_WU_W", "VADDWOD_D_WU_W",2299 "VAVG_W", "VAVG_WU", "VAVGR_W", "VAVGR_WU",2300 "VABSD_W", "VABSD_WU", "VADDA_W", "VMUH_W", "VMUH_WU",2301 "VMULWEV_D_W", "VMULWOD_D_W", "VMULWEV_D_WU", "VMULWOD_D_WU",2302 "VMULWEV_D_WU_W", "VMULWOD_D_WU_W", "VSIGNCOV_W", "VROTR_W",2303 "VSRLR_W", "VSRAR_W", "VSRLN_H_W", "VSRAN_H_W", "VSRLRN_H_W",2304 "VSRARN_H_W", "VSSRLN_H_W", "VSSRAN_H_W", "VSSRLN_HU_W",2305 "VSSRAN_HU_W", "VSSRLRN_H_W", "VSSRARN_H_W", "VSSRLRN_HU_W",2306 "VSSRARN_HU_W",2307 "VSEQ_W", "VSLE_W", "VSLE_WU", "VSLT_W", "VSLT_WU",2308 "VPACKEV_W", "VPACKOD_W", "VPICKEV_W", "VPICKOD_W",2309 "VILVL_W", "VILVH_W"] in2310 def : Pat<(deriveLSXIntrinsic<Inst>.ret2311 (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),2312 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2313foreach Inst = ["VADD_Q", "VSUB_Q",2314 "VSADD_D", "VSADD_DU", "VSSUB_D", "VSSUB_DU",2315 "VHADDW_Q_D", "VHADDW_QU_DU", "VHSUBW_Q_D", "VHSUBW_QU_DU",2316 "VADDWEV_Q_D", "VADDWOD_Q_D", "VSUBWEV_Q_D", "VSUBWOD_Q_D",2317 "VADDWEV_Q_DU", "VADDWOD_Q_DU", "VSUBWEV_Q_DU", "VSUBWOD_Q_DU",2318 "VADDWEV_Q_DU_D", "VADDWOD_Q_DU_D",2319 "VAVG_D", "VAVG_DU", "VAVGR_D", "VAVGR_DU",2320 "VABSD_D", "VABSD_DU", "VADDA_D", "VMUH_D", "VMUH_DU",2321 "VMULWEV_Q_D", "VMULWOD_Q_D", "VMULWEV_Q_DU", "VMULWOD_Q_DU",2322 "VMULWEV_Q_DU_D", "VMULWOD_Q_DU_D", "VSIGNCOV_D", "VROTR_D",2323 "VSRLR_D", "VSRAR_D", "VSRLN_W_D", "VSRAN_W_D", "VSRLRN_W_D",2324 "VSRARN_W_D", "VSSRLN_W_D", "VSSRAN_W_D", "VSSRLN_WU_D",2325 "VSSRAN_WU_D", "VSSRLRN_W_D", "VSSRARN_W_D", "VSSRLRN_WU_D",2326 "VSSRARN_WU_D", "VFFINT_S_L",2327 "VSEQ_D", "VSLE_D", "VSLE_DU", "VSLT_D", "VSLT_DU",2328 "VPACKEV_D", "VPACKOD_D", "VPICKEV_D", "VPICKOD_D",2329 "VILVL_D", "VILVH_D"] in2330 def : Pat<(deriveLSXIntrinsic<Inst>.ret2331 (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),2332 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2333 2334// vty: v16i8/v8i16/v4i32/v2i642335// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk),2336// (LAInst vty:$vd, vty:$vj, vty:$vk)>;2337foreach Inst = ["VMADDWEV_H_B", "VMADDWOD_H_B", "VMADDWEV_H_BU",2338 "VMADDWOD_H_BU", "VMADDWEV_H_BU_B", "VMADDWOD_H_BU_B"] in2339 def : Pat<(deriveLSXIntrinsic<Inst>.ret2340 (v8i16 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),2341 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2342foreach Inst = ["VMADDWEV_W_H", "VMADDWOD_W_H", "VMADDWEV_W_HU",2343 "VMADDWOD_W_HU", "VMADDWEV_W_HU_H", "VMADDWOD_W_HU_H"] in2344 def : Pat<(deriveLSXIntrinsic<Inst>.ret2345 (v4i32 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),2346 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2347foreach Inst = ["VMADDWEV_D_W", "VMADDWOD_D_W", "VMADDWEV_D_WU",2348 "VMADDWOD_D_WU", "VMADDWEV_D_WU_W", "VMADDWOD_D_WU_W"] in2349 def : Pat<(deriveLSXIntrinsic<Inst>.ret2350 (v2i64 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),2351 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2352foreach Inst = ["VMADDWEV_Q_D", "VMADDWOD_Q_D", "VMADDWEV_Q_DU",2353 "VMADDWOD_Q_DU", "VMADDWEV_Q_DU_D", "VMADDWOD_Q_DU_D"] in2354 def : Pat<(deriveLSXIntrinsic<Inst>.ret2355 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),2356 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2357 2358// vty: v16i8/v8i16/v4i32/v2i642359// Pat<(Intrinsic vty:$vj),2360// (LAInst vty:$vj)>;2361foreach Inst = ["VEXTH_H_B", "VEXTH_HU_BU",2362 "VMSKLTZ_B", "VMSKGEZ_B", "VMSKNZ_B",2363 "VCLO_B"] in2364 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj)),2365 (!cast<LAInst>(Inst) LSX128:$vj)>;2366foreach Inst = ["VEXTH_W_H", "VEXTH_WU_HU", "VMSKLTZ_H",2367 "VCLO_H", "VFCVTL_S_H", "VFCVTH_S_H"] in2368 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj)),2369 (!cast<LAInst>(Inst) LSX128:$vj)>;2370foreach Inst = ["VEXTH_D_W", "VEXTH_DU_WU", "VMSKLTZ_W",2371 "VCLO_W", "VFFINT_S_W", "VFFINT_S_WU",2372 "VFFINTL_D_W", "VFFINTH_D_W"] in2373 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj)),2374 (!cast<LAInst>(Inst) LSX128:$vj)>;2375foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D",2376 "VEXTL_Q_D", "VEXTL_QU_DU",2377 "VCLO_D", "VFFINT_D_L", "VFFINT_D_LU"] in2378 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj)),2379 (!cast<LAInst>(Inst) LSX128:$vj)>;2380 2381// Pat<(Intrinsic timm:$imm)2382// (LAInst timm:$imm)>;2383def : Pat<(int_loongarch_lsx_vldi timm:$imm),2384 (VLDI (to_valid_timm timm:$imm))>;2385foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in2386 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm),2387 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;2388 2389// vty: v16i8/v8i16/v4i32/v2i642390// Pat<(Intrinsic vty:$vj, timm:$imm)2391// (LAInst vty:$vj, timm:$imm)>;2392foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B",2393 "VSLLWIL_HU_BU", "VSRLRI_B", "VSRARI_B",2394 "VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU",2395 "VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in2396 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm),2397 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;2398foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H",2399 "VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H",2400 "VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU",2401 "VREPLVEI_H", "VSHUF4I_H"] in2402 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm),2403 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;2404foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W",2405 "VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W",2406 "VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU",2407 "VREPLVEI_W", "VSHUF4I_W"] in2408 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm),2409 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;2410foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D",2411 "VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU",2412 "VPICKVE2GR_D", "VPICKVE2GR_DU",2413 "VREPLVEI_D"] in2414 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm),2415 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;2416 2417// vty: v16i8/v8i16/v4i32/v2i642418// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm)2419// (LAInst vty:$vd, vty:$vj, timm:$imm)>;2420foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H",2421 "VSSRLNI_B_H", "VSSRANI_B_H", "VSSRLNI_BU_H", "VSSRANI_BU_H",2422 "VSSRLRNI_B_H", "VSSRARNI_B_H", "VSSRLRNI_BU_H", "VSSRARNI_BU_H",2423 "VFRSTPI_B", "VBITSELI_B", "VEXTRINS_B"] in2424 def : Pat<(deriveLSXIntrinsic<Inst>.ret2425 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm),2426 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,2427 (to_valid_timm timm:$imm))>;2428foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W",2429 "VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W",2430 "VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W",2431 "VFRSTPI_H", "VEXTRINS_H"] in2432 def : Pat<(deriveLSXIntrinsic<Inst>.ret2433 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm),2434 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,2435 (to_valid_timm timm:$imm))>;2436foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D",2437 "VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D",2438 "VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D",2439 "VPERMI_W", "VEXTRINS_W"] in2440 def : Pat<(deriveLSXIntrinsic<Inst>.ret2441 (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm),2442 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,2443 (to_valid_timm timm:$imm))>;2444foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q",2445 "VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q",2446 "VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q",2447 "VSHUF4I_D", "VEXTRINS_D"] in2448 def : Pat<(deriveLSXIntrinsic<Inst>.ret2449 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm),2450 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,2451 (to_valid_timm timm:$imm))>;2452 2453// vty: v16i8/v8i16/v4i32/v2i642454// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk),2455// (LAInst vty:$vd, vty:$vj, vty:$vk)>;2456foreach Inst = ["VFRSTP_B", "VBITSEL_V", "VSHUF_B"] in2457 def : Pat<(deriveLSXIntrinsic<Inst>.ret2458 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),2459 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2460foreach Inst = ["VFRSTP_H", "VSHUF_H"] in2461 def : Pat<(deriveLSXIntrinsic<Inst>.ret2462 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),2463 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2464def : Pat<(int_loongarch_lsx_vshuf_w (v4i32 LSX128:$vd), (v4i32 LSX128:$vj),2465 (v4i32 LSX128:$vk)),2466 (VSHUF_W LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2467def : Pat<(int_loongarch_lsx_vshuf_d (v2i64 LSX128:$vd), (v2i64 LSX128:$vj),2468 (v2i64 LSX128:$vk)),2469 (VSHUF_D LSX128:$vd, LSX128:$vj, LSX128:$vk)>;2470 2471// vty: v4f32/v2f642472// Pat<(Intrinsic vty:$vj, vty:$vk, vty:$va),2473// (LAInst vty:$vj, vty:$vk, vty:$va)>;2474foreach Inst = ["VFMSUB_S", "VFNMADD_S", "VFNMSUB_S"] in2475 def : Pat<(deriveLSXIntrinsic<Inst>.ret2476 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), (v4f32 LSX128:$va)),2477 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>;2478foreach Inst = ["VFMSUB_D", "VFNMADD_D", "VFNMSUB_D"] in2479 def : Pat<(deriveLSXIntrinsic<Inst>.ret2480 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), (v2f64 LSX128:$va)),2481 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>;2482 2483// vty: v4f32/v2f642484// Pat<(Intrinsic vty:$vj, vty:$vk),2485// (LAInst vty:$vj, vty:$vk)>;2486foreach Inst = ["VFMAX_S", "VFMIN_S", "VFMAXA_S", "VFMINA_S", "VFCVT_H_S",2487 "VFCMP_CAF_S", "VFCMP_CUN_S", "VFCMP_CEQ_S", "VFCMP_CUEQ_S",2488 "VFCMP_CLT_S", "VFCMP_CULT_S", "VFCMP_CLE_S", "VFCMP_CULE_S",2489 "VFCMP_CNE_S", "VFCMP_COR_S", "VFCMP_CUNE_S",2490 "VFCMP_SAF_S", "VFCMP_SUN_S", "VFCMP_SEQ_S", "VFCMP_SUEQ_S",2491 "VFCMP_SLT_S", "VFCMP_SULT_S", "VFCMP_SLE_S", "VFCMP_SULE_S",2492 "VFCMP_SNE_S", "VFCMP_SOR_S", "VFCMP_SUNE_S"] in2493 def : Pat<(deriveLSXIntrinsic<Inst>.ret2494 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)),2495 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2496foreach Inst = ["VFMAX_D", "VFMIN_D", "VFMAXA_D", "VFMINA_D", "VFCVT_S_D",2497 "VFTINTRNE_W_D", "VFTINTRZ_W_D", "VFTINTRP_W_D", "VFTINTRM_W_D",2498 "VFTINT_W_D",2499 "VFCMP_CAF_D", "VFCMP_CUN_D", "VFCMP_CEQ_D", "VFCMP_CUEQ_D",2500 "VFCMP_CLT_D", "VFCMP_CULT_D", "VFCMP_CLE_D", "VFCMP_CULE_D",2501 "VFCMP_CNE_D", "VFCMP_COR_D", "VFCMP_CUNE_D",2502 "VFCMP_SAF_D", "VFCMP_SUN_D", "VFCMP_SEQ_D", "VFCMP_SUEQ_D",2503 "VFCMP_SLT_D", "VFCMP_SULT_D", "VFCMP_SLE_D", "VFCMP_SULE_D",2504 "VFCMP_SNE_D", "VFCMP_SOR_D", "VFCMP_SUNE_D"] in2505 def : Pat<(deriveLSXIntrinsic<Inst>.ret2506 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)),2507 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>;2508 2509// vty: v4f32/v2f642510// Pat<(Intrinsic vty:$vj),2511// (LAInst vty:$vj)>;2512foreach Inst = ["VFLOGB_S", "VFCLASS_S", "VFSQRT_S", "VFRECIP_S", "VFRSQRT_S",2513 "VFRINT_S", "VFCVTL_D_S", "VFCVTH_D_S",2514 "VFRINTRNE_S", "VFRINTRZ_S", "VFRINTRP_S", "VFRINTRM_S",2515 "VFTINTRNE_W_S", "VFTINTRZ_W_S", "VFTINTRP_W_S", "VFTINTRM_W_S",2516 "VFTINT_W_S", "VFTINTRZ_WU_S", "VFTINT_WU_S",2517 "VFTINTRNEL_L_S", "VFTINTRNEH_L_S", "VFTINTRZL_L_S",2518 "VFTINTRZH_L_S", "VFTINTRPL_L_S", "VFTINTRPH_L_S",2519 "VFTINTRML_L_S", "VFTINTRMH_L_S", "VFTINTL_L_S",2520 "VFTINTH_L_S"] in2521 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)),2522 (!cast<LAInst>(Inst) LSX128:$vj)>;2523foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D",2524 "VFRINT_D",2525 "VFRINTRNE_D", "VFRINTRZ_D", "VFRINTRP_D", "VFRINTRM_D",2526 "VFTINTRNE_L_D", "VFTINTRZ_L_D", "VFTINTRP_L_D", "VFTINTRM_L_D",2527 "VFTINT_L_D", "VFTINTRZ_LU_D", "VFTINT_LU_D"] in2528 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)),2529 (!cast<LAInst>(Inst) LSX128:$vj)>;2530 2531// 128-Bit vector FP approximate reciprocal operation2532let Predicates = [HasFrecipe] in {2533foreach Inst = ["VFRECIPE_S", "VFRSQRTE_S"] in2534 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)),2535 (!cast<LAInst>(Inst) LSX128:$vj)>;2536foreach Inst = ["VFRECIPE_D", "VFRSQRTE_D"] in2537 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)),2538 (!cast<LAInst>(Inst) LSX128:$vj)>;2539 2540def : Pat<(loongarch_vfrecipe v4f32:$src), 2541 (VFRECIPE_S v4f32:$src)>;2542def : Pat<(loongarch_vfrecipe v2f64:$src), 2543 (VFRECIPE_D v2f64:$src)>;2544def : Pat<(loongarch_vfrsqrte v4f32:$src), 2545 (VFRSQRTE_S v4f32:$src)>;2546def : Pat<(loongarch_vfrsqrte v2f64:$src), 2547 (VFRSQRTE_D v2f64:$src)>;2548}2549 2550// Vector floating-point conversion2551def : Pat<(f32 (fceil FPR32:$fj)),2552 (f32 (EXTRACT_SUBREG (VFRINTRP_S (VREPLVEI_W2553 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>;2554def : Pat<(f64 (fceil FPR64:$fj)),2555 (f64 (EXTRACT_SUBREG (VFRINTRP_D (VREPLVEI_D2556 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>;2557def : Pat<(f32 (ffloor FPR32:$fj)),2558 (f32 (EXTRACT_SUBREG (VFRINTRM_S (VREPLVEI_W2559 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>;2560def : Pat<(f64 (ffloor FPR64:$fj)),2561 (f64 (EXTRACT_SUBREG (VFRINTRM_D (VREPLVEI_D2562 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>;2563def : Pat<(f32 (ftrunc FPR32:$fj)),2564 (f32 (EXTRACT_SUBREG (VFRINTRZ_S (VREPLVEI_W2565 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>;2566def : Pat<(f64 (ftrunc FPR64:$fj)),2567 (f64 (EXTRACT_SUBREG (VFRINTRZ_D (VREPLVEI_D2568 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>;2569def : Pat<(f32 (froundeven FPR32:$fj)),2570 (f32 (EXTRACT_SUBREG (VFRINTRNE_S (VREPLVEI_W2571 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>;2572def : Pat<(f64 (froundeven FPR64:$fj)),2573 (f64 (EXTRACT_SUBREG (VFRINTRNE_D (VREPLVEI_D2574 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>;2575 2576defm : PatVrF<fceil, "VFRINTRP">;2577defm : PatVrF<ffloor, "VFRINTRM">;2578defm : PatVrF<ftrunc, "VFRINTRZ">;2579defm : PatVrF<froundeven, "VFRINTRNE">;2580 2581// load2582def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm),2583 (VLD GPR:$rj, (to_valid_timm timm:$imm))>;2584def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk),2585 (VLDX GPR:$rj, GPR:$rk)>;2586 2587// vldrepl2588def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm),2589 (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>;2590def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm),2591 (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>;2592def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm),2593 (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>;2594def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm),2595 (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>;2596 2597defm : VldreplPat<v16i8, VLDREPL_B, simm12_addlike>;2598defm : VldreplPat<v8i16, VLDREPL_H, simm11_lsl1>;2599defm : VldreplPat<v4i32, VLDREPL_W, simm10_lsl2>;2600defm : VldreplPat<v2i64, VLDREPL_D, simm9_lsl3>;2601defm : VldreplPat<v4f32, VLDREPL_W, simm10_lsl2>;2602defm : VldreplPat<v2f64, VLDREPL_D, simm9_lsl3>;2603 2604// store2605def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm),2606 (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>;2607def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk),2608 (VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>;2609 2610def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx),2611 (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm),2612 (to_valid_timm timm:$idx))>;2613def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx),2614 (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm),2615 (to_valid_timm timm:$idx))>;2616def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx),2617 (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm),2618 (to_valid_timm timm:$idx))>;2619def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx),2620 (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm),2621 (to_valid_timm timm:$idx))>;2622 2623} // Predicates = [HasExtLSX]2624