136 lines · cpp
1//===-- LoongArchTargetTransformInfo.cpp - LoongArch specific TTI ---------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8/// \file9/// This file implements a TargetTransformInfo analysis pass specific to the10/// LoongArch target machine. It uses the target's detailed information to11/// provide more precise answers to certain TTI queries, while letting the12/// target independent and default TTI implementations handle the rest.13///14//===----------------------------------------------------------------------===//15 16#include "LoongArchTargetTransformInfo.h"17 18using namespace llvm;19 20#define DEBUG_TYPE "loongarchtti"21 22TypeSize LoongArchTTIImpl::getRegisterBitWidth(23 TargetTransformInfo::RegisterKind K) const {24 TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K);25 switch (K) {26 case TargetTransformInfo::RGK_Scalar:27 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);28 case TargetTransformInfo::RGK_FixedWidthVector:29 if (ST->hasExtLASX())30 return TypeSize::getFixed(256);31 if (ST->hasExtLSX())32 return TypeSize::getFixed(128);33 [[fallthrough]];34 case TargetTransformInfo::RGK_ScalableVector:35 return DefSize;36 }37 38 llvm_unreachable("Unsupported register kind");39}40 41unsigned LoongArchTTIImpl::getNumberOfRegisters(unsigned ClassID) const {42 switch (ClassID) {43 case LoongArchRegisterClass::GPRRC:44 // 30 = 32 GPRs - r0 (zero register) - r21 (non-allocatable)45 return 30;46 case LoongArchRegisterClass::FPRRC:47 return ST->hasBasicF() ? 32 : 0;48 case LoongArchRegisterClass::VRRC:49 return ST->hasExtLSX() ? 32 : 0;50 }51 llvm_unreachable("unknown register class");52}53 54unsigned LoongArchTTIImpl::getRegisterClassForType(bool Vector,55 Type *Ty) const {56 if (Vector)57 return LoongArchRegisterClass::VRRC;58 if (!Ty)59 return LoongArchRegisterClass::GPRRC;60 61 Type *ScalarTy = Ty->getScalarType();62 if ((ScalarTy->isFloatTy() && ST->hasBasicF()) ||63 (ScalarTy->isDoubleTy() && ST->hasBasicD())) {64 return LoongArchRegisterClass::FPRRC;65 }66 67 return LoongArchRegisterClass::GPRRC;68}69 70unsigned LoongArchTTIImpl::getMaxInterleaveFactor(ElementCount VF) const {71 return ST->getMaxInterleaveFactor();72}73 74const char *LoongArchTTIImpl::getRegisterClassName(unsigned ClassID) const {75 switch (ClassID) {76 case LoongArchRegisterClass::GPRRC:77 return "LoongArch::GPRRC";78 case LoongArchRegisterClass::FPRRC:79 return "LoongArch::FPRRC";80 case LoongArchRegisterClass::VRRC:81 return "LoongArch::VRRC";82 }83 llvm_unreachable("unknown register class");84}85 86TargetTransformInfo::PopcntSupportKind87LoongArchTTIImpl::getPopcntSupport(unsigned TyWidth) const {88 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");89 return ST->hasExtLSX() ? TTI::PSK_FastHardware : TTI::PSK_Software;90}91 92unsigned LoongArchTTIImpl::getCacheLineSize() const { return 64; }93 94unsigned LoongArchTTIImpl::getPrefetchDistance() const { return 200; }95 96bool LoongArchTTIImpl::enableWritePrefetching() const { return true; }97 98bool LoongArchTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {99 switch (II->getIntrinsicID()) {100 default:101 return true;102 case Intrinsic::vector_reduce_add:103 case Intrinsic::vector_reduce_and:104 case Intrinsic::vector_reduce_or:105 case Intrinsic::vector_reduce_smax:106 case Intrinsic::vector_reduce_smin:107 case Intrinsic::vector_reduce_umax:108 case Intrinsic::vector_reduce_umin:109 case Intrinsic::vector_reduce_xor:110 return false;111 }112}113 114LoongArchTTIImpl::TTI::MemCmpExpansionOptions115LoongArchTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {116 TTI::MemCmpExpansionOptions Options;117 118 if (!ST->hasUAL())119 return Options;120 121 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);122 Options.NumLoadsPerBlock = Options.MaxNumLoads;123 Options.AllowOverlappingLoads = true;124 125 // TODO: Support for vectors.126 if (ST->is64Bit()) {127 Options.LoadSizes = {8, 4, 2, 1};128 Options.AllowedTailExpansions = {3, 5, 6};129 } else {130 Options.LoadSizes = {4, 2, 1};131 Options.AllowedTailExpansions = {3};132 }133 134 return Options;135}136