305 lines · cpp
1//===-- LoongArchMCTargetDesc.cpp - LoongArch Target Descriptions ---------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides LoongArch specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#include "LoongArchMCTargetDesc.h"14#include "LoongArchELFStreamer.h"15#include "LoongArchInstPrinter.h"16#include "LoongArchMCAsmInfo.h"17#include "TargetInfo/LoongArchTargetInfo.h"18#include "llvm/MC/MCAsmBackend.h"19#include "llvm/MC/MCAsmInfo.h"20#include "llvm/MC/MCCodeEmitter.h"21#include "llvm/MC/MCDwarf.h"22#include "llvm/MC/MCInstrAnalysis.h"23#include "llvm/MC/MCInstrInfo.h"24#include "llvm/MC/MCObjectWriter.h"25#include "llvm/MC/MCRegisterInfo.h"26#include "llvm/MC/MCSubtargetInfo.h"27#include "llvm/MC/TargetRegistry.h"28#include "llvm/Support/Compiler.h"29#include <bitset>30 31#define GET_INSTRINFO_MC_DESC32#define ENABLE_INSTR_PREDICATE_VERIFIER33#include "LoongArchGenInstrInfo.inc"34 35#define GET_REGINFO_MC_DESC36#include "LoongArchGenRegisterInfo.inc"37 38#define GET_SUBTARGETINFO_MC_DESC39#include "LoongArchGenSubtargetInfo.inc"40 41using namespace llvm;42 43static MCRegisterInfo *createLoongArchMCRegisterInfo(const Triple &TT) {44 MCRegisterInfo *X = new MCRegisterInfo();45 InitLoongArchMCRegisterInfo(X, LoongArch::R1);46 return X;47}48 49static MCInstrInfo *createLoongArchMCInstrInfo() {50 MCInstrInfo *X = new MCInstrInfo();51 InitLoongArchMCInstrInfo(X);52 return X;53}54 55static MCSubtargetInfo *56createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {57 if (CPU.empty() || CPU == "generic")58 CPU = TT.isArch64Bit() ? "generic-la64" : "generic-la32";59 return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);60}61 62static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI,63 const Triple &TT,64 const MCTargetOptions &Options) {65 MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);66 67 // Initial state of the frame pointer is sp(r3).68 unsigned SP = MRI.getDwarfRegNum(LoongArch::R3, true);69 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);70 MAI->addInitialFrameState(Inst);71 72 return MAI;73}74 75static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T,76 unsigned SyntaxVariant,77 const MCAsmInfo &MAI,78 const MCInstrInfo &MII,79 const MCRegisterInfo &MRI) {80 return new LoongArchInstPrinter(MAI, MII, MRI);81}82 83static MCTargetStreamer *84createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {85 return STI.getTargetTriple().isOSBinFormatELF()86 ? new LoongArchTargetELFStreamer(S, STI)87 : nullptr;88}89 90static MCTargetStreamer *91createLoongArchAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,92 MCInstPrinter *InstPrint) {93 return new LoongArchTargetAsmStreamer(S, OS);94}95 96namespace {97 98class LoongArchMCInstrAnalysis : public MCInstrAnalysis {99 int64_t GPRState[31] = {};100 std::bitset<31> GPRValidMask;101 102 static bool isGPR(MCRegister Reg) {103 return Reg >= LoongArch::R0 && Reg <= LoongArch::R31;104 }105 106 static unsigned getRegIndex(MCRegister Reg) {107 assert(isGPR(Reg) && Reg != LoongArch::R0 && "Invalid GPR reg");108 return Reg - LoongArch::R1;109 }110 111 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {112 if (Reg == LoongArch::R0)113 return;114 115 auto Index = getRegIndex(Reg);116 117 if (Value) {118 GPRState[Index] = *Value;119 GPRValidMask.set(Index);120 } else {121 GPRValidMask.reset(Index);122 }123 }124 125 std::optional<int64_t> getGPRState(MCRegister Reg) const {126 if (Reg == LoongArch::R0)127 return 0;128 129 auto Index = getRegIndex(Reg);130 131 if (GPRValidMask.test(Index))132 return GPRState[Index];133 return std::nullopt;134 }135 136public:137 explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)138 : MCInstrAnalysis(Info) {}139 140 void resetState() override { GPRValidMask.reset(); }141 142 void updateState(const MCInst &Inst, uint64_t Addr) override {143 // Terminators mark the end of a basic block which means the sequentially144 // next instruction will be the first of another basic block and the current145 // state will typically not be valid anymore. For calls, we assume all146 // registers may be clobbered by the callee (TODO: should we take the147 // calling convention into account?).148 if (isTerminator(Inst) || isCall(Inst)) {149 resetState();150 return;151 }152 153 switch (Inst.getOpcode()) {154 default: {155 // Clear the state of all defined registers for instructions that we don't156 // explicitly support.157 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();158 for (unsigned I = 0; I < NumDefs; ++I) {159 auto DefReg = Inst.getOperand(I).getReg();160 if (isGPR(DefReg))161 setGPRState(DefReg, std::nullopt);162 }163 break;164 }165 case LoongArch::PCADDU18I:166 setGPRState(167 Inst.getOperand(0).getReg(),168 Addr + SignExtend64<38>(169 static_cast<uint64_t>(Inst.getOperand(1).getImm()) << 18));170 break;171 }172 }173 174 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,175 uint64_t &Target) const override {176 unsigned NumOps = Inst.getNumOperands();177 if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||178 Inst.getOpcode() == LoongArch::BL) {179 Target = Addr + Inst.getOperand(NumOps - 1).getImm();180 return true;181 }182 183 if (Inst.getOpcode() == LoongArch::JIRL) {184 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {185 Target = *TargetRegState + Inst.getOperand(2).getImm();186 return true;187 }188 return false;189 }190 191 return false;192 }193 194 bool isTerminator(const MCInst &Inst) const override {195 if (MCInstrAnalysis::isTerminator(Inst))196 return true;197 198 switch (Inst.getOpcode()) {199 default:200 return false;201 case LoongArch::JIRL:202 return Inst.getOperand(0).getReg() == LoongArch::R0;203 }204 }205 206 bool isCall(const MCInst &Inst) const override {207 if (MCInstrAnalysis::isCall(Inst))208 return true;209 210 switch (Inst.getOpcode()) {211 default:212 return false;213 case LoongArch::JIRL:214 return Inst.getOperand(0).getReg() != LoongArch::R0;215 }216 }217 218 bool isReturn(const MCInst &Inst) const override {219 if (MCInstrAnalysis::isReturn(Inst))220 return true;221 222 switch (Inst.getOpcode()) {223 default:224 return false;225 case LoongArch::JIRL:226 return Inst.getOperand(0).getReg() == LoongArch::R0 &&227 Inst.getOperand(1).getReg() == LoongArch::R1;228 }229 }230 231 bool isBranch(const MCInst &Inst) const override {232 if (MCInstrAnalysis::isBranch(Inst))233 return true;234 235 switch (Inst.getOpcode()) {236 default:237 return false;238 case LoongArch::JIRL:239 return Inst.getOperand(0).getReg() == LoongArch::R0 &&240 Inst.getOperand(1).getReg() != LoongArch::R1;241 }242 }243 244 bool isUnconditionalBranch(const MCInst &Inst) const override {245 if (MCInstrAnalysis::isUnconditionalBranch(Inst))246 return true;247 248 switch (Inst.getOpcode()) {249 default:250 return false;251 case LoongArch::JIRL:252 return Inst.getOperand(0).getReg() == LoongArch::R0 &&253 Inst.getOperand(1).getReg() != LoongArch::R1;254 }255 }256 257 bool isIndirectBranch(const MCInst &Inst) const override {258 if (MCInstrAnalysis::isIndirectBranch(Inst))259 return true;260 261 switch (Inst.getOpcode()) {262 default:263 return false;264 case LoongArch::JIRL:265 return Inst.getOperand(0).getReg() == LoongArch::R0 &&266 Inst.getOperand(1).getReg() != LoongArch::R1;267 }268 }269};270 271} // end namespace272 273static MCInstrAnalysis *createLoongArchInstrAnalysis(const MCInstrInfo *Info) {274 return new LoongArchMCInstrAnalysis(Info);275}276 277namespace {278MCStreamer *createLoongArchELFStreamer(const Triple &T, MCContext &Context,279 std::unique_ptr<MCAsmBackend> &&MAB,280 std::unique_ptr<MCObjectWriter> &&MOW,281 std::unique_ptr<MCCodeEmitter> &&MCE) {282 return createLoongArchELFStreamer(Context, std::move(MAB), std::move(MOW),283 std::move(MCE));284}285} // end namespace286 287extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void288LLVMInitializeLoongArchTargetMC() {289 for (Target *T : {&getTheLoongArch32Target(), &getTheLoongArch64Target()}) {290 TargetRegistry::RegisterMCRegInfo(*T, createLoongArchMCRegisterInfo);291 TargetRegistry::RegisterMCInstrInfo(*T, createLoongArchMCInstrInfo);292 TargetRegistry::RegisterMCSubtargetInfo(*T, createLoongArchMCSubtargetInfo);293 TargetRegistry::RegisterMCAsmInfo(*T, createLoongArchMCAsmInfo);294 TargetRegistry::RegisterMCCodeEmitter(*T, createLoongArchMCCodeEmitter);295 TargetRegistry::RegisterMCAsmBackend(*T, createLoongArchAsmBackend);296 TargetRegistry::RegisterMCInstPrinter(*T, createLoongArchMCInstPrinter);297 TargetRegistry::RegisterMCInstrAnalysis(*T, createLoongArchInstrAnalysis);298 TargetRegistry::RegisterELFStreamer(*T, createLoongArchELFStreamer);299 TargetRegistry::RegisterObjectTargetStreamer(300 *T, createLoongArchObjectTargetStreamer);301 TargetRegistry::RegisterAsmTargetStreamer(*T,302 createLoongArchAsmTargetStreamer);303 }304}305