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1//===-- M68kInstrBits.td - Bit Manipulation Instrs ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file describes the bit manipulation instructions in the M68k11/// architecture. Here is the current status of the file:12///13/// Machine:14///15/// BCHG [~] BCLR [~] BSET [~] BTST [~]16///17/// Map:18///19/// [ ] - was not touched at all20/// [!] - requires extarnal stuff implemented21/// [~] - in progress but usable22/// [x] - done23///24//===----------------------------------------------------------------------===//25 26//===----------------------------------------------------------------------===//27// BTST28//===----------------------------------------------------------------------===//29 30/// ------------+---------+---------+---------+---------31/// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 032/// ------------+---------+---------+---------+---------33/// 0 0 0 0 | REG | OP MODE | MODE | REG34/// ------------+---------+---------+---------+---------35class MxBITEnc_R<bits<3> opmode, MxEncMemOp dst_enc, string bitno_name> {36 dag Value = (ascend37 (descend 0b0000,38 (operand "$"#bitno_name, 3),39 opmode, dst_enc.EA40 ),41 dst_enc.Supplement42 );43}44 45/// ---------------------+---------+---------+---------46/// F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 047/// ---------------------+---------+---------+---------48/// 0 0 0 0 1 0 0 | OP MODE | MODE | REG49/// ---------------------+--+------+---------+---------50/// 0 0 0 0 0 0 0 0 | BIT NUMBER51/// ------------------------+--------------------------52class MxBITEnc_I<bits<3> opmode, MxEncMemOp dst_enc, string bitno_name> {53 dag Value = (ascend54 (descend 0b0000100, opmode, dst_enc.EA),55 (descend 0b00000000, (operand "$"#bitno_name, 8)),56 dst_enc.Supplement57 );58}59 60let Defs = [CCR] in {61class MxBIT_RR<string MN, bits<3> OPMODE, MxType TYPE>62 : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.ROp:$bitno),63 MN#"\t$bitno, $dst"> {64 let Inst = MxBITEnc_R<OPMODE, MxEncAddrMode_r<"dst">, "bitno">.Value;65}66 67class MxBIT_RI<string MN, bits<3> OPMODE, MxType TYPE>68 : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.IOp:$bitno),69 MN#"\t$bitno, $dst"> {70 let Inst = MxBITEnc_I<OPMODE, MxEncAddrMode_r<"dst">, "bitno">.Value;71}72 73class MxBIT_MR<string MN, bits<3> OPMODE, MxType TYPE,74 MxOperand MEMOpd, MxEncMemOp DST_ENC>75 : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$bitno),76 MN#"\t$bitno, $dst"> {77 let Inst = MxBITEnc_R<OPMODE, DST_ENC, "bitno">.Value;78}79 80class MxBIT_MI<string MN, bits<3> OPMODE, MxType TYPE,81 MxOperand MEMOpd, MxEncMemOp DST_ENC>82 : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$bitno),83 MN#"\t$bitno, $dst"> {84 let Inst = MxBITEnc_I<OPMODE, DST_ENC, "bitno">.Value;85}86} // Defs = [CCR]87 88def BTST8qd : MxBIT_MR<"btst", 0b100, MxType8d, MxType8.QOp,89 MxEncAddrMode_q<"dst">>;90def BTST8kd : MxBIT_MR<"btst", 0b100, MxType8d, MxType8.KOp,91 MxEncAddrMode_k<"dst">>;92def BTST8qi : MxBIT_MI<"btst", 0b000, MxType8d, MxType8.QOp,93 MxEncAddrMode_q<"dst">>;94def BTST8ki : MxBIT_MI<"btst", 0b000, MxType8d, MxType8.KOp,95 MxEncAddrMode_k<"dst">>;96 97multiclass MxBIT<string MN, bits<3> OP, bits<3> OPI> {98 // Register Bit manipulation limited to 32 bits only99 def NAME#32dd : MxBIT_RR<MN, OP, MxType32d>;100 def NAME#32di : MxBIT_RI<MN, OPI, MxType32d>;101 102 // Memory Bit manipulation limited to 8 bits only103 def NAME#8jd : MxBIT_MR<MN, OP, MxType8d,104 MxType8.JOp, MxEncAddrMode_j<"dst">>;105 def NAME#8od : MxBIT_MR<MN, OP, MxType8d,106 MxType8.OOp, MxEncAddrMode_o<"dst">>;107 def NAME#8ed : MxBIT_MR<MN, OP, MxType8d,108 MxType8.EOp, MxEncAddrMode_e<"dst">>;109 def NAME#8pd : MxBIT_MR<MN, OP, MxType8d,110 MxType8.POp, MxEncAddrMode_p<"dst">>;111 def NAME#8fd : MxBIT_MR<MN, OP, MxType8d,112 MxType8.FOp, MxEncAddrMode_f<"dst">>;113 114 def NAME#8ji : MxBIT_MI<MN, OPI, MxType8d,115 MxType8.JOp, MxEncAddrMode_j<"dst">>;116 def NAME#8oi : MxBIT_MI<MN, OPI, MxType8d,117 MxType8.OOp, MxEncAddrMode_o<"dst">>;118 def NAME#8ei : MxBIT_MI<MN, OPI, MxType8d,119 MxType8.EOp, MxEncAddrMode_e<"dst">>;120 def NAME#8pi : MxBIT_MI<MN, OPI, MxType8d,121 MxType8.POp, MxEncAddrMode_p<"dst">>;122 def NAME#8fi : MxBIT_MI<MN, OPI, MxType8d,123 MxType8.FOp, MxEncAddrMode_f<"dst">>;124}125 126defm BCHG : MxBIT<"bchg", 0b101, 0b001>;127defm BCLR : MxBIT<"bclr", 0b110, 0b010>;128defm BSET : MxBIT<"bset", 0b111, 0b011>;129defm BTST : MxBIT<"btst", 0b100, 0b000>;130 131// Codegen patterns132 133multiclass MxBITPatR<MxInst INSTd, MxInst INSTi, SDNode NODE> {134def : Pat<(NODE MxType32d.VT:$dst, MxType32d.VT:$bitno),135 (INSTd MxType32d.ROp:$dst, MxType32d.ROp:$bitno)>;136def : Pat<(NODE MxType32d.VT:$dst, MxType32d.IPat:$bitno),137 (INSTi MxType32d.ROp:$dst, MxType32d.IOp:$bitno)>;138}139 140defm : MxBITPatR<BTST32dd, BTST32di, MxBtst>;141 142multiclass MxBITPatM<MxInst INSTd, MxInst INSTi, SDNode NODE, MxType TYPE,143 MxOperand MEMOpd, ComplexPattern MEMPat> {144def : Pat<(NODE (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno),145 (INSTd MEMOpd:$dst, TYPE.ROp:$bitno)>;146def : Pat<(NODE (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno),147 (INSTi MEMOpd:$dst, TYPE.IOp:$bitno)>;148}149 150defm : MxBITPatM<BTST8qd, BTST8qi, MxBtst,151 MxType8d, MxType8.QOp, MxType8.QPat>;152defm : MxBITPatM<BTST8kd, BTST8ki, MxBtst,153 MxType8d, MxType8.KOp, MxType8.KPat>;154defm : MxBITPatM<BTST8jd, BTST8ji, MxBtst,155 MxType8d, MxType8.JOp, MxType8.JPat>;156defm : MxBITPatM<BTST8od, BTST8oi, MxBtst,157 MxType8d, MxType8.OOp, MxType8.OPat>;158defm : MxBITPatM<BTST8ed, BTST8ei, MxBtst,159 MxType8d, MxType8.EOp, MxType8.EPat>;160defm : MxBITPatM<BTST8pd, BTST8pi, MxBtst,161 MxType8d, MxType8.POp, MxType8.PPat>;162defm : MxBITPatM<BTST8fd, BTST8fi, MxBtst,163 MxType8d, MxType8.FOp, MxType8.FPat>;164