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1//===-- M68kInstrCompiler.td - Pseudos and Patterns --------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file describes the various pseudo instructions used by the compiler,11/// as well as Pat patterns used during instruction selection.12///13//===----------------------------------------------------------------------===//14 15//===----------------------------------------------------------------------===//16// ConstantPool, GlobalAddress, ExternalSymbol, and JumpTable17//===----------------------------------------------------------------------===//18 19def : Pat<(i32 (MxWrapper tconstpool :$src)), (MOV32ri tconstpool :$src)>;20def : Pat<(i32 (MxWrapper tglobaladdr :$src)), (MOV32ri tglobaladdr :$src)>;21def : Pat<(i32 (MxWrapper texternalsym :$src)), (MOV32ri texternalsym :$src)>;22def : Pat<(i32 (MxWrapper tjumptable :$src)), (MOV32ri tjumptable :$src)>;23def : Pat<(i32 (MxWrapper tblockaddress :$src)), (MOV32ri tblockaddress :$src)>;24 25def : Pat<(add MxDRD32:$src, (MxWrapper tconstpool:$opd)),26 (ADD32di MxDRD32:$src, tconstpool:$opd)>;27def : Pat<(add MxARD32:$src, (MxWrapper tjumptable:$opd)),28 (ADD32ai MxARD32:$src, tjumptable:$opd)>;29def : Pat<(add MxARD32:$src, (MxWrapper tglobaladdr :$opd)),30 (ADD32ai MxARD32:$src, tglobaladdr:$opd)>;31def : Pat<(add MxARD32:$src, (MxWrapper texternalsym:$opd)),32 (ADD32ai MxARD32:$src, texternalsym:$opd)>;33def : Pat<(add MxARD32:$src, (MxWrapper tblockaddress:$opd)),34 (ADD32ai MxARD32:$src, tblockaddress:$opd)>;35 36def : Pat<(store (i32 (MxWrapper tglobaladdr:$src)), iPTR:$dst),37 (MOV32ji MxARI32:$dst, tglobaladdr:$src)>;38def : Pat<(store (i32 (MxWrapper texternalsym:$src)), iPTR:$dst),39 (MOV32ji MxARI32:$dst, texternalsym:$src)>;40def : Pat<(store (i32 (MxWrapper tblockaddress:$src)), iPTR:$dst),41 (MOV32ji MxARI32:$dst, tblockaddress:$src)>;42 43def : Pat<(i32 (MxWrapperPC tconstpool :$src)), (LEA32q tconstpool :$src)>;44def : Pat<(i32 (MxWrapperPC tglobaladdr :$src)), (LEA32q tglobaladdr :$src)>;45def : Pat<(i32 (MxWrapperPC texternalsym :$src)), (LEA32q texternalsym :$src)>;46def : Pat<(i32 (MxWrapperPC tjumptable :$src)), (LEA32q tjumptable :$src)>;47def : Pat<(i32 (MxWrapperPC tblockaddress :$src)), (LEA32q tblockaddress :$src)>;48 49 50//===----------------------------------------------------------------------===//51// Conditional Move Pseudo Instructions52//53// CMOV* - Used to implement the SELECT DAG operation. Expanded after54// instruction selection into a branch sequence.55//===----------------------------------------------------------------------===//56 57let usesCustomInserter = 1, Uses = [CCR] in58class MxCMove<MxType TYPE>59 : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$t, TYPE.ROp:$f, i8imm:$cond),60 [(set TYPE.VT:$dst,61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;62 63def CMOV8d : MxCMove<MxType8d>;64def CMOV16d : MxCMove<MxType16d>;65def CMOV32r : MxCMove<MxType32r>;66 67 68//===----------------------------------------------------------------------===//69// Calls70//===----------------------------------------------------------------------===//71 72// ADJCALLSTACKDOWN/UP implicitly use/def %SP because they may be expanded into73// a stack adjustment and the codegen must know that they may modify the stack74// pointer before prolog-epilog rewriting occurs.75// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become76// sub / add which can clobber CCR.77let Defs = [SP, CCR], Uses = [SP] in {78 79 def ADJCALLSTACKDOWN80 : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),81 [(MxCallSeqStart timm:$amt1, timm:$amt2)]>;82 83 def ADJCALLSTACKUP84 : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),85 [(MxCallSeqEnd timm:$amt1, timm:$amt2)]>;86 87} // Defs88 89//===----------------------------------------------------------------------===//90// Tail Call91//===----------------------------------------------------------------------===//92 93// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they94// can never use callee-saved registers. That is the purpose of the XR32_TC95// register classes.96 97// FIXME TC is disabled for PIC mode because the global base98// register which is part of the address mode may be assigned a99// callee-saved register.100def : Pat<(MxTCRet (load MxCP_ARII:$dst), imm:$adj),101 (TCRETURNj (MOV32af_TC MxARII32:$dst), imm:$adj)>,102 Requires<[IsNotPIC]>;103 104def : Pat<(MxTCRet AR32_TC:$dst, imm:$adj),105 (TCRETURNj MxARI32_TC:$dst, imm:$adj)>;106 107def : Pat<(MxTCRet (i32 tglobaladdr:$dst), imm:$adj),108 (TCRETURNq MxPCD32:$dst, imm:$adj)>;109 110def : Pat<(MxTCRet (i32 texternalsym:$dst), imm:$adj),111 (TCRETURNq MxPCD32:$dst, imm:$adj)>;112 113 114//===----------------------------------------------------------------------===//115// Segmented Stack116//117// When using segmented stacks these are lowered into instructions which first118// check if the current stacklet has enough free memory. If it does, memory is119// allocated by bumping the stack pointer. Otherwise memory is allocated from120// the heap.121//===----------------------------------------------------------------------===//122 123let Defs = [SP, CCR], Uses = [SP] in124let usesCustomInserter = 1 in125def SALLOCA : MxPseudo<(outs MxARD32:$dst), (ins MxARD32:$size),126 [(set iPTR:$dst, (MxSegAlloca iPTR:$size))]>;127