967 lines · cpp
1//===-- M68kInstrInfo.cpp - M68k Instruction Information --------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file contains the M68k declaration of the TargetInstrInfo class.11///12//===----------------------------------------------------------------------===//13 14#include "M68kInstrInfo.h"15 16#include "M68kInstrBuilder.h"17#include "M68kMachineFunction.h"18#include "M68kTargetMachine.h"19#include "MCTargetDesc/M68kMCCodeEmitter.h"20 21#include "llvm/ADT/STLExtras.h"22#include "llvm/ADT/ScopeExit.h"23#include "llvm/CodeGen/LivePhysRegs.h"24#include "llvm/CodeGen/LiveVariables.h"25#include "llvm/CodeGen/MachineInstrBuilder.h"26#include "llvm/CodeGen/MachineOperand.h"27#include "llvm/CodeGen/MachineRegisterInfo.h"28#include "llvm/CodeGenTypes/MachineValueType.h"29#include "llvm/MC/TargetRegistry.h"30#include "llvm/Support/ErrorHandling.h"31#include "llvm/Support/Regex.h"32 33#include <functional>34 35using namespace llvm;36 37#define DEBUG_TYPE "M68k-instr-info"38 39#define GET_INSTRINFO_CTOR_DTOR40#include "M68kGenInstrInfo.inc"41 42// Pin the vtable to this file.43void M68kInstrInfo::anchor() {}44 45M68kInstrInfo::M68kInstrInfo(const M68kSubtarget &STI)46 : M68kGenInstrInfo(STI, RI, M68k::ADJCALLSTACKDOWN, M68k::ADJCALLSTACKUP, 0,47 M68k::RET),48 Subtarget(STI), RI(STI) {}49 50static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc) {51 switch (BrOpc) {52 default:53 return M68k::COND_INVALID;54 case M68k::Beq8:55 return M68k::COND_EQ;56 case M68k::Bne8:57 return M68k::COND_NE;58 case M68k::Blt8:59 return M68k::COND_LT;60 case M68k::Ble8:61 return M68k::COND_LE;62 case M68k::Bgt8:63 return M68k::COND_GT;64 case M68k::Bge8:65 return M68k::COND_GE;66 case M68k::Bcs8:67 return M68k::COND_CS;68 case M68k::Bls8:69 return M68k::COND_LS;70 case M68k::Bhi8:71 return M68k::COND_HI;72 case M68k::Bcc8:73 return M68k::COND_CC;74 case M68k::Bmi8:75 return M68k::COND_MI;76 case M68k::Bpl8:77 return M68k::COND_PL;78 case M68k::Bvs8:79 return M68k::COND_VS;80 case M68k::Bvc8:81 return M68k::COND_VC;82 }83}84 85bool M68kInstrInfo::AnalyzeBranchImpl(MachineBasicBlock &MBB,86 MachineBasicBlock *&TBB,87 MachineBasicBlock *&FBB,88 SmallVectorImpl<MachineOperand> &Cond,89 bool AllowModify) const {90 91 auto UncondBranch =92 std::pair<MachineBasicBlock::reverse_iterator, MachineBasicBlock *>{93 MBB.rend(), nullptr};94 95 // Erase any instructions if allowed at the end of the scope.96 std::vector<std::reference_wrapper<llvm::MachineInstr>> EraseList;97 auto FinalizeOnReturn = llvm::make_scope_exit([&EraseList] {98 for (auto &Ref : EraseList)99 Ref.get().eraseFromParent();100 });101 102 // Start from the bottom of the block and work up, examining the103 // terminator instructions.104 for (auto iter = MBB.rbegin(); iter != MBB.rend(); iter = std::next(iter)) {105 106 unsigned Opcode = iter->getOpcode();107 108 if (iter->isDebugInstr())109 continue;110 111 // Working from the bottom, when we see a non-terminator instruction, we're112 // done.113 if (!isUnpredicatedTerminator(*iter))114 break;115 116 // A terminator that isn't a branch can't easily be handled by this117 // analysis.118 if (!iter->isBranch())119 return true;120 121 // Handle unconditional branches.122 if (Opcode == M68k::BRA8 || Opcode == M68k::BRA16) {123 if (!iter->getOperand(0).isMBB())124 return true;125 UncondBranch = {iter, iter->getOperand(0).getMBB()};126 127 // TBB is used to indicate the unconditional destination.128 TBB = UncondBranch.second;129 130 if (!AllowModify)131 continue;132 133 // If the block has any instructions after a JMP, erase them.134 EraseList.insert(EraseList.begin(), MBB.rbegin(), iter);135 136 Cond.clear();137 FBB = nullptr;138 139 // Erase the JMP if it's equivalent to a fall-through.140 if (MBB.isLayoutSuccessor(UncondBranch.second)) {141 TBB = nullptr;142 EraseList.push_back(*iter);143 UncondBranch = {MBB.rend(), nullptr};144 }145 146 continue;147 }148 149 // Handle conditional branches.150 auto BranchCode = M68k::GetCondFromBranchOpc(Opcode);151 152 // Can't handle indirect branch.153 if (BranchCode == M68k::COND_INVALID)154 return true;155 156 // In practice we should never have an undef CCR operand, if we do157 // abort here as we are not prepared to preserve the flag.158 // ??? Is this required?159 // if (iter->getOperand(1).isUndef())160 // return true;161 162 // Working from the bottom, handle the first conditional branch.163 if (Cond.empty()) {164 if (!iter->getOperand(0).isMBB())165 return true;166 MachineBasicBlock *CondBranchTarget = iter->getOperand(0).getMBB();167 168 // If we see something like this:169 //170 // bcc l1171 // bra l2172 // ...173 // l1:174 // ...175 // l2:176 if (UncondBranch.first != MBB.rend()) {177 178 assert(std::next(UncondBranch.first) == iter && "Wrong block layout.");179 180 // And we are allowed to modify the block and the target block of the181 // conditional branch is the direct successor of this block:182 //183 // bcc l1184 // bra l2185 // l1:186 // ...187 // l2:188 //189 // we change it to this if allowed:190 //191 // bncc l2192 // l1:193 // ...194 // l2:195 //196 // Which is a bit more efficient.197 if (AllowModify && MBB.isLayoutSuccessor(CondBranchTarget)) {198 199 BranchCode = GetOppositeBranchCondition(BranchCode);200 unsigned BNCC = GetCondBranchFromCond(BranchCode);201 202 BuildMI(MBB, *UncondBranch.first, MBB.rfindDebugLoc(iter), get(BNCC))203 .addMBB(UncondBranch.second);204 205 EraseList.push_back(*iter);206 EraseList.push_back(*UncondBranch.first);207 208 TBB = UncondBranch.second;209 FBB = nullptr;210 Cond.push_back(MachineOperand::CreateImm(BranchCode));211 212 // Otherwise preserve TBB, FBB and Cond as requested213 } else {214 TBB = CondBranchTarget;215 FBB = UncondBranch.second;216 Cond.push_back(MachineOperand::CreateImm(BranchCode));217 }218 219 UncondBranch = {MBB.rend(), nullptr};220 continue;221 }222 223 TBB = CondBranchTarget;224 FBB = nullptr;225 Cond.push_back(MachineOperand::CreateImm(BranchCode));226 227 continue;228 }229 230 // Handle subsequent conditional branches. Only handle the case where all231 // conditional branches branch to the same destination and their condition232 // opcodes fit one of the special multi-branch idioms.233 assert(Cond.size() == 1);234 assert(TBB);235 236 // If the conditions are the same, we can leave them alone.237 auto OldBranchCode = static_cast<M68k::CondCode>(Cond[0].getImm());238 if (!iter->getOperand(0).isMBB())239 return true;240 auto NewTBB = iter->getOperand(0).getMBB();241 if (OldBranchCode == BranchCode && TBB == NewTBB)242 continue;243 244 // If they differ we cannot do much here.245 return true;246 }247 248 return false;249}250 251bool M68kInstrInfo::analyzeBranch(MachineBasicBlock &MBB,252 MachineBasicBlock *&TBB,253 MachineBasicBlock *&FBB,254 SmallVectorImpl<MachineOperand> &Cond,255 bool AllowModify) const {256 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, AllowModify);257}258 259unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB,260 int *BytesRemoved) const {261 assert(!BytesRemoved && "code size not handled");262 263 MachineBasicBlock::iterator I = MBB.end();264 unsigned Count = 0;265 266 while (I != MBB.begin()) {267 --I;268 if (I->isDebugValue())269 continue;270 if (I->getOpcode() != M68k::BRA8 &&271 getCondFromBranchOpc(I->getOpcode()) == M68k::COND_INVALID)272 break;273 // Remove the branch.274 I->eraseFromParent();275 I = MBB.end();276 ++Count;277 }278 279 return Count;280}281 282unsigned M68kInstrInfo::insertBranch(283 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,284 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {285 // Shouldn't be a fall through.286 assert(TBB && "InsertBranch must not be told to insert a fallthrough");287 assert((Cond.size() == 1 || Cond.size() == 0) &&288 "M68k branch conditions have one component!");289 assert(!BytesAdded && "code size not handled");290 291 if (Cond.empty()) {292 // Unconditional branch?293 assert(!FBB && "Unconditional branch with multiple successors!");294 BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB);295 return 1;296 }297 298 // If FBB is null, it is implied to be a fall-through block.299 bool FallThru = FBB == nullptr;300 301 // Conditional branch.302 unsigned Count = 0;303 M68k::CondCode CC = (M68k::CondCode)Cond[0].getImm();304 unsigned Opc = GetCondBranchFromCond(CC);305 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);306 ++Count;307 if (!FallThru) {308 // Two-way Conditional branch. Insert the second branch.309 BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB);310 ++Count;311 }312 return Count;313}314 315void M68kInstrInfo::AddSExt(MachineBasicBlock &MBB,316 MachineBasicBlock::iterator I, DebugLoc DL,317 unsigned Reg, MVT From, MVT To) const {318 if (From == MVT::i8) {319 unsigned R = Reg;320 // EXT16 requires i16 register321 if (To == MVT::i32) {322 R = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);323 assert(R && "No viable SUB register available");324 }325 BuildMI(MBB, I, DL, get(M68k::EXT16), R).addReg(R);326 }327 328 if (To == MVT::i32)329 BuildMI(MBB, I, DL, get(M68k::EXT32), Reg).addReg(Reg);330}331 332void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB,333 MachineBasicBlock::iterator I, DebugLoc DL,334 unsigned Reg, MVT From, MVT To) const {335 336 unsigned Mask, And;337 if (From == MVT::i8)338 Mask = 0xFF;339 else340 Mask = 0xFFFF;341 342 if (To == MVT::i16)343 And = M68k::AND16di;344 else // i32345 And = M68k::AND32di;346 347 // TODO use xor r,r to decrease size348 BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask);349}350 351// Convert MOVI to the appropriate instruction (sequence) for setting352// the register to an immediate value.353bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const {354 Register Reg = MIB->getOperand(0).getReg();355 int64_t Imm = MIB->getOperand(1).getImm();356 bool IsAddressReg = false;357 358 const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID);359 const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID);360 const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID);361 362 if (AR16->contains(Reg) || AR32->contains(Reg))363 IsAddressReg = true;364 365 // We need to assign to the full register to make IV happy366 Register SReg =367 MVTSize == MVT::i32368 ? Reg369 : Register(RI.getMatchingMegaReg(Reg, IsAddressReg ? AR32 : DR32));370 assert(SReg && "No viable MEGA register available");371 372 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");373 374 // Sign extention doesn't matter if we only use the bottom 8 bits375 if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) {376 LLVM_DEBUG(dbgs() << "MOVEQ\n");377 378 MIB->setDesc(get(M68k::MOVQ));379 MIB->getOperand(0).setReg(SReg);380 381 // Counter the effects of sign-extension with a bitwise not.382 // This is only faster and smaller for 32 bit values.383 } else if (DR32->contains(Reg) && isUInt<8>(Imm)) {384 LLVM_DEBUG(dbgs() << "MOVEQ and NOT\n");385 386 MachineBasicBlock &MBB = *MIB->getParent();387 DebugLoc DL = MIB->getDebugLoc();388 389 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex8Lo);390 assert(SubReg && "No viable SUB register available");391 392 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::MOVQ), SReg).addImm(~Imm & 0xFF);393 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::NOT8d), SubReg).addReg(SubReg);394 395 MIB->removeFromParent();396 397 // Special case for setting address register to NULL (0)398 } else if (IsAddressReg && Imm == 0) {399 LLVM_DEBUG(dbgs() << "SUBA\n");400 401 MachineBasicBlock &MBB = *MIB->getParent();402 DebugLoc DL = MIB->getDebugLoc();403 404 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::SUB32ar), SReg)405 .addReg(SReg, RegState::Undef)406 .addReg(SReg, RegState::Undef);407 408 MIB->removeFromParent();409 410 // movea.w implicitly sign extends to the full register width,411 // so exploit that if the immediate fits in the correct range.412 //413 // TODO: use lea imm.w, %an for further constants when 16-bit414 // absolute addressing is implemented.415 } else if (AR32->contains(Reg) && isUInt<16>(Imm)) {416 LLVM_DEBUG(dbgs() << "MOVEA w/ implicit extend\n");417 418 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);419 assert(SubReg && "No viable SUB register available");420 421 MIB->setDesc(get(M68k::MOV16ai));422 MIB->getOperand(0).setReg(SubReg);423 424 // Fall back to a move with immediate425 } else {426 LLVM_DEBUG(dbgs() << "MOVE\n");427 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri));428 }429 430 return true;431}432 433bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst,434 MVT MVTSrc) const {435 unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;436 Register Dst = MIB->getOperand(0).getReg();437 Register Src = MIB->getOperand(1).getReg();438 439 assert(Dst != Src && "You cannot use the same Regs with MOVX_RR");440 441 const auto &TRI = getRegisterInfo();442 443 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);444 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);445 446 assert(RCDst && RCSrc && "Wrong use of MOVX_RR");447 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVX_RR");448 (void)RCSrc;449 450 // We need to find the super source register that matches the size of Dst451 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);452 assert(SSrc && "No viable MEGA register available");453 454 DebugLoc DL = MIB->getDebugLoc();455 456 // If it happens to that super source register is the destination register457 // we do nothing458 if (Dst == SSrc) {459 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n');460 MIB->eraseFromParent();461 } else { // otherwise we need to MOV462 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n");463 MIB->setDesc(get(Move));464 MIB->getOperand(1).setReg(SSrc);465 }466 467 return true;468}469 470/// Expand SExt MOVE pseudos into a MOV and a EXT if the operands are two471/// different registers or just EXT if it is the same register472bool M68kInstrInfo::ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned,473 MVT MVTDst, MVT MVTSrc) const {474 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");475 476 unsigned Move;477 478 if (MVTDst == MVT::i16)479 Move = M68k::MOV16rr;480 else // i32481 Move = M68k::MOV32rr;482 483 Register Dst = MIB->getOperand(0).getReg();484 Register Src = MIB->getOperand(1).getReg();485 486 assert(Dst != Src && "You cannot use the same Regs with MOVSX_RR");487 488 const auto &TRI = getRegisterInfo();489 490 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);491 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);492 493 assert(RCDst && RCSrc && "Wrong use of MOVSX_RR");494 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVSX_RR");495 (void)RCSrc;496 497 // We need to find the super source register that matches the size of Dst498 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);499 assert(SSrc && "No viable MEGA register available");500 501 MachineBasicBlock &MBB = *MIB->getParent();502 DebugLoc DL = MIB->getDebugLoc();503 504 if (Dst != SSrc) {505 LLVM_DEBUG(dbgs() << "Move and " << '\n');506 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc);507 }508 509 if (IsSigned) {510 LLVM_DEBUG(dbgs() << "Sign Extend" << '\n');511 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);512 } else {513 LLVM_DEBUG(dbgs() << "Zero Extend" << '\n');514 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);515 }516 517 MIB->eraseFromParent();518 519 return true;520}521 522bool M68kInstrInfo::ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned,523 const MCInstrDesc &Desc, MVT MVTDst,524 MVT MVTSrc) const {525 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and ");526 527 Register Dst = MIB->getOperand(0).getReg();528 529 // We need the subreg of Dst to make instruction verifier happy because the530 // real machine instruction consumes and produces values of the same size and531 // the registers the will be used here fall into different classes and this532 // makes IV cry. We could use a bigger operation, but this will put some533 // pressure on cache and memory, so no.534 unsigned SubDst =535 RI.getSubReg(Dst, MVTSrc == MVT::i8 ? M68k::MxSubRegIndex8Lo536 : M68k::MxSubRegIndex16Lo);537 assert(SubDst && "No viable SUB register available");538 539 // Make this a plain move540 MIB->setDesc(Desc);541 MIB->getOperand(0).setReg(SubDst);542 543 MachineBasicBlock::iterator I = MIB.getInstr();544 I++;545 MachineBasicBlock &MBB = *MIB->getParent();546 DebugLoc DL = MIB->getDebugLoc();547 548 if (IsSigned) {549 LLVM_DEBUG(dbgs() << "Sign Extend" << '\n');550 AddSExt(MBB, I, DL, Dst, MVTSrc, MVTDst);551 } else {552 LLVM_DEBUG(dbgs() << "Zero Extend" << '\n');553 AddZExt(MBB, I, DL, Dst, MVTSrc, MVTDst);554 }555 556 return true;557}558 559bool M68kInstrInfo::ExpandPUSH_POP(MachineInstrBuilder &MIB,560 const MCInstrDesc &Desc, bool IsPush) const {561 MachineBasicBlock::iterator I = MIB.getInstr();562 I++;563 MachineBasicBlock &MBB = *MIB->getParent();564 MachineOperand MO = MIB->getOperand(0);565 DebugLoc DL = MIB->getDebugLoc();566 if (IsPush)567 BuildMI(MBB, I, DL, Desc).addReg(RI.getStackRegister()).add(MO);568 else569 BuildMI(MBB, I, DL, Desc, MO.getReg()).addReg(RI.getStackRegister());570 571 MIB->eraseFromParent();572 return true;573}574 575bool M68kInstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const {576 if (MIB->getOpcode() == M68k::MOV8cd) {577 // Promote used register to the next class578 MachineOperand &Opd = MIB->getOperand(1);579 Opd.setReg(getRegisterInfo().getMatchingSuperReg(580 Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass));581 }582 583 // Replace the pseudo instruction with the real one584 if (IsToCCR)585 MIB->setDesc(get(M68k::MOV16cd));586 else587 // FIXME M68010 or later is required588 MIB->setDesc(get(M68k::MOV16dc));589 590 return true;591}592 593bool M68kInstrInfo::ExpandMOVEM(MachineInstrBuilder &MIB,594 const MCInstrDesc &Desc, bool IsRM) const {595 int Reg = 0, Offset = 0, Base = 0;596 auto DL = MIB->getDebugLoc();597 auto MI = MIB.getInstr();598 auto &MBB = *MIB->getParent();599 600 if (IsRM) {601 Reg = MIB->getOperand(0).getReg();602 Offset = MIB->getOperand(1).getImm();603 Base = MIB->getOperand(2).getReg();604 } else {605 Offset = MIB->getOperand(0).getImm();606 Base = MIB->getOperand(1).getReg();607 Reg = MIB->getOperand(2).getReg();608 }609 610 unsigned Mask = 1 << RI.getSpillRegisterOrder(Reg);611 if (IsRM) {612 BuildMI(MBB, MI, DL, Desc)613 .addImm(Mask)614 .addImm(Offset)615 .addReg(Base)616 .addReg(Reg, RegState::ImplicitDefine)617 .copyImplicitOps(*MIB);618 } else {619 BuildMI(MBB, MI, DL, Desc)620 .addImm(Offset)621 .addReg(Base)622 .addImm(Mask)623 .addReg(Reg, RegState::Implicit)624 .copyImplicitOps(*MIB);625 }626 627 MIB->eraseFromParent();628 629 return true;630}631 632/// Expand a single-def pseudo instruction to a two-addr633/// instruction with two undef reads of the register being defined.634/// This is used for mapping:635/// %d0 = SETCS_C32d636/// to:637/// %d0 = SUBX32dd %d0<undef>, %d0<undef>638///639static bool Expand2AddrUndef(MachineInstrBuilder &MIB,640 const MCInstrDesc &Desc) {641 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");642 Register Reg = MIB->getOperand(0).getReg();643 MIB->setDesc(Desc);644 645 // MachineInstr::addOperand() will insert explicit operands before any646 // implicit operands.647 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);648 // But we don't trust that.649 assert(MIB->getOperand(1).getReg() == Reg &&650 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");651 return true;652}653 654bool M68kInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {655 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);656 switch (MI.getOpcode()) {657 case M68k::PUSH8d:658 return ExpandPUSH_POP(MIB, get(M68k::MOV8ed), true);659 case M68k::PUSH16d:660 return ExpandPUSH_POP(MIB, get(M68k::MOV16er), true);661 case M68k::PUSH32r:662 return ExpandPUSH_POP(MIB, get(M68k::MOV32er), true);663 664 case M68k::POP8d:665 return ExpandPUSH_POP(MIB, get(M68k::MOV8do), false);666 case M68k::POP16d:667 return ExpandPUSH_POP(MIB, get(M68k::MOV16ro), false);668 case M68k::POP32r:669 return ExpandPUSH_POP(MIB, get(M68k::MOV32ro), false);670 671 case M68k::SETCS_C8d:672 return Expand2AddrUndef(MIB, get(M68k::SUBX8dd));673 case M68k::SETCS_C16d:674 return Expand2AddrUndef(MIB, get(M68k::SUBX16dd));675 case M68k::SETCS_C32d:676 return Expand2AddrUndef(MIB, get(M68k::SUBX32dd));677 }678 return false;679}680 681bool M68kInstrInfo::isPCRelRegisterOperandLegal(682 const MachineOperand &MO) const {683 assert(MO.isReg());684 685 // Check whether this MO belongs to an instruction with addressing mode 'k',686 // Refer to TargetInstrInfo.h for more information about this function.687 688 const MachineInstr *MI = MO.getParent();689 const unsigned NameIndices = M68kInstrNameIndices[MI->getOpcode()];690 StringRef InstrName(&M68kInstrNameData[NameIndices]);691 const unsigned OperandNo = MO.getOperandNo();692 693 // If this machine operand is the 2nd operand, then check694 // whether the instruction has destination addressing mode 'k'.695 if (OperandNo == 1)696 return Regex("[A-Z]+(8|16|32)k[a-z](_TC)?$").match(InstrName);697 698 // If this machine operand is the last one, then check699 // whether the instruction has source addressing mode 'k'.700 if (OperandNo == MI->getNumExplicitOperands() - 1)701 return Regex("[A-Z]+(8|16|32)[a-z]k(_TC)?$").match(InstrName);702 703 return false;704}705 706void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,707 MachineBasicBlock::iterator MI,708 const DebugLoc &DL, Register DstReg,709 Register SrcReg, bool KillSrc,710 bool RenamableDest, bool RenamableSrc) const {711 unsigned Opc = 0;712 713 // First deal with the normal symmetric copies.714 if (M68k::XR32RegClass.contains(DstReg, SrcReg))715 Opc = M68k::MOV32rr;716 else if (M68k::XR16RegClass.contains(DstReg, SrcReg))717 Opc = M68k::MOV16rr;718 else if (M68k::DR8RegClass.contains(DstReg, SrcReg))719 Opc = M68k::MOV8dd;720 721 if (Opc) {722 BuildMI(MBB, MI, DL, get(Opc), DstReg)723 .addReg(SrcReg, getKillRegState(KillSrc));724 return;725 }726 727 // Now deal with asymmetrically sized copies. The cases that follow are upcast728 // moves.729 //730 // NOTE731 // These moves are not aware of type nature of these values and thus732 // won't do any SExt or ZExt and upper bits will basically contain garbage.733 MachineInstrBuilder MIB(*MBB.getParent(), MI);734 if (M68k::DR8RegClass.contains(SrcReg)) {735 if (M68k::XR16RegClass.contains(DstReg))736 Opc = M68k::MOVXd16d8;737 else if (M68k::XR32RegClass.contains(DstReg))738 Opc = M68k::MOVXd32d8;739 } else if (M68k::XR16RegClass.contains(SrcReg) &&740 M68k::XR32RegClass.contains(DstReg))741 Opc = M68k::MOVXd32d16;742 743 if (Opc) {744 BuildMI(MBB, MI, DL, get(Opc), DstReg)745 .addReg(SrcReg, getKillRegState(KillSrc));746 return;747 }748 749 bool FromCCR = SrcReg == M68k::CCR;750 bool FromSR = SrcReg == M68k::SR;751 bool ToCCR = DstReg == M68k::CCR;752 bool ToSR = DstReg == M68k::SR;753 754 if (FromCCR) {755 if (M68k::DR8RegClass.contains(DstReg)) {756 Opc = M68k::MOV8dc;757 } else if (M68k::DR16RegClass.contains(DstReg)) {758 Opc = M68k::MOV16dc;759 } else if (M68k::DR32RegClass.contains(DstReg)) {760 Opc = M68k::MOV16dc;761 } else {762 LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');763 llvm_unreachable("Invalid register for MOVE from CCR");764 }765 } else if (ToCCR) {766 if (M68k::DR8RegClass.contains(SrcReg)) {767 Opc = M68k::MOV8cd;768 } else if (M68k::DR16RegClass.contains(SrcReg)) {769 Opc = M68k::MOV16cd;770 } else if (M68k::DR32RegClass.contains(SrcReg)) {771 Opc = M68k::MOV16cd;772 } else {773 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");774 llvm_unreachable("Invalid register for MOVE to CCR");775 }776 } else if (FromSR || ToSR)777 llvm_unreachable("Cannot emit SR copy instruction");778 779 if (Opc) {780 BuildMI(MBB, MI, DL, get(Opc), DstReg)781 .addReg(SrcReg, getKillRegState(KillSrc));782 return;783 }784 785 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "786 << RI.getName(DstReg) << '\n');787 llvm_unreachable("Cannot emit physreg copy instruction");788}789 790namespace {791unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,792 const TargetRegisterInfo *TRI,793 const M68kSubtarget &STI, bool load) {794 switch (TRI->getSpillSize(*RC)) {795 default:796 LLVM_DEBUG(797 dbgs() << "Cannot determine appropriate opcode for load/store to/from "798 << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC)799 << " with spill size " << TRI->getSpillSize(*RC) << '\n');800 llvm_unreachable("Unknown spill size");801 case 2:802 if (M68k::XR16RegClass.hasSubClassEq(RC))803 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;804 if (M68k::DR8RegClass.hasSubClassEq(RC))805 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;806 if (M68k::CCRCRegClass.hasSubClassEq(RC))807 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;808 llvm_unreachable("Unknown 2-byte regclass");809 case 4:810 if (M68k::XR32RegClass.hasSubClassEq(RC))811 return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;812 llvm_unreachable("Unknown 4-byte regclass");813 }814}815 816unsigned getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC,817 const TargetRegisterInfo *TRI,818 const M68kSubtarget &STI) {819 return getLoadStoreRegOpcode(SrcReg, RC, TRI, STI, false);820}821 822unsigned getLoadRegOpcode(unsigned DstReg, const TargetRegisterClass *RC,823 const TargetRegisterInfo *TRI,824 const M68kSubtarget &STI) {825 return getLoadStoreRegOpcode(DstReg, RC, TRI, STI, true);826}827} // end anonymous namespace828 829bool M68kInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,830 unsigned SubIdx, unsigned &Size,831 unsigned &Offset,832 const MachineFunction &MF) const {833 // The slot size must be the maximum size so we can easily use MOVEM.L834 Size = 4;835 Offset = 0;836 return true;837}838 839void M68kInstrInfo::storeRegToStackSlot(840 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,841 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,842 MachineInstr::MIFlag Flags) const {843 const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();844 assert(MFI.getObjectSize(FrameIndex) >= TRI.getSpillSize(*RC) &&845 "Stack slot is too small to store");846 (void)MFI;847 848 unsigned Opc = getStoreRegOpcode(SrcReg, RC, &TRI, Subtarget);849 DebugLoc DL = MBB.findDebugLoc(MI);850 // (0,FrameIndex) <- $reg851 M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIndex)852 .addReg(SrcReg, getKillRegState(IsKill));853}854 855void M68kInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,856 MachineBasicBlock::iterator MI,857 Register DstReg, int FrameIndex,858 const TargetRegisterClass *RC,859 Register VReg,860 MachineInstr::MIFlag Flags) const {861 const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();862 assert(MFI.getObjectSize(FrameIndex) >= TRI.getSpillSize(*RC) &&863 "Stack slot is too small to load");864 (void)MFI;865 866 unsigned Opc = getLoadRegOpcode(DstReg, RC, &TRI, Subtarget);867 DebugLoc DL = MBB.findDebugLoc(MI);868 M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FrameIndex);869}870 871/// Return a virtual register initialized with the global base register872/// value. Output instructions required to initialize the register in the873/// function entry block, if necessary.874///875/// TODO Move this function to M68kMachineFunctionInfo.876unsigned M68kInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {877 M68kMachineFunctionInfo *MxFI = MF->getInfo<M68kMachineFunctionInfo>();878 unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();879 if (GlobalBaseReg != 0)880 return GlobalBaseReg;881 882 // Create the register. The code to initialize it is inserted later,883 // by the M68kGlobalBaseReg pass (below).884 //885 // NOTE886 // Normally M68k uses A5 register as global base pointer but this will887 // create unnecessary spill if we use less then 4 registers in code; since A5888 // is callee-save anyway we could try to allocate caller-save first and if889 // lucky get one, otherwise it does not really matter which callee-save to890 // use.891 MachineRegisterInfo &RegInfo = MF->getRegInfo();892 GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);893 MxFI->setGlobalBaseReg(GlobalBaseReg);894 return GlobalBaseReg;895}896 897std::pair<unsigned, unsigned>898M68kInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {899 return std::make_pair(TF, 0u);900}901 902ArrayRef<std::pair<unsigned, const char *>>903M68kInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {904 using namespace M68kII;905 static const std::pair<unsigned, const char *> TargetFlags[] = {906 {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},907 {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},908 {MO_GOT, "m68k-got"},909 {MO_GOTOFF, "m68k-gotoff"},910 {MO_GOTPCREL, "m68k-gotpcrel"},911 {MO_PLT, "m68k-plt"},912 {MO_TLSGD, "m68k-tlsgd"},913 {MO_TLSLD, "m68k-tlsld"},914 {MO_TLSLDM, "m68k-tlsldm"},915 {MO_TLSIE, "m68k-tlsie"},916 {MO_TLSLE, "m68k-tlsle"}};917 return ArrayRef(TargetFlags);918}919 920#undef DEBUG_TYPE921#define DEBUG_TYPE "m68k-create-global-base-reg"922 923#define PASS_NAME "M68k PIC Global Base Reg Initialization"924 925namespace {926/// This initializes the PIC global base register927struct M68kGlobalBaseReg : public MachineFunctionPass {928 static char ID;929 M68kGlobalBaseReg() : MachineFunctionPass(ID) {}930 931 bool runOnMachineFunction(MachineFunction &MF) override {932 const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();933 M68kMachineFunctionInfo *MxFI = MF.getInfo<M68kMachineFunctionInfo>();934 935 unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();936 937 // If we didn't need a GlobalBaseReg, don't insert code.938 if (GlobalBaseReg == 0)939 return false;940 941 // Insert the set of GlobalBaseReg into the first MBB of the function942 MachineBasicBlock &FirstMBB = MF.front();943 MachineBasicBlock::iterator MBBI = FirstMBB.begin();944 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);945 const M68kInstrInfo *TII = STI.getInstrInfo();946 947 // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5948 BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)949 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);950 951 return true;952 }953 954 void getAnalysisUsage(AnalysisUsage &AU) const override {955 AU.setPreservesCFG();956 MachineFunctionPass::getAnalysisUsage(AU);957 }958};959char M68kGlobalBaseReg::ID = 0;960} // namespace961 962INITIALIZE_PASS(M68kGlobalBaseReg, DEBUG_TYPE, PASS_NAME, false, false)963 964FunctionPass *llvm::createM68kGlobalBaseRegPass() {965 return new M68kGlobalBaseReg();966}967