176 lines · cpp
1//===-- M68kTargetMachine.cpp - M68k Target Machine -------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file contains implementation for M68k target machine.11///12//===----------------------------------------------------------------------===//13 14#include "M68kTargetMachine.h"15#include "M68k.h"16#include "M68kMachineFunction.h"17#include "M68kSubtarget.h"18#include "M68kTargetObjectFile.h"19#include "TargetInfo/M68kTargetInfo.h"20#include "llvm/CodeGen/GlobalISel/IRTranslator.h"21#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"22#include "llvm/CodeGen/GlobalISel/Legalizer.h"23#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"24#include "llvm/CodeGen/Passes.h"25#include "llvm/CodeGen/TargetPassConfig.h"26#include "llvm/InitializePasses.h"27#include "llvm/MC/TargetRegistry.h"28#include "llvm/PassRegistry.h"29#include <memory>30#include <optional>31 32using namespace llvm;33 34#define DEBUG_TYPE "m68k"35 36extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() {37 RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget());38 auto *PR = PassRegistry::getPassRegistry();39 initializeGlobalISel(*PR);40 initializeM68kAsmPrinterPass(*PR);41 initializeM68kDAGToDAGISelLegacyPass(*PR);42 initializeM68kExpandPseudoPass(*PR);43 initializeM68kGlobalBaseRegPass(*PR);44 initializeM68kCollapseMOVEMPass(*PR);45}46 47namespace {48 49Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {50 // If not defined we default to static51 return RM.value_or(Reloc::Static);52}53 54CodeModel::Model getEffectiveCodeModel(std::optional<CodeModel::Model> CM,55 bool JIT) {56 if (!CM) {57 return CodeModel::Small;58 } else if (CM == CodeModel::Kernel) {59 llvm_unreachable("Kernel code model is not implemented yet");60 }61 return CM.value();62}63} // end anonymous namespace64 65M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT,66 StringRef CPU, StringRef FS,67 const TargetOptions &Options,68 std::optional<Reloc::Model> RM,69 std::optional<CodeModel::Model> CM,70 CodeGenOptLevel OL, bool JIT)71 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,72 getEffectiveRelocModel(RM),73 ::getEffectiveCodeModel(CM, JIT), OL),74 TLOF(std::make_unique<M68kELFTargetObjectFile>()),75 Subtarget(TT, CPU, FS, *this) {76 initAsmInfo();77}78 79M68kTargetMachine::~M68kTargetMachine() {}80 81const M68kSubtarget *82M68kTargetMachine::getSubtargetImpl(const Function &F) const {83 Attribute CPUAttr = F.getFnAttribute("target-cpu");84 Attribute FSAttr = F.getFnAttribute("target-features");85 86 auto CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;87 auto FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;88 89 auto &I = SubtargetMap[CPU + FS];90 if (!I) {91 // This needs to be done before we create a new subtarget since any92 // creation will depend on the TM and the code generation flags on the93 // function that reside in TargetOptions.94 resetTargetOptions(F);95 I = std::make_unique<M68kSubtarget>(TargetTriple, CPU, FS, *this);96 }97 return I.get();98}99 100MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(101 BumpPtrAllocator &Allocator, const Function &F,102 const TargetSubtargetInfo *STI) const {103 return M68kMachineFunctionInfo::create<M68kMachineFunctionInfo>(Allocator, F,104 STI);105}106 107//===----------------------------------------------------------------------===//108// Pass Pipeline Configuration109//===----------------------------------------------------------------------===//110 111namespace {112class M68kPassConfig : public TargetPassConfig {113public:114 M68kPassConfig(M68kTargetMachine &TM, PassManagerBase &PM)115 : TargetPassConfig(TM, PM) {}116 117 M68kTargetMachine &getM68kTargetMachine() const {118 return getTM<M68kTargetMachine>();119 }120 121 const M68kSubtarget &getM68kSubtarget() const {122 return *getM68kTargetMachine().getSubtargetImpl();123 }124 void addIRPasses() override;125 bool addIRTranslator() override;126 bool addLegalizeMachineIR() override;127 bool addRegBankSelect() override;128 bool addGlobalInstructionSelect() override;129 bool addInstSelector() override;130 void addPreSched2() override;131 void addPreEmitPass() override;132};133} // namespace134 135TargetPassConfig *M68kTargetMachine::createPassConfig(PassManagerBase &PM) {136 return new M68kPassConfig(*this, PM);137}138 139void M68kPassConfig::addIRPasses() {140 addPass(createAtomicExpandLegacyPass());141 TargetPassConfig::addIRPasses();142}143 144bool M68kPassConfig::addInstSelector() {145 // Install an instruction selector.146 addPass(createM68kISelDag(getM68kTargetMachine()));147 addPass(createM68kGlobalBaseRegPass());148 return false;149}150 151bool M68kPassConfig::addIRTranslator() {152 addPass(new IRTranslator());153 return false;154}155 156bool M68kPassConfig::addLegalizeMachineIR() {157 addPass(new Legalizer());158 return false;159}160 161bool M68kPassConfig::addRegBankSelect() {162 addPass(new RegBankSelect());163 return false;164}165 166bool M68kPassConfig::addGlobalInstructionSelect() {167 addPass(new InstructionSelect());168 return false;169}170 171void M68kPassConfig::addPreSched2() { addPass(createM68kExpandPseudoPass()); }172 173void M68kPassConfig::addPreEmitPass() {174 addPass(createM68kCollapseMOVEMPass());175}176