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1//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the interfaces that MSP430 uses to lower LLVM code into a10// selection DAG.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H15#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H16 17#include "MSP430.h"18#include "llvm/CodeGen/SelectionDAG.h"19#include "llvm/CodeGen/TargetLowering.h"20 21namespace llvm {22 class MSP430Subtarget;23 class MSP430TargetLowering : public TargetLowering {24 public:25 explicit MSP430TargetLowering(const TargetMachine &TM,26 const MSP430Subtarget &STI);27 28 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {29 return MVT::i8;30 }31 32 MVT::SimpleValueType getCmpLibcallReturnType() const override {33 return MVT::i16;34 }35 36 /// LowerOperation - Provide custom lowering hooks for some operations.37 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;38 39 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;40 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;41 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;42 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;43 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;44 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;45 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;46 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;47 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;48 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;49 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;50 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;51 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;52 53 TargetLowering::ConstraintType54 getConstraintType(StringRef Constraint) const override;55 std::pair<unsigned, const TargetRegisterClass *>56 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,57 StringRef Constraint, MVT VT) const override;58 59 /// isTruncateFree - Return true if it's free to truncate a value of type60 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in61 /// register R15W to i8 by referencing its sub-register R15B.62 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;63 bool isTruncateFree(EVT VT1, EVT VT2) const override;64 65 /// isZExtFree - Return true if any actual instruction that defines a value66 /// of type Ty1 implicit zero-extends the value to Ty2 in the result67 /// register. This does not necessarily include registers defined in unknown68 /// ways, such as incoming arguments, or copies from unknown virtual69 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not70 /// necessarily apply to truncate instructions. e.g. on msp430, all71 /// instructions that define 8-bit values implicit zero-extend the result72 /// out to 16 bits.73 bool isZExtFree(Type *Ty1, Type *Ty2) const override;74 bool isZExtFree(EVT VT1, EVT VT2) const override;75 76 bool isLegalICmpImmediate(int64_t) const override;77 bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;78 79 MachineBasicBlock *80 EmitInstrWithCustomInserter(MachineInstr &MI,81 MachineBasicBlock *BB) const override;82 MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,83 MachineBasicBlock *BB) const;84 85 private:86 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,87 CallingConv::ID CallConv, bool isVarArg,88 bool isTailCall,89 const SmallVectorImpl<ISD::OutputArg> &Outs,90 const SmallVectorImpl<SDValue> &OutVals,91 const SmallVectorImpl<ISD::InputArg> &Ins,92 const SDLoc &dl, SelectionDAG &DAG,93 SmallVectorImpl<SDValue> &InVals) const;94 95 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,96 bool isVarArg,97 const SmallVectorImpl<ISD::InputArg> &Ins,98 const SDLoc &dl, SelectionDAG &DAG,99 SmallVectorImpl<SDValue> &InVals) const;100 101 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,102 CallingConv::ID CallConv, bool isVarArg,103 const SmallVectorImpl<ISD::InputArg> &Ins,104 const SDLoc &dl, SelectionDAG &DAG,105 SmallVectorImpl<SDValue> &InVals) const;106 107 SDValue108 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,109 const SmallVectorImpl<ISD::InputArg> &Ins,110 const SDLoc &dl, SelectionDAG &DAG,111 SmallVectorImpl<SDValue> &InVals) const override;112 SDValue113 LowerCall(TargetLowering::CallLoweringInfo &CLI,114 SmallVectorImpl<SDValue> &InVals) const override;115 116 bool CanLowerReturn(CallingConv::ID CallConv,117 MachineFunction &MF,118 bool IsVarArg,119 const SmallVectorImpl<ISD::OutputArg> &Outs,120 LLVMContext &Context, const Type *RetTy) const override;121 122 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,123 const SmallVectorImpl<ISD::OutputArg> &Outs,124 const SmallVectorImpl<SDValue> &OutVals,125 const SDLoc &dl, SelectionDAG &DAG) const override;126 127 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,128 SDValue &Base,129 SDValue &Offset,130 ISD::MemIndexedMode &AM,131 SelectionDAG &DAG) const override;132 };133} // namespace llvm134 135#endif136