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1//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Declarations that describe the MSP430 register file11//===----------------------------------------------------------------------===//12 13class MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> {14 field bits<4> Num = num;15 let Namespace = "MSP430";16 let HWEncoding{3-0} = num;17 let AltNames = alt;18 let DwarfNumbers = [num];19}20 21class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,22 list<string> alt = []> 23 : RegisterWithSubRegs<n, subregs> {24 field bits<4> Num = num;25 let Namespace = "MSP430";26 let HWEncoding{3-0} = num;27 let AltNames = alt;28 let DwarfNumbers = [num];29}30 31//===----------------------------------------------------------------------===//32// Registers33//===----------------------------------------------------------------------===//34 35def PCB : MSP430Reg<0, "r0", ["pc"]>, DwarfRegNum<[16]>;36def SPB : MSP430Reg<1, "r1", ["sp"]>, DwarfRegNum<[17]>;37def SRB : MSP430Reg<2, "r2", ["sr"]>, DwarfRegNum<[18]>;38def CGB : MSP430Reg<3, "r3", ["cg"]>, DwarfRegNum<[19]>;39def R4B : MSP430Reg<4, "r4", ["fp"]>, DwarfRegNum<[20]>;40def R5B : MSP430Reg<5, "r5">, DwarfRegNum<[21]>;41def R6B : MSP430Reg<6, "r6">, DwarfRegNum<[22]>;42def R7B : MSP430Reg<7, "r7">, DwarfRegNum<[23]>;43def R8B : MSP430Reg<8, "r8">, DwarfRegNum<[24]>;44def R9B : MSP430Reg<9, "r9">, DwarfRegNum<[25]>;45def R10B : MSP430Reg<10, "r10">, DwarfRegNum<[26]>;46def R11B : MSP430Reg<11, "r11">, DwarfRegNum<[27]>;47def R12B : MSP430Reg<12, "r12">, DwarfRegNum<[28]>;48def R13B : MSP430Reg<13, "r13">, DwarfRegNum<[29]>;49def R14B : MSP430Reg<14, "r14">, DwarfRegNum<[30]>;50def R15B : MSP430Reg<15, "r15">, DwarfRegNum<[31]>;51 52def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }53 54let SubRegIndices = [subreg_8bit] in {55def PC : MSP430RegWithSubregs<0, "r0", [PCB], ["pc"]>, DwarfRegNum<[0]>;56def SP : MSP430RegWithSubregs<1, "r1", [SPB], ["sp"]>, DwarfRegNum<[1]>;57def SR : MSP430RegWithSubregs<2, "r2", [SRB], ["sr"]>, DwarfRegNum<[2]>;58def CG : MSP430RegWithSubregs<3, "r3", [CGB], ["cg"]>, DwarfRegNum<[3]>;59def R4 : MSP430RegWithSubregs<4, "r4", [R4B], ["fp"]>, DwarfRegNum<[4]>;60def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>, DwarfRegNum<[5]>;61def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>, DwarfRegNum<[6]>;62def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>, DwarfRegNum<[7]>;63def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>, DwarfRegNum<[8]>;64def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>, DwarfRegNum<[9]>;65def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>, DwarfRegNum<[10]>;66def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>, DwarfRegNum<[11]>;67def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>, DwarfRegNum<[12]>;68def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>, DwarfRegNum<[13]>;69def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>, DwarfRegNum<[14]>;70def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>, DwarfRegNum<[15]>;71}72 73def GR8 : RegisterClass<"MSP430", [i8], 8,74 // Volatile registers75 (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,76 // Frame pointer, sometimes allocable77 R4B,78 // Volatile, but not allocable79 PCB, SPB, SRB, CGB)>;80 81def GR16 : RegisterClass<"MSP430", [i16], 16,82 // Volatile registers83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,84 // Frame pointer, sometimes allocable85 R4,86 // Volatile, but not allocable87 PC, SP, SR, CG)>;88