2150 lines · cpp
1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file is part of the Mips Disassembler.10//11//===----------------------------------------------------------------------===//12 13#include "MCTargetDesc/MipsMCTargetDesc.h"14#include "TargetInfo/MipsTargetInfo.h"15#include "llvm/ADT/ArrayRef.h"16#include "llvm/MC/MCContext.h"17#include "llvm/MC/MCDecoder.h"18#include "llvm/MC/MCDecoderOps.h"19#include "llvm/MC/MCDisassembler/MCDisassembler.h"20#include "llvm/MC/MCInst.h"21#include "llvm/MC/MCRegisterInfo.h"22#include "llvm/MC/MCSubtargetInfo.h"23#include "llvm/MC/TargetRegistry.h"24#include "llvm/Support/Compiler.h"25#include "llvm/Support/Debug.h"26#include "llvm/Support/ErrorHandling.h"27#include "llvm/Support/MathExtras.h"28#include "llvm/Support/raw_ostream.h"29#include <cassert>30#include <cstdint>31 32using namespace llvm;33using namespace llvm::MCD;34 35#define DEBUG_TYPE "mips-disassembler"36 37using DecodeStatus = MCDisassembler::DecodeStatus;38 39namespace {40 41class MipsDisassembler : public MCDisassembler {42 bool IsMicroMips;43 bool IsBigEndian;44 45public:46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)47 : MCDisassembler(STI, Ctx),48 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),49 IsBigEndian(IsBigEndian) {}50 51 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }52 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }53 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }54 55 bool hasMips32r6() const {56 return STI.hasFeature(Mips::FeatureMips32r6);57 }58 59 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }60 61 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }62 63 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }64 65 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }66 67 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }68 69 bool hasCOP3() const {70 // Only present in MIPS-I and MIPS-II71 return !hasMips32() && !hasMips3();72 }73 74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,75 ArrayRef<uint8_t> Bytes, uint64_t Address,76 raw_ostream &CStream) const override;77};78 79} // end anonymous namespace80 81static MCDisassembler *createMipsDisassembler(const Target &T,82 const MCSubtargetInfo &STI,83 MCContext &Ctx) {84 return new MipsDisassembler(STI, Ctx, true);85}86 87static MCDisassembler *createMipselDisassembler(const Target &T,88 const MCSubtargetInfo &STI,89 MCContext &Ctx) {90 return new MipsDisassembler(STI, Ctx, false);91}92 93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void94LLVMInitializeMipsDisassembler() {95 // Register the disassembler.96 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),97 createMipsDisassembler);98 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),99 createMipselDisassembler);100 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),101 createMipsDisassembler);102 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),103 createMipselDisassembler);104}105 106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();108 return RegInfo->getRegClass(RC).getRegister(RegNo);109}110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,111 uint64_t Address,112 const MCDisassembler *Decoder) {113 // Currently only hardware register 29 is supported.114 if (RegNo != 29)115 return MCDisassembler::Fail;116 Inst.addOperand(MCOperand::createReg(Mips::HWR29));117 return MCDisassembler::Success;118}119 120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,121 uint64_t Address,122 const MCDisassembler *Decoder) {123 if (RegNo > 30 || RegNo % 2)124 return MCDisassembler::Fail;125 126 MCRegister Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2);127 Inst.addOperand(MCOperand::createReg(Reg));128 return MCDisassembler::Success;129}130 131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,132 uint64_t Address,133 const MCDisassembler *Decoder) {134 if (RegNo >= 4)135 return MCDisassembler::Fail;136 137 MCRegister Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);138 Inst.addOperand(MCOperand::createReg(Reg));139 return MCDisassembler::Success;140}141 142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,143 uint64_t Address,144 const MCDisassembler *Decoder) {145 if (RegNo >= 4)146 return MCDisassembler::Fail;147 148 MCRegister Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);149 Inst.addOperand(MCOperand::createReg(Reg));150 return MCDisassembler::Success;151}152 153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,154 uint64_t Address,155 const MCDisassembler *Decoder) {156 if (RegNo >= 4)157 return MCDisassembler::Fail;158 159 MCRegister Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);160 Inst.addOperand(MCOperand::createReg(Reg));161 return MCDisassembler::Success;162}163 164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,165 uint64_t Address,166 const MCDisassembler *Decoder) {167 if (RegNo > 31)168 return MCDisassembler::Fail;169 170 MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);171 Inst.addOperand(MCOperand::createReg(Reg));172 return MCDisassembler::Success;173}174 175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,176 uint64_t Address,177 const MCDisassembler *Decoder) {178 if (RegNo > 31)179 return MCDisassembler::Fail;180 181 MCRegister Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);182 Inst.addOperand(MCOperand::createReg(Reg));183 return MCDisassembler::Success;184}185 186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,187 uint64_t Address,188 const MCDisassembler *Decoder) {189 if (RegNo > 31)190 return MCDisassembler::Fail;191 192 MCRegister Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);193 Inst.addOperand(MCOperand::createReg(Reg));194 return MCDisassembler::Success;195}196 197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,198 uint64_t Address,199 const MCDisassembler *Decoder) {200 if (RegNo > 31)201 return MCDisassembler::Fail;202 203 MCRegister Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);204 Inst.addOperand(MCOperand::createReg(Reg));205 return MCDisassembler::Success;206}207 208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,209 uint64_t Address,210 const MCDisassembler *Decoder) {211 if (RegNo > 7)212 return MCDisassembler::Fail;213 214 MCRegister Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);215 Inst.addOperand(MCOperand::createReg(Reg));216 return MCDisassembler::Success;217}218 219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,220 uint64_t Address,221 const MCDisassembler *Decoder) {222 if (RegNo > 31)223 return MCDisassembler::Fail;224 225 MCRegister Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);226 Inst.addOperand(MCOperand::createReg(Reg));227 return MCDisassembler::Success;228}229 230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,231 uint64_t Address,232 const MCDisassembler *Decoder) {233 if (RegNo > 31)234 return MCDisassembler::Fail;235 236 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);237 Inst.addOperand(MCOperand::createReg(Reg));238 return MCDisassembler::Success;239}240 241static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,242 uint64_t Address,243 const MCDisassembler *Decoder) {244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};246 unsigned RegNum;247 248 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);249 250 // Empty register lists are not allowed.251 if (RegLst == 0)252 return MCDisassembler::Fail;253 254 RegNum = RegLst & 0xf;255 256 // RegLst values 10-15, and 26-31 are reserved.257 if (RegNum > 9)258 return MCDisassembler::Fail;259 260 for (unsigned i = 0; i < RegNum; i++)261 Inst.addOperand(MCOperand::createReg(Regs[i]));262 263 if (RegLst & 0x10)264 Inst.addOperand(MCOperand::createReg(Mips::RA));265 266 return MCDisassembler::Success;267}268 269static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,270 uint64_t Address,271 const MCDisassembler *Decoder) {272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};273 unsigned RegLst;274 switch (Inst.getOpcode()) {275 default:276 RegLst = fieldFromInstruction(Insn, 4, 2);277 break;278 case Mips::LWM16_MMR6:279 case Mips::SWM16_MMR6:280 RegLst = fieldFromInstruction(Insn, 8, 2);281 break;282 }283 unsigned RegNum = RegLst & 0x3;284 285 for (unsigned i = 0; i <= RegNum; i++)286 Inst.addOperand(MCOperand::createReg(Regs[i]));287 288 Inst.addOperand(MCOperand::createReg(Mips::RA));289 290 return MCDisassembler::Success;291}292 293template <typename InsnType>294static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,295 const MCDisassembler *Decoder) {296 using DecodeFN =297 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);298 299 // The size of the n field depends on the element size300 // The register class also depends on this.301 InsnType tmp = fieldFromInstruction(insn, 17, 5);302 unsigned NSize = 0;303 DecodeFN RegDecoder = nullptr;304 if ((tmp & 0x18) == 0x00) { // INSVE_B305 NSize = 4;306 RegDecoder = DecodeMSA128BRegisterClass;307 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H308 NSize = 3;309 RegDecoder = DecodeMSA128HRegisterClass;310 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W311 NSize = 2;312 RegDecoder = DecodeMSA128WRegisterClass;313 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D314 NSize = 1;315 RegDecoder = DecodeMSA128DRegisterClass;316 } else317 llvm_unreachable("Invalid encoding");318 319 assert(NSize != 0 && RegDecoder != nullptr);320 321 // $wd322 tmp = fieldFromInstruction(insn, 6, 5);323 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)324 return MCDisassembler::Fail;325 // $wd_in326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)327 return MCDisassembler::Fail;328 // $n329 tmp = fieldFromInstruction(insn, 16, NSize);330 MI.addOperand(MCOperand::createImm(tmp));331 // $ws332 tmp = fieldFromInstruction(insn, 11, 5);333 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)334 return MCDisassembler::Fail;335 // $n2336 MI.addOperand(MCOperand::createImm(0));337 338 return MCDisassembler::Success;339}340 341template <typename InsnType>342static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,343 uint64_t Address,344 const MCDisassembler *Decoder) {345 InsnType Rs = fieldFromInstruction(insn, 16, 5);346 InsnType Imm = fieldFromInstruction(insn, 0, 16);347 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,348 Rs)));349 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,350 Rs)));351 MI.addOperand(MCOperand::createImm(Imm));352 353 return MCDisassembler::Success;354}355 356template <typename InsnType>357static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,358 const MCDisassembler *Decoder) {359 InsnType Rs = fieldFromInstruction(insn, 21, 5);360 InsnType Imm = fieldFromInstruction(insn, 0, 16);361 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,362 Rs)));363 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,364 Rs)));365 MI.addOperand(MCOperand::createImm(Imm));366 367 return MCDisassembler::Success;368}369 370template <typename InsnType>371static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,372 uint64_t Address,373 const MCDisassembler *Decoder) {374 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled375 // (otherwise we would have matched the ADDI instruction from the earlier376 // ISA's instead).377 //378 // We have:379 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii380 // BOVC if rs >= rt381 // BEQZALC if rs == 0 && rt != 0382 // BEQC if rs < rt && rs != 0383 384 InsnType Rs = fieldFromInstruction(insn, 21, 5);385 InsnType Rt = fieldFromInstruction(insn, 16, 5);386 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;387 bool HasRs = false;388 389 if (Rs >= Rt) {390 MI.setOpcode(Mips::BOVC);391 HasRs = true;392 } else if (Rs != 0 && Rs < Rt) {393 MI.setOpcode(Mips::BEQC);394 HasRs = true;395 } else396 MI.setOpcode(Mips::BEQZALC);397 398 if (HasRs)399 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,400 Rs)));401 402 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,403 Rt)));404 MI.addOperand(MCOperand::createImm(Imm));405 406 return MCDisassembler::Success;407}408 409template <typename InsnType>410static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,411 uint64_t Address,412 const MCDisassembler *Decoder) {413 InsnType Rt = fieldFromInstruction(insn, 21, 5);414 InsnType Rs = fieldFromInstruction(insn, 16, 5);415 int64_t Imm = 0;416 417 if (Rs >= Rt) {418 MI.setOpcode(Mips::BOVC_MMR6);419 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,420 Rt)));421 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,422 Rs)));423 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;424 } else if (Rs != 0 && Rs < Rt) {425 MI.setOpcode(Mips::BEQC_MMR6);426 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,427 Rs)));428 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,429 Rt)));430 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;431 } else {432 MI.setOpcode(Mips::BEQZALC_MMR6);433 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,434 Rt)));435 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;436 }437 438 MI.addOperand(MCOperand::createImm(Imm));439 440 return MCDisassembler::Success;441}442 443template <typename InsnType>444static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,445 uint64_t Address,446 const MCDisassembler *Decoder) {447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled448 // (otherwise we would have matched the ADDI instruction from the earlier449 // ISA's instead).450 //451 // We have:452 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii453 // BNVC if rs >= rt454 // BNEZALC if rs == 0 && rt != 0455 // BNEC if rs < rt && rs != 0456 457 InsnType Rs = fieldFromInstruction(insn, 21, 5);458 InsnType Rt = fieldFromInstruction(insn, 16, 5);459 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;460 bool HasRs = false;461 462 if (Rs >= Rt) {463 MI.setOpcode(Mips::BNVC);464 HasRs = true;465 } else if (Rs != 0 && Rs < Rt) {466 MI.setOpcode(Mips::BNEC);467 HasRs = true;468 } else469 MI.setOpcode(Mips::BNEZALC);470 471 if (HasRs)472 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,473 Rs)));474 475 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,476 Rt)));477 MI.addOperand(MCOperand::createImm(Imm));478 479 return MCDisassembler::Success;480}481 482template <typename InsnType>483static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,484 uint64_t Address,485 const MCDisassembler *Decoder) {486 InsnType Rt = fieldFromInstruction(insn, 21, 5);487 InsnType Rs = fieldFromInstruction(insn, 16, 5);488 int64_t Imm = 0;489 490 if (Rs >= Rt) {491 MI.setOpcode(Mips::BNVC_MMR6);492 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,493 Rt)));494 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,495 Rs)));496 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;497 } else if (Rs != 0 && Rs < Rt) {498 MI.setOpcode(Mips::BNEC_MMR6);499 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,500 Rs)));501 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,502 Rt)));503 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;504 } else {505 MI.setOpcode(Mips::BNEZALC_MMR6);506 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,507 Rt)));508 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;509 }510 511 MI.addOperand(MCOperand::createImm(Imm));512 513 return MCDisassembler::Success;514}515 516template <typename InsnType>517static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,518 uint64_t Address,519 const MCDisassembler *Decoder) {520 // We have:521 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii522 // Invalid if rt == 0523 // BGTZC_MMR6 if rs == 0 && rt != 0524 // BLTZC_MMR6 if rs == rt && rt != 0525 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0526 527 InsnType Rt = fieldFromInstruction(insn, 21, 5);528 InsnType Rs = fieldFromInstruction(insn, 16, 5);529 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;530 bool HasRs = false;531 532 if (Rt == 0)533 return MCDisassembler::Fail;534 else if (Rs == 0)535 MI.setOpcode(Mips::BGTZC_MMR6);536 else if (Rs == Rt)537 MI.setOpcode(Mips::BLTZC_MMR6);538 else {539 MI.setOpcode(Mips::BLTC_MMR6);540 HasRs = true;541 }542 543 if (HasRs)544 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,545 Rs)));546 547 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,548 Rt)));549 550 MI.addOperand(MCOperand::createImm(Imm));551 552 return MCDisassembler::Success;553}554 555template <typename InsnType>556static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,557 uint64_t Address,558 const MCDisassembler *Decoder) {559 // We have:560 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii561 // Invalid if rt == 0562 // BLEZC_MMR6 if rs == 0 && rt != 0563 // BGEZC_MMR6 if rs == rt && rt != 0564 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0565 566 InsnType Rt = fieldFromInstruction(insn, 21, 5);567 InsnType Rs = fieldFromInstruction(insn, 16, 5);568 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;569 bool HasRs = false;570 571 if (Rt == 0)572 return MCDisassembler::Fail;573 else if (Rs == 0)574 MI.setOpcode(Mips::BLEZC_MMR6);575 else if (Rs == Rt)576 MI.setOpcode(Mips::BGEZC_MMR6);577 else {578 HasRs = true;579 MI.setOpcode(Mips::BGEC_MMR6);580 }581 582 if (HasRs)583 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,584 Rs)));585 586 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,587 Rt)));588 589 MI.addOperand(MCOperand::createImm(Imm));590 591 return MCDisassembler::Success;592}593 594template <typename InsnType>595static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,596 uint64_t Address,597 const MCDisassembler *Decoder) {598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled599 // (otherwise we would have matched the BLEZL instruction from the earlier600 // ISA's instead).601 //602 // We have:603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii604 // Invalid if rs == 0605 // BLEZC if rs == 0 && rt != 0606 // BGEZC if rs == rt && rt != 0607 // BGEC if rs != rt && rs != 0 && rt != 0608 609 InsnType Rs = fieldFromInstruction(insn, 21, 5);610 InsnType Rt = fieldFromInstruction(insn, 16, 5);611 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;612 bool HasRs = false;613 614 if (Rt == 0)615 return MCDisassembler::Fail;616 else if (Rs == 0)617 MI.setOpcode(Mips::BLEZC);618 else if (Rs == Rt)619 MI.setOpcode(Mips::BGEZC);620 else {621 HasRs = true;622 MI.setOpcode(Mips::BGEC);623 }624 625 if (HasRs)626 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,627 Rs)));628 629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,630 Rt)));631 632 MI.addOperand(MCOperand::createImm(Imm));633 634 return MCDisassembler::Success;635}636 637template <typename InsnType>638static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,639 uint64_t Address,640 const MCDisassembler *Decoder) {641 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled642 // (otherwise we would have matched the BGTZL instruction from the earlier643 // ISA's instead).644 //645 // We have:646 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii647 // Invalid if rs == 0648 // BGTZC if rs == 0 && rt != 0649 // BLTZC if rs == rt && rt != 0650 // BLTC if rs != rt && rs != 0 && rt != 0651 652 bool HasRs = false;653 654 InsnType Rs = fieldFromInstruction(insn, 21, 5);655 InsnType Rt = fieldFromInstruction(insn, 16, 5);656 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;657 658 if (Rt == 0)659 return MCDisassembler::Fail;660 else if (Rs == 0)661 MI.setOpcode(Mips::BGTZC);662 else if (Rs == Rt)663 MI.setOpcode(Mips::BLTZC);664 else {665 MI.setOpcode(Mips::BLTC);666 HasRs = true;667 }668 669 if (HasRs)670 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,671 Rs)));672 673 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,674 Rt)));675 676 MI.addOperand(MCOperand::createImm(Imm));677 678 return MCDisassembler::Success;679}680 681template <typename InsnType>682static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,683 uint64_t Address,684 const MCDisassembler *Decoder) {685 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled686 // (otherwise we would have matched the BGTZ instruction from the earlier687 // ISA's instead).688 //689 // We have:690 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii691 // BGTZ if rt == 0692 // BGTZALC if rs == 0 && rt != 0693 // BLTZALC if rs != 0 && rs == rt694 // BLTUC if rs != 0 && rs != rt695 696 InsnType Rs = fieldFromInstruction(insn, 21, 5);697 InsnType Rt = fieldFromInstruction(insn, 16, 5);698 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;699 bool HasRs = false;700 bool HasRt = false;701 702 if (Rt == 0) {703 MI.setOpcode(Mips::BGTZ);704 HasRs = true;705 } else if (Rs == 0) {706 MI.setOpcode(Mips::BGTZALC);707 HasRt = true;708 } else if (Rs == Rt) {709 MI.setOpcode(Mips::BLTZALC);710 HasRs = true;711 } else {712 MI.setOpcode(Mips::BLTUC);713 HasRs = true;714 HasRt = true;715 }716 717 if (HasRs)718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,719 Rs)));720 721 if (HasRt)722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,723 Rt)));724 725 MI.addOperand(MCOperand::createImm(Imm));726 727 return MCDisassembler::Success;728}729 730template <typename InsnType>731static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,732 uint64_t Address,733 const MCDisassembler *Decoder) {734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled735 // (otherwise we would have matched the BLEZL instruction from the earlier736 // ISA's instead).737 //738 // We have:739 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii740 // Invalid if rs == 0741 // BLEZALC if rs == 0 && rt != 0742 // BGEZALC if rs == rt && rt != 0743 // BGEUC if rs != rt && rs != 0 && rt != 0744 745 InsnType Rs = fieldFromInstruction(insn, 21, 5);746 InsnType Rt = fieldFromInstruction(insn, 16, 5);747 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;748 bool HasRs = false;749 750 if (Rt == 0)751 return MCDisassembler::Fail;752 else if (Rs == 0)753 MI.setOpcode(Mips::BLEZALC);754 else if (Rs == Rt)755 MI.setOpcode(Mips::BGEZALC);756 else {757 HasRs = true;758 MI.setOpcode(Mips::BGEUC);759 }760 761 if (HasRs)762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,763 Rs)));764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,765 Rt)));766 767 MI.addOperand(MCOperand::createImm(Imm));768 769 return MCDisassembler::Success;770}771 772// Override the generated disassembler to produce DEXT all the time. This is773// for feature / behaviour parity with binutils.774template <typename InsnType>775static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,776 const MCDisassembler *Decoder) {777 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);778 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);779 unsigned Size = 0;780 unsigned Pos = 0;781 782 switch (MI.getOpcode()) {783 case Mips::DEXT:784 Pos = Lsb;785 Size = Msbd + 1;786 break;787 case Mips::DEXTM:788 Pos = Lsb;789 Size = Msbd + 1 + 32;790 break;791 case Mips::DEXTU:792 Pos = Lsb + 32;793 Size = Msbd + 1;794 break;795 default:796 llvm_unreachable("Unknown DEXT instruction!");797 }798 799 MI.setOpcode(Mips::DEXT);800 801 InsnType Rs = fieldFromInstruction(Insn, 21, 5);802 InsnType Rt = fieldFromInstruction(Insn, 16, 5);803 804 MI.addOperand(805 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));806 MI.addOperand(807 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));808 MI.addOperand(MCOperand::createImm(Pos));809 MI.addOperand(MCOperand::createImm(Size));810 811 return MCDisassembler::Success;812}813 814// Override the generated disassembler to produce DINS all the time. This is815// for feature / behaviour parity with binutils.816template <typename InsnType>817static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,818 const MCDisassembler *Decoder) {819 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);820 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);821 unsigned Size = 0;822 unsigned Pos = 0;823 824 switch (MI.getOpcode()) {825 case Mips::DINS:826 Pos = Lsb;827 Size = Msbd + 1 - Pos;828 break;829 case Mips::DINSM:830 Pos = Lsb;831 Size = Msbd + 33 - Pos;832 break;833 case Mips::DINSU:834 Pos = Lsb + 32;835 // mbsd = pos + size - 33836 // mbsd - pos + 33 = size837 Size = Msbd + 33 - Pos;838 break;839 default:840 llvm_unreachable("Unknown DINS instruction!");841 }842 843 InsnType Rs = fieldFromInstruction(Insn, 21, 5);844 InsnType Rt = fieldFromInstruction(Insn, 16, 5);845 846 MI.setOpcode(Mips::DINS);847 MI.addOperand(848 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));849 MI.addOperand(850 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));851 MI.addOperand(MCOperand::createImm(Pos));852 MI.addOperand(MCOperand::createImm(Size));853 854 return MCDisassembler::Success;855}856 857// Auto-generated decoder wouldn't add the third operand for CRC32*.858template <typename InsnType>859static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,860 const MCDisassembler *Decoder) {861 InsnType Rs = fieldFromInstruction(Insn, 21, 5);862 InsnType Rt = fieldFromInstruction(Insn, 16, 5);863 MI.addOperand(864 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));865 MI.addOperand(866 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));867 MI.addOperand(868 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));869 return MCDisassembler::Success;870}871 872static DecodeStatus873DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,874 const MCDisassembler *Decoder) {875 return MCDisassembler::Fail;876}877 878static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,879 uint64_t Address,880 const MCDisassembler *Decoder) {881 if (RegNo > 31)882 return MCDisassembler::Fail;883 884 MCRegister Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);885 Inst.addOperand(MCOperand::createReg(Reg));886 return MCDisassembler::Success;887}888 889static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,890 uint64_t Address,891 const MCDisassembler *Decoder) {892 if (RegNo > 7)893 return MCDisassembler::Fail;894 MCRegister Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);895 Inst.addOperand(MCOperand::createReg(Reg));896 return MCDisassembler::Success;897}898 899static DecodeStatus900DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,901 const MCDisassembler *Decoder) {902 if (RegNo > 7)903 return MCDisassembler::Fail;904 MCRegister Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);905 Inst.addOperand(MCOperand::createReg(Reg));906 return MCDisassembler::Success;907}908 909static DecodeStatus910DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,911 const MCDisassembler *Decoder) {912 if (RegNo > 7)913 return MCDisassembler::Fail;914 MCRegister Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);915 Inst.addOperand(MCOperand::createReg(Reg));916 return MCDisassembler::Success;917}918 919// Tablegen emits references to these unimplemented functions due to usage of920// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are921// unused, which in turn use these register class decoders.922static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,923 uint64_t Address,924 const MCDisassembler *Decoder) {925 llvm_unreachable("this is unused");926}927 928static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,929 uint64_t Address,930 const MCDisassembler *Decoder) {931 llvm_unreachable("this is unused");932}933 934static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,935 uint64_t Address,936 const MCDisassembler *Decoder) {937 llvm_unreachable("this is unused");938}939 940static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,941 uint64_t Address,942 const MCDisassembler *Decoder) {943 llvm_unreachable("this is unused");944}945 946static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,947 uint64_t Address,948 const MCDisassembler *Decoder) {949 if (RegNo > 31)950 return MCDisassembler::Fail;951 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);952 Inst.addOperand(MCOperand::createReg(Reg));953 return MCDisassembler::Success;954}955 956static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,957 uint64_t Address,958 const MCDisassembler *Decoder) {959 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())960 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);961 962 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);963}964 965static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,966 uint64_t Address,967 const MCDisassembler *Decoder) {968 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);969}970 971static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,972 uint64_t Address,973 const MCDisassembler *Decoder) {974 if (RegNo > 31)975 return MCDisassembler::Fail;976 977 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);978 Inst.addOperand(MCOperand::createReg(Reg));979 return MCDisassembler::Success;980}981 982static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,983 uint64_t Address,984 const MCDisassembler *Decoder) {985 if (RegNo > 31)986 return MCDisassembler::Fail;987 988 MCRegister Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);989 Inst.addOperand(MCOperand::createReg(Reg));990 return MCDisassembler::Success;991}992 993static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,994 uint64_t Address,995 const MCDisassembler *Decoder) {996 if (RegNo > 31)997 return MCDisassembler::Fail;998 MCRegister Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);999 Inst.addOperand(MCOperand::createReg(Reg));1000 return MCDisassembler::Success;1001}1002 1003static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,1004 uint64_t Address,1005 const MCDisassembler *Decoder) {1006 if (RegNo > 7)1007 return MCDisassembler::Fail;1008 MCRegister Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);1009 Inst.addOperand(MCOperand::createReg(Reg));1010 return MCDisassembler::Success;1011}1012 1013static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,1014 uint64_t Address,1015 const MCDisassembler *Decoder) {1016 if (RegNo > 31)1017 return MCDisassembler::Fail;1018 1019 MCRegister Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);1020 Inst.addOperand(MCOperand::createReg(Reg));1021 return MCDisassembler::Success;1022}1023 1024static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,1025 const MCDisassembler *Decoder) {1026 int Offset = SignExtend32<16>(Insn & 0xffff);1027 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1028 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1029 1030 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1031 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1032 1033 if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||1034 Inst.getOpcode() == Mips::SCD)1035 Inst.addOperand(MCOperand::createReg(Reg));1036 1037 Inst.addOperand(MCOperand::createReg(Reg));1038 Inst.addOperand(MCOperand::createReg(Base));1039 Inst.addOperand(MCOperand::createImm(Offset));1040 1041 return MCDisassembler::Success;1042}1043 1044static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,1045 const MCDisassembler *Decoder) {1046 int Offset = SignExtend32<9>(Insn >> 7);1047 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1048 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1049 1050 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1051 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1052 1053 if (Inst.getOpcode() == Mips::SCE)1054 Inst.addOperand(MCOperand::createReg(Reg));1055 1056 Inst.addOperand(MCOperand::createReg(Reg));1057 Inst.addOperand(MCOperand::createReg(Base));1058 Inst.addOperand(MCOperand::createImm(Offset));1059 1060 return MCDisassembler::Success;1061}1062 1063static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,1064 uint64_t Address,1065 const MCDisassembler *Decoder) {1066 int Offset = SignExtend32<16>(Insn & 0xffff);1067 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1068 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1069 1070 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1071 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1072 1073 Inst.addOperand(MCOperand::createReg(Reg));1074 Inst.addOperand(MCOperand::createReg(Base));1075 Inst.addOperand(MCOperand::createImm(Offset));1076 1077 return MCDisassembler::Success;1078}1079 1080static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,1081 const MCDisassembler *Decoder) {1082 int Offset = SignExtend32<16>(Insn & 0xffff);1083 unsigned Hint = fieldFromInstruction(Insn, 16, 5);1084 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1085 1086 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1087 1088 Inst.addOperand(MCOperand::createReg(Base));1089 Inst.addOperand(MCOperand::createImm(Offset));1090 Inst.addOperand(MCOperand::createImm(Hint));1091 1092 return MCDisassembler::Success;1093}1094 1095static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,1096 uint64_t Address,1097 const MCDisassembler *Decoder) {1098 int Offset = SignExtend32<12>(Insn & 0xfff);1099 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1100 unsigned Hint = fieldFromInstruction(Insn, 21, 5);1101 1102 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1103 1104 Inst.addOperand(MCOperand::createReg(Base));1105 Inst.addOperand(MCOperand::createImm(Offset));1106 Inst.addOperand(MCOperand::createImm(Hint));1107 1108 return MCDisassembler::Success;1109}1110 1111static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,1112 uint64_t Address,1113 const MCDisassembler *Decoder) {1114 int Offset = SignExtend32<9>(Insn & 0x1ff);1115 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1116 unsigned Hint = fieldFromInstruction(Insn, 21, 5);1117 1118 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1119 1120 Inst.addOperand(MCOperand::createReg(Base));1121 Inst.addOperand(MCOperand::createImm(Offset));1122 Inst.addOperand(MCOperand::createImm(Hint));1123 1124 return MCDisassembler::Success;1125}1126 1127static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,1128 uint64_t Address,1129 const MCDisassembler *Decoder) {1130 int Offset = SignExtend32<9>(Insn >> 7);1131 unsigned Hint = fieldFromInstruction(Insn, 16, 5);1132 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1133 1134 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1135 1136 Inst.addOperand(MCOperand::createReg(Base));1137 Inst.addOperand(MCOperand::createImm(Offset));1138 Inst.addOperand(MCOperand::createImm(Hint));1139 1140 return MCDisassembler::Success;1141}1142 1143static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,1144 const MCDisassembler *Decoder) {1145 int Offset = SignExtend32<16>(Insn & 0xffff);1146 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1147 1148 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1149 1150 Inst.addOperand(MCOperand::createReg(Base));1151 Inst.addOperand(MCOperand::createImm(Offset));1152 1153 return MCDisassembler::Success;1154}1155 1156static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,1157 uint64_t Address,1158 const MCDisassembler *Decoder) {1159 int Offset = SignExtend32<16>(Insn & 0xffff);1160 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1161 1162 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1163 1164 Inst.addOperand(MCOperand::createReg(Base));1165 Inst.addOperand(MCOperand::createImm(Offset));1166 1167 return MCDisassembler::Success;1168}1169 1170static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,1171 const MCDisassembler *Decoder) {1172 int Immediate = SignExtend32<16>(Insn & 0xffff);1173 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1174 1175 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1176 1177 Inst.addOperand(MCOperand::createReg(Base));1178 Inst.addOperand(MCOperand::createImm(Immediate));1179 1180 return MCDisassembler::Success;1181}1182 1183static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,1184 uint64_t Address,1185 const MCDisassembler *Decoder) {1186 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));1187 unsigned RegNo = fieldFromInstruction(Insn, 6, 5);1188 unsigned BaseNo = fieldFromInstruction(Insn, 11, 5);1189 1190 MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);1191 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1192 1193 Inst.addOperand(MCOperand::createReg(Reg));1194 Inst.addOperand(MCOperand::createReg(Base));1195 1196 // The immediate field of an LD/ST instruction is scaled which means it must1197 // be multiplied (when decoding) by the size (in bytes) of the instructions'1198 // data format.1199 // .b - 1 byte1200 // .h - 2 bytes1201 // .w - 4 bytes1202 // .d - 8 bytes1203 switch(Inst.getOpcode())1204 {1205 default:1206 assert(false && "Unexpected instruction");1207 return MCDisassembler::Fail;1208 break;1209 case Mips::LD_B:1210 case Mips::ST_B:1211 Inst.addOperand(MCOperand::createImm(Offset));1212 break;1213 case Mips::LD_H:1214 case Mips::ST_H:1215 Inst.addOperand(MCOperand::createImm(Offset * 2));1216 break;1217 case Mips::LD_W:1218 case Mips::ST_W:1219 Inst.addOperand(MCOperand::createImm(Offset * 4));1220 break;1221 case Mips::LD_D:1222 case Mips::ST_D:1223 Inst.addOperand(MCOperand::createImm(Offset * 8));1224 break;1225 }1226 1227 return MCDisassembler::Success;1228}1229 1230static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,1231 uint64_t Address,1232 const MCDisassembler *Decoder) {1233 unsigned Offset = Insn & 0xf;1234 unsigned Reg = fieldFromInstruction(Insn, 7, 3);1235 unsigned Base = fieldFromInstruction(Insn, 4, 3);1236 1237 switch (Inst.getOpcode()) {1238 case Mips::LBU16_MM:1239 case Mips::LHU16_MM:1240 case Mips::LW16_MM:1241 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)1242 == MCDisassembler::Fail)1243 return MCDisassembler::Fail;1244 break;1245 case Mips::SB16_MM:1246 case Mips::SB16_MMR6:1247 case Mips::SH16_MM:1248 case Mips::SH16_MMR6:1249 case Mips::SW16_MM:1250 case Mips::SW16_MMR6:1251 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)1252 == MCDisassembler::Fail)1253 return MCDisassembler::Fail;1254 break;1255 }1256 1257 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)1258 == MCDisassembler::Fail)1259 return MCDisassembler::Fail;1260 1261 switch (Inst.getOpcode()) {1262 case Mips::LBU16_MM:1263 if (Offset == 0xf)1264 Inst.addOperand(MCOperand::createImm(-1));1265 else1266 Inst.addOperand(MCOperand::createImm(Offset));1267 break;1268 case Mips::SB16_MM:1269 case Mips::SB16_MMR6:1270 Inst.addOperand(MCOperand::createImm(Offset));1271 break;1272 case Mips::LHU16_MM:1273 case Mips::SH16_MM:1274 case Mips::SH16_MMR6:1275 Inst.addOperand(MCOperand::createImm(Offset << 1));1276 break;1277 case Mips::LW16_MM:1278 case Mips::SW16_MM:1279 case Mips::SW16_MMR6:1280 Inst.addOperand(MCOperand::createImm(Offset << 2));1281 break;1282 }1283 1284 return MCDisassembler::Success;1285}1286 1287static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,1288 uint64_t Address,1289 const MCDisassembler *Decoder) {1290 unsigned Offset = Insn & 0x1F;1291 unsigned RegNo = fieldFromInstruction(Insn, 5, 5);1292 1293 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1294 1295 Inst.addOperand(MCOperand::createReg(Reg));1296 Inst.addOperand(MCOperand::createReg(Mips::SP));1297 Inst.addOperand(MCOperand::createImm(Offset << 2));1298 1299 return MCDisassembler::Success;1300}1301 1302static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,1303 uint64_t Address,1304 const MCDisassembler *Decoder) {1305 unsigned Offset = Insn & 0x7F;1306 unsigned RegNo = fieldFromInstruction(Insn, 7, 3);1307 1308 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1309 1310 Inst.addOperand(MCOperand::createReg(Reg));1311 Inst.addOperand(MCOperand::createReg(Mips::GP));1312 Inst.addOperand(MCOperand::createImm(Offset << 2));1313 1314 return MCDisassembler::Success;1315}1316 1317static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,1318 uint64_t Address,1319 const MCDisassembler *Decoder) {1320 int Offset;1321 switch (Inst.getOpcode()) {1322 case Mips::LWM16_MMR6:1323 case Mips::SWM16_MMR6:1324 Offset = fieldFromInstruction(Insn, 4, 4);1325 break;1326 default:1327 Offset = SignExtend32<4>(Insn & 0xf);1328 break;1329 }1330 1331 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)1332 == MCDisassembler::Fail)1333 return MCDisassembler::Fail;1334 1335 Inst.addOperand(MCOperand::createReg(Mips::SP));1336 Inst.addOperand(MCOperand::createImm(Offset << 2));1337 1338 return MCDisassembler::Success;1339}1340 1341static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,1342 uint64_t Address,1343 const MCDisassembler *Decoder) {1344 int Offset = SignExtend32<9>(Insn & 0x1ff);1345 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1346 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1347 1348 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1349 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1350 1351 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)1352 Inst.addOperand(MCOperand::createReg(Reg));1353 1354 Inst.addOperand(MCOperand::createReg(Reg));1355 Inst.addOperand(MCOperand::createReg(Base));1356 Inst.addOperand(MCOperand::createImm(Offset));1357 1358 return MCDisassembler::Success;1359}1360 1361static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,1362 uint64_t Address,1363 const MCDisassembler *Decoder) {1364 int Offset = SignExtend32<12>(Insn & 0x0fff);1365 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1366 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1367 1368 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1369 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1370 1371 switch (Inst.getOpcode()) {1372 case Mips::SWM32_MM:1373 case Mips::LWM32_MM:1374 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)1375 == MCDisassembler::Fail)1376 return MCDisassembler::Fail;1377 Inst.addOperand(MCOperand::createReg(Base));1378 Inst.addOperand(MCOperand::createImm(Offset));1379 break;1380 case Mips::SC_MM:1381 Inst.addOperand(MCOperand::createReg(Reg));1382 [[fallthrough]];1383 default:1384 Inst.addOperand(MCOperand::createReg(Reg));1385 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)1386 Inst.addOperand(MCOperand::createReg(Reg+1));1387 1388 Inst.addOperand(MCOperand::createReg(Base));1389 Inst.addOperand(MCOperand::createImm(Offset));1390 }1391 1392 return MCDisassembler::Success;1393}1394 1395static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,1396 uint64_t Address,1397 const MCDisassembler *Decoder) {1398 int Offset = SignExtend32<16>(Insn & 0xffff);1399 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1400 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1401 1402 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);1403 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1404 1405 Inst.addOperand(MCOperand::createReg(Reg));1406 Inst.addOperand(MCOperand::createReg(Base));1407 Inst.addOperand(MCOperand::createImm(Offset));1408 1409 return MCDisassembler::Success;1410}1411 1412static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,1413 const MCDisassembler *Decoder) {1414 int Offset = SignExtend32<16>(Insn & 0xffff);1415 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1416 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1417 1418 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);1419 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1420 1421 Inst.addOperand(MCOperand::createReg(Reg));1422 Inst.addOperand(MCOperand::createReg(Base));1423 Inst.addOperand(MCOperand::createImm(Offset));1424 1425 return MCDisassembler::Success;1426}1427 1428static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,1429 uint64_t Address,1430 const MCDisassembler *Decoder) {1431 // This function is the same as DecodeFMem but with the Reg and Base fields1432 // swapped according to microMIPS spec.1433 int Offset = SignExtend32<16>(Insn & 0xffff);1434 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1435 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1436 1437 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);1438 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1439 1440 Inst.addOperand(MCOperand::createReg(Reg));1441 Inst.addOperand(MCOperand::createReg(Base));1442 Inst.addOperand(MCOperand::createImm(Offset));1443 1444 return MCDisassembler::Success;1445}1446 1447static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,1448 const MCDisassembler *Decoder) {1449 int Offset = SignExtend32<16>(Insn & 0xffff);1450 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1451 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1452 1453 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);1454 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1455 1456 Inst.addOperand(MCOperand::createReg(Reg));1457 Inst.addOperand(MCOperand::createReg(Base));1458 Inst.addOperand(MCOperand::createImm(Offset));1459 1460 return MCDisassembler::Success;1461}1462 1463static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,1464 const MCDisassembler *Decoder) {1465 int Offset = SignExtend32<16>(Insn & 0xffff);1466 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1467 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1468 1469 MCRegister Reg = getReg(Decoder, Mips::COP3RegClassID, RegNo);1470 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1471 1472 Inst.addOperand(MCOperand::createReg(Reg));1473 Inst.addOperand(MCOperand::createReg(Base));1474 Inst.addOperand(MCOperand::createImm(Offset));1475 1476 return MCDisassembler::Success;1477}1478 1479static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,1480 uint64_t Address,1481 const MCDisassembler *Decoder) {1482 int Offset = SignExtend32<11>(Insn & 0x07ff);1483 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);1484 unsigned BaseNo = fieldFromInstruction(Insn, 11, 5);1485 1486 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);1487 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1488 1489 Inst.addOperand(MCOperand::createReg(Reg));1490 Inst.addOperand(MCOperand::createReg(Base));1491 Inst.addOperand(MCOperand::createImm(Offset));1492 1493 return MCDisassembler::Success;1494}1495 1496static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,1497 uint64_t Address,1498 const MCDisassembler *Decoder) {1499 int Offset = SignExtend32<11>(Insn & 0x07ff);1500 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);1501 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);1502 1503 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);1504 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1505 1506 Inst.addOperand(MCOperand::createReg(Reg));1507 Inst.addOperand(MCOperand::createReg(Base));1508 Inst.addOperand(MCOperand::createImm(Offset));1509 1510 return MCDisassembler::Success;1511}1512 1513static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,1514 uint64_t Address,1515 const MCDisassembler *Decoder) {1516 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);1517 unsigned RtNo = fieldFromInstruction(Insn, 16, 5);1518 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);1519 1520 MCRegister Rt = getReg(Decoder, Mips::GPR32RegClassID, RtNo);1521 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);1522 1523 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){1524 Inst.addOperand(MCOperand::createReg(Rt));1525 }1526 1527 Inst.addOperand(MCOperand::createReg(Rt));1528 Inst.addOperand(MCOperand::createReg(Base));1529 Inst.addOperand(MCOperand::createImm(Offset));1530 1531 return MCDisassembler::Success;1532}1533 1534static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,1535 uint64_t Address,1536 const MCDisassembler *Decoder) {1537 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;1538 Inst.addOperand(MCOperand::createImm(BranchOffset));1539 return MCDisassembler::Success;1540}1541 1542static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,1543 uint64_t Address,1544 const MCDisassembler *Decoder) {1545 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);1546 Inst.addOperand(MCOperand::createImm(BranchOffset));1547 return MCDisassembler::Success;1548}1549 1550static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,1551 uint64_t Address,1552 const MCDisassembler *Decoder) {1553 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;1554 Inst.addOperand(MCOperand::createImm(JumpOffset));1555 return MCDisassembler::Success;1556}1557 1558static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,1559 uint64_t Address,1560 const MCDisassembler *Decoder) {1561 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;1562 1563 Inst.addOperand(MCOperand::createImm(BranchOffset));1564 return MCDisassembler::Success;1565}1566 1567static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,1568 uint64_t Address,1569 const MCDisassembler *Decoder) {1570 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;1571 1572 Inst.addOperand(MCOperand::createImm(BranchOffset));1573 return MCDisassembler::Success;1574}1575 1576static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,1577 uint64_t Address,1578 const MCDisassembler *Decoder) {1579 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;1580 1581 Inst.addOperand(MCOperand::createImm(BranchOffset));1582 return MCDisassembler::Success;1583}1584 1585static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,1586 uint64_t Address,1587 const MCDisassembler *Decoder) {1588 int32_t BranchOffset = SignExtend32<8>(Offset << 1);1589 Inst.addOperand(MCOperand::createImm(BranchOffset));1590 return MCDisassembler::Success;1591}1592 1593static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,1594 uint64_t Address,1595 const MCDisassembler *Decoder) {1596 int32_t BranchOffset = SignExtend32<11>(Offset << 1);1597 Inst.addOperand(MCOperand::createImm(BranchOffset));1598 return MCDisassembler::Success;1599}1600 1601static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,1602 uint64_t Address,1603 const MCDisassembler *Decoder) {1604 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;1605 Inst.addOperand(MCOperand::createImm(BranchOffset));1606 return MCDisassembler::Success;1607}1608 1609static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,1610 uint64_t Address,1611 const MCDisassembler *Decoder) {1612 int32_t BranchOffset = SignExtend32<27>(Offset << 1);1613 1614 Inst.addOperand(MCOperand::createImm(BranchOffset));1615 return MCDisassembler::Success;1616}1617 1618static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,1619 uint64_t Address,1620 const MCDisassembler *Decoder) {1621 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;1622 Inst.addOperand(MCOperand::createImm(JumpOffset));1623 return MCDisassembler::Success;1624}1625 1626static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,1627 uint64_t Address,1628 const MCDisassembler *Decoder) {1629 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;1630 Inst.addOperand(MCOperand::createImm(JumpOffset));1631 return MCDisassembler::Success;1632}1633 1634static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,1635 uint64_t Address,1636 const MCDisassembler *Decoder) {1637 if (Value == 0)1638 Inst.addOperand(MCOperand::createImm(1));1639 else if (Value == 0x7)1640 Inst.addOperand(MCOperand::createImm(-1));1641 else1642 Inst.addOperand(MCOperand::createImm(Value << 2));1643 return MCDisassembler::Success;1644}1645 1646static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,1647 uint64_t Address,1648 const MCDisassembler *Decoder) {1649 if (Value == 0x7F)1650 Inst.addOperand(MCOperand::createImm(-1));1651 else1652 Inst.addOperand(MCOperand::createImm(Value));1653 return MCDisassembler::Success;1654}1655 1656static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,1657 uint64_t Address,1658 const MCDisassembler *Decoder) {1659 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));1660 return MCDisassembler::Success;1661}1662 1663template <unsigned Bits, int Offset, int Scale>1664static DecodeStatus1665DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,1666 const MCDisassembler *Decoder) {1667 Value &= ((1 << Bits) - 1);1668 Value *= Scale;1669 Inst.addOperand(MCOperand::createImm(Value + Offset));1670 return MCDisassembler::Success;1671}1672 1673template <unsigned Bits, int Offset = 0, int ScaleBy = 1>1674static DecodeStatus1675DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,1676 const MCDisassembler *Decoder) {1677 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;1678 Inst.addOperand(MCOperand::createImm(Imm + Offset));1679 return MCDisassembler::Success;1680}1681 1682template <unsigned Bits, int Offset>1683static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,1684 uint64_t Address,1685 const MCDisassembler *Decoder) {1686 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,1687 Decoder);1688}1689 1690static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,1691 const MCDisassembler *Decoder) {1692 // First we need to grab the pos(lsb) from MCInst.1693 // This function only handles the 32 bit variants of ins, as dins1694 // variants are handled differently.1695 int Pos = Inst.getOperand(2).getImm();1696 int Size = (int) Insn - Pos + 1;1697 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));1698 return MCDisassembler::Success;1699}1700 1701static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,1702 uint64_t Address,1703 const MCDisassembler *Decoder) {1704 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));1705 return MCDisassembler::Success;1706}1707 1708static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,1709 uint64_t Address,1710 const MCDisassembler *Decoder) {1711 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));1712 return MCDisassembler::Success;1713}1714 1715static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,1716 const MCDisassembler *Decoder) {1717 int32_t DecodedValue;1718 switch (Insn) {1719 case 0: DecodedValue = 256; break;1720 case 1: DecodedValue = 257; break;1721 case 510: DecodedValue = -258; break;1722 case 511: DecodedValue = -257; break;1723 default: DecodedValue = SignExtend32<9>(Insn); break;1724 }1725 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));1726 return MCDisassembler::Success;1727}1728 1729static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,1730 uint64_t Address,1731 const MCDisassembler *Decoder) {1732 // Insn must be >= 0, since it is unsigned that condition is always true.1733 assert(Insn < 16);1734 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,1735 16, 31, 32, 63, 64, 255, 32768, 65535};1736 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));1737 return MCDisassembler::Success;1738}1739 1740static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,1741 uint64_t Address,1742 const MCDisassembler *Decoder) {1743 switch (RegPair) {1744 default:1745 return MCDisassembler::Fail;1746 case 0:1747 Inst.addOperand(MCOperand::createReg(Mips::A1));1748 Inst.addOperand(MCOperand::createReg(Mips::A2));1749 break;1750 case 1:1751 Inst.addOperand(MCOperand::createReg(Mips::A1));1752 Inst.addOperand(MCOperand::createReg(Mips::A3));1753 break;1754 case 2:1755 Inst.addOperand(MCOperand::createReg(Mips::A2));1756 Inst.addOperand(MCOperand::createReg(Mips::A3));1757 break;1758 case 3:1759 Inst.addOperand(MCOperand::createReg(Mips::A0));1760 Inst.addOperand(MCOperand::createReg(Mips::S5));1761 break;1762 case 4:1763 Inst.addOperand(MCOperand::createReg(Mips::A0));1764 Inst.addOperand(MCOperand::createReg(Mips::S6));1765 break;1766 case 5:1767 Inst.addOperand(MCOperand::createReg(Mips::A0));1768 Inst.addOperand(MCOperand::createReg(Mips::A1));1769 break;1770 case 6:1771 Inst.addOperand(MCOperand::createReg(Mips::A0));1772 Inst.addOperand(MCOperand::createReg(Mips::A2));1773 break;1774 case 7:1775 Inst.addOperand(MCOperand::createReg(Mips::A0));1776 Inst.addOperand(MCOperand::createReg(Mips::A3));1777 break;1778 }1779 1780 return MCDisassembler::Success;1781}1782 1783static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,1784 uint64_t Address,1785 const MCDisassembler *Decoder) {1786 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);1787 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==1788 MCDisassembler::Fail)1789 return MCDisassembler::Fail;1790 1791 unsigned RegRs;1792 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())1793 RegRs = fieldFromInstruction(Insn, 0, 2) |1794 (fieldFromInstruction(Insn, 3, 1) << 2);1795 else1796 RegRs = fieldFromInstruction(Insn, 1, 3);1797 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==1798 MCDisassembler::Fail)1799 return MCDisassembler::Fail;1800 1801 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);1802 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==1803 MCDisassembler::Fail)1804 return MCDisassembler::Fail;1805 1806 return MCDisassembler::Success;1807}1808 1809static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,1810 uint64_t Address,1811 const MCDisassembler *Decoder) {1812 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));1813 return MCDisassembler::Success;1814}1815 1816template <typename InsnType>1817static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,1818 uint64_t Address,1819 const MCDisassembler *Decoder) {1820 // We have:1821 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii1822 // Invalid if rt == 01823 // BGTZALC_MMR6 if rs == 0 && rt != 01824 // BLTZALC_MMR6 if rs != 0 && rs == rt1825 // BLTUC_MMR6 if rs != 0 && rs != rt1826 1827 InsnType Rt = fieldFromInstruction(insn, 21, 5);1828 InsnType Rs = fieldFromInstruction(insn, 16, 5);1829 InsnType Imm = 0;1830 bool HasRs = false;1831 bool HasRt = false;1832 1833 if (Rt == 0)1834 return MCDisassembler::Fail;1835 else if (Rs == 0) {1836 MI.setOpcode(Mips::BGTZALC_MMR6);1837 HasRt = true;1838 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;1839 }1840 else if (Rs == Rt) {1841 MI.setOpcode(Mips::BLTZALC_MMR6);1842 HasRs = true;1843 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;1844 }1845 else {1846 MI.setOpcode(Mips::BLTUC_MMR6);1847 HasRs = true;1848 HasRt = true;1849 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;1850 }1851 1852 if (HasRs)1853 MI.addOperand(1854 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));1855 1856 if (HasRt)1857 MI.addOperand(1858 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));1859 1860 MI.addOperand(MCOperand::createImm(Imm));1861 1862 return MCDisassembler::Success;1863}1864 1865template <typename InsnType>1866static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,1867 uint64_t Address,1868 const MCDisassembler *Decoder) {1869 // We have:1870 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii1871 // Invalid if rt == 01872 // BLEZALC_MMR6 if rs == 0 && rt != 01873 // BGEZALC_MMR6 if rs == rt && rt != 01874 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 01875 1876 InsnType Rt = fieldFromInstruction(insn, 21, 5);1877 InsnType Rs = fieldFromInstruction(insn, 16, 5);1878 InsnType Imm = 0;1879 bool HasRs = false;1880 1881 if (Rt == 0)1882 return MCDisassembler::Fail;1883 else if (Rs == 0) {1884 MI.setOpcode(Mips::BLEZALC_MMR6);1885 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;1886 }1887 else if (Rs == Rt) {1888 MI.setOpcode(Mips::BGEZALC_MMR6);1889 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;1890 }1891 else {1892 HasRs = true;1893 MI.setOpcode(Mips::BGEUC_MMR6);1894 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;1895 }1896 1897 if (HasRs)1898 MI.addOperand(1899 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));1900 MI.addOperand(1901 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));1902 1903 MI.addOperand(MCOperand::createImm(Imm));1904 1905 return MCDisassembler::Success;1906}1907 1908// This instruction does not have a working decoder, and needs to be1909// fixed. This "fixme" function was introduced to keep the backend compiling,1910// while making changes to tablegen code.1911static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,1912 uint64_t Address,1913 const MCDisassembler *Decoder) {1914 return MCDisassembler::Fail;1915}1916 1917#include "MipsGenDisassemblerTables.inc"1918 1919/// Read two bytes from the ArrayRef and return 16 bit halfword sorted1920/// according to the given endianness.1921static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,1922 uint64_t &Size, uint32_t &Insn,1923 bool IsBigEndian) {1924 // We want to read exactly 2 Bytes of data.1925 if (Bytes.size() < 2) {1926 Size = 0;1927 return MCDisassembler::Fail;1928 }1929 1930 if (IsBigEndian) {1931 Insn = (Bytes[0] << 8) | Bytes[1];1932 } else {1933 Insn = (Bytes[1] << 8) | Bytes[0];1934 }1935 1936 return MCDisassembler::Success;1937}1938 1939/// Read four bytes from the ArrayRef and return 32 bit word sorted1940/// according to the given endianness.1941static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,1942 uint64_t &Size, uint32_t &Insn,1943 bool IsBigEndian, bool IsMicroMips) {1944 // We want to read exactly 4 Bytes of data.1945 if (Bytes.size() < 4) {1946 Size = 0;1947 return MCDisassembler::Fail;1948 }1949 1950 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)1951 // always precede the low 16 bits in the instruction stream (that is, they1952 // are placed at lower addresses in the instruction stream).1953 //1954 // microMIPS byte ordering:1955 // Big-endian: 0 | 1 | 2 | 31956 // Little-endian: 1 | 0 | 3 | 21957 1958 if (IsBigEndian) {1959 // Encoded as a big-endian 32-bit word in the stream.1960 Insn =1961 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);1962 } else {1963 if (IsMicroMips) {1964 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |1965 (Bytes[1] << 24);1966 } else {1967 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |1968 (Bytes[3] << 24);1969 }1970 }1971 1972 return MCDisassembler::Success;1973}1974 1975DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,1976 ArrayRef<uint8_t> Bytes,1977 uint64_t Address,1978 raw_ostream &CStream) const {1979 uint32_t Insn;1980 DecodeStatus Result;1981 Size = 0;1982 1983 if (IsMicroMips) {1984 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);1985 if (Result == MCDisassembler::Fail)1986 return MCDisassembler::Fail;1987 1988 if (hasMips32r6()) {1989 LLVM_DEBUG(1990 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");1991 // Calling the auto-generated decoder function for microMIPS32R61992 // 16-bit instructions.1993 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,1994 Address, this, STI);1995 if (Result != MCDisassembler::Fail) {1996 Size = 2;1997 return Result;1998 }1999 }2000 2001 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");2002 // Calling the auto-generated decoder function for microMIPS 16-bit2003 // instructions.2004 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,2005 this, STI);2006 if (Result != MCDisassembler::Fail) {2007 Size = 2;2008 return Result;2009 }2010 2011 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);2012 if (Result == MCDisassembler::Fail)2013 return MCDisassembler::Fail;2014 2015 if (hasMips32r6()) {2016 LLVM_DEBUG(2017 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");2018 // Calling the auto-generated decoder function.2019 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,2020 Address, this, STI);2021 if (Result != MCDisassembler::Fail) {2022 Size = 4;2023 return Result;2024 }2025 }2026 2027 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");2028 // Calling the auto-generated decoder function.2029 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,2030 this, STI);2031 if (Result != MCDisassembler::Fail) {2032 Size = 4;2033 return Result;2034 }2035 2036 if (isFP64()) {2037 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");2038 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,2039 Address, this, STI);2040 if (Result != MCDisassembler::Fail) {2041 Size = 4;2042 return Result;2043 }2044 }2045 2046 // This is an invalid instruction. Claim that the Size is 2 bytes. Since2047 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes2048 // could form a valid instruction. The two bytes we rejected as an2049 // instruction could have actually beeen an inline constant pool that is2050 // unconditionally branched over.2051 Size = 2;2052 return MCDisassembler::Fail;2053 }2054 2055 // Attempt to read the instruction so that we can attempt to decode it. If2056 // the buffer is not 4 bytes long, let the higher level logic figure out2057 // what to do with a size of zero and MCDisassembler::Fail.2058 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);2059 if (Result == MCDisassembler::Fail)2060 return MCDisassembler::Fail;2061 2062 // The only instruction size for standard encoded MIPS.2063 Size = 4;2064 2065 if (hasCOP3()) {2066 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");2067 Result =2068 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);2069 if (Result != MCDisassembler::Fail)2070 return Result;2071 }2072 2073 if (hasMips32r6() && isGP64()) {2074 LLVM_DEBUG(2075 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");2076 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,2077 Address, this, STI);2078 if (Result != MCDisassembler::Fail)2079 return Result;2080 }2081 2082 if (hasMips32r6() && isPTR64()) {2083 LLVM_DEBUG(2084 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");2085 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,2086 Address, this, STI);2087 if (Result != MCDisassembler::Fail)2088 return Result;2089 }2090 2091 if (hasMips32r6()) {2092 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");2093 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,2094 Address, this, STI);2095 if (Result != MCDisassembler::Fail)2096 return Result;2097 }2098 2099 if (hasMips2() && isPTR64()) {2100 LLVM_DEBUG(2101 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");2102 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,2103 Address, this, STI);2104 if (Result != MCDisassembler::Fail)2105 return Result;2106 }2107 2108 if (hasCnMips()) {2109 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");2110 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this,2111 STI);2112 if (Result != MCDisassembler::Fail)2113 return Result;2114 }2115 2116 if (hasCnMipsP()) {2117 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");2118 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address,2119 this, STI);2120 if (Result != MCDisassembler::Fail)2121 return Result;2122 }2123 2124 if (isGP64()) {2125 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");2126 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this,2127 STI);2128 if (Result != MCDisassembler::Fail)2129 return Result;2130 }2131 2132 if (isFP64()) {2133 LLVM_DEBUG(2134 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");2135 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address,2136 this, STI);2137 if (Result != MCDisassembler::Fail)2138 return Result;2139 }2140 2141 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");2142 // Calling the auto-generated decoder function.2143 Result =2144 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);2145 if (Result != MCDisassembler::Fail)2146 return Result;2147 2148 return MCDisassembler::Fail;2149}2150