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1//===- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code --*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the MipsMCCodeEmitter class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H15 16#include "llvm/MC/MCCodeEmitter.h"17#include <cstdint>18 19namespace llvm {20 21class MCContext;22class MCExpr;23class MCFixup;24class MCInst;25class MCInstrInfo;26class MCOperand;27class MCSubtargetInfo;28class raw_ostream;29 30class MipsMCCodeEmitter : public MCCodeEmitter {31 const MCInstrInfo &MCII;32 MCContext &Ctx;33 bool IsLittleEndian;34 35 bool isMicroMips(const MCSubtargetInfo &STI) const;36 bool isMips32r6(const MCSubtargetInfo &STI) const;37 38public:39 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)40 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}41 MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete;42 MipsMCCodeEmitter &operator=(const MipsMCCodeEmitter &) = delete;43 ~MipsMCCodeEmitter() override = default;44 45 void EmitByte(unsigned char C, raw_ostream &OS) const;46 47 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,48 SmallVectorImpl<MCFixup> &Fixups,49 const MCSubtargetInfo &STI) const override;50 51 // getBinaryCodeForInstr - TableGen'erated function for getting the52 // binary encoding for an instruction.53 uint64_t getBinaryCodeForInstr(const MCInst &MI,54 SmallVectorImpl<MCFixup> &Fixups,55 const MCSubtargetInfo &STI) const;56 57 // getJumpTargetOpValue - Return binary encoding of the jump58 // target operand. If the machine operand requires relocation,59 // record the relocation and return zero.60 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,61 SmallVectorImpl<MCFixup> &Fixups,62 const MCSubtargetInfo &STI) const;63 64 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump65 // target operand. If the machine operand requires relocation,66 // record the relocation and return zero.67 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,68 SmallVectorImpl<MCFixup> &Fixups,69 const MCSubtargetInfo &STI) const;70 71 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump72 // target operand.73 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,74 SmallVectorImpl<MCFixup> &Fixups,75 const MCSubtargetInfo &STI) const;76 77 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,78 SmallVectorImpl<MCFixup> &Fixups,79 const MCSubtargetInfo &STI) const;80 81 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,82 SmallVectorImpl<MCFixup> &Fixups,83 const MCSubtargetInfo &STI) const;84 85 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp86 // instruction immediate operand.87 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,88 SmallVectorImpl<MCFixup> &Fixups,89 const MCSubtargetInfo &STI) const;90 91 // getBranchTargetOpValue - Return binary encoding of the branch92 // target operand. If the machine operand requires relocation,93 // record the relocation and return zero.94 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,95 SmallVectorImpl<MCFixup> &Fixups,96 const MCSubtargetInfo &STI) const;97 98 // getBranchTargetOpValue1SImm16 - Return binary encoding of the branch99 // target operand. If the machine operand requires relocation,100 // record the relocation and return zero.101 unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,102 SmallVectorImpl<MCFixup> &Fixups,103 const MCSubtargetInfo &STI) const;104 105 // getBranchTargetOpValueMMR6 - Return binary encoding of the branch106 // target operand. If the machine operand requires relocation,107 // record the relocation and return zero.108 unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,109 SmallVectorImpl<MCFixup> &Fixups,110 const MCSubtargetInfo &STI) const;111 112 // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch113 // target operand. If the machine operand requires relocation,114 // record the relocation and return zero.115 unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,116 SmallVectorImpl<MCFixup> &Fixups,117 const MCSubtargetInfo &STI) const;118 119 // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch120 // target operand. If the machine operand requires relocation,121 // record the relocation and return zero.122 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,123 SmallVectorImpl<MCFixup> &Fixups,124 const MCSubtargetInfo &STI) const;125 126 // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS127 // 10-bit branch target operand. If the machine operand requires relocation,128 // record the relocation and return zero.129 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,130 SmallVectorImpl<MCFixup> &Fixups,131 const MCSubtargetInfo &STI) const;132 133 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch134 // target operand. If the machine operand requires relocation,135 // record the relocation and return zero.136 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,137 SmallVectorImpl<MCFixup> &Fixups,138 const MCSubtargetInfo &STI) const;139 140 // getBranchTarget21OpValue - Return binary encoding of the branch141 // offset operand. If the machine operand requires relocation,142 // record the relocation and return zero.143 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,144 SmallVectorImpl<MCFixup> &Fixups,145 const MCSubtargetInfo &STI) const;146 147 // getBranchTarget21OpValueMM - Return binary encoding of the branch148 // offset operand for microMIPS. If the machine operand requires149 // relocation,record the relocation and return zero.150 unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,151 SmallVectorImpl<MCFixup> &Fixups,152 const MCSubtargetInfo &STI) const;153 154 // getBranchTarget26OpValue - Return binary encoding of the branch155 // offset operand. If the machine operand requires relocation,156 // record the relocation and return zero.157 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,158 SmallVectorImpl<MCFixup> &Fixups,159 const MCSubtargetInfo &STI) const;160 161 // getBranchTarget26OpValueMM - Return binary encoding of the branch162 // offset operand. If the machine operand requires relocation,163 // record the relocation and return zero.164 unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo,165 SmallVectorImpl<MCFixup> &Fixups,166 const MCSubtargetInfo &STI) const;167 168 // getJumpOffset16OpValue - Return binary encoding of the jump169 // offset operand. If the machine operand requires relocation,170 // record the relocation and return zero.171 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,172 SmallVectorImpl<MCFixup> &Fixups,173 const MCSubtargetInfo &STI) const;174 175 // getMachineOpValue - Return binary encoding of operand. If the machin176 // operand requires relocation, record the relocation and return zero.177 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,178 SmallVectorImpl<MCFixup> &Fixups,179 const MCSubtargetInfo &STI) const;180 unsigned getImmOpValue(const MCInst &MI, const MCOperand &MO,181 SmallVectorImpl<MCFixup> &Fixups,182 const MCSubtargetInfo &STI) const;183 184 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,185 SmallVectorImpl<MCFixup> &Fixups,186 const MCSubtargetInfo &STI) const;187 188 template <unsigned ShiftAmount = 0>189 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,190 SmallVectorImpl<MCFixup> &Fixups,191 const MCSubtargetInfo &STI) const;192 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,193 SmallVectorImpl<MCFixup> &Fixups,194 const MCSubtargetInfo &STI) const;195 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,196 SmallVectorImpl<MCFixup> &Fixups,197 const MCSubtargetInfo &STI) const;198 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,199 SmallVectorImpl<MCFixup> &Fixups,200 const MCSubtargetInfo &STI) const;201 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,202 SmallVectorImpl<MCFixup> &Fixups,203 const MCSubtargetInfo &STI) const;204 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,205 SmallVectorImpl<MCFixup> &Fixups,206 const MCSubtargetInfo &STI) const;207 unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,208 SmallVectorImpl<MCFixup> &Fixups,209 const MCSubtargetInfo &STI) const;210 unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,211 SmallVectorImpl<MCFixup> &Fixups,212 const MCSubtargetInfo &STI) const;213 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,214 SmallVectorImpl<MCFixup> &Fixups,215 const MCSubtargetInfo &STI) const;216 unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,217 SmallVectorImpl<MCFixup> &Fixups,218 const MCSubtargetInfo &STI) const;219 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,220 SmallVectorImpl<MCFixup> &Fixups,221 const MCSubtargetInfo &STI) const;222 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,223 SmallVectorImpl<MCFixup> &Fixups,224 const MCSubtargetInfo &STI) const;225 226 /// Subtract Offset then encode as a N-bit unsigned integer.227 template <unsigned Bits, int Offset>228 unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,229 SmallVectorImpl<MCFixup> &Fixups,230 const MCSubtargetInfo &STI) const;231 232 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,233 SmallVectorImpl<MCFixup> &Fixups,234 const MCSubtargetInfo &STI) const;235 236 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,237 SmallVectorImpl<MCFixup> &Fixups,238 const MCSubtargetInfo &STI) const;239 240 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,241 SmallVectorImpl<MCFixup> &Fixups,242 const MCSubtargetInfo &STI) const;243 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,244 SmallVectorImpl<MCFixup> &Fixups,245 const MCSubtargetInfo &STI) const;246 247 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,248 SmallVectorImpl<MCFixup> &Fixups,249 const MCSubtargetInfo &STI) const;250 unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,251 SmallVectorImpl<MCFixup> &Fixups,252 const MCSubtargetInfo &STI) const;253 254 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,255 SmallVectorImpl<MCFixup> &Fixups,256 const MCSubtargetInfo &STI) const;257 258 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,259 const MCSubtargetInfo &STI) const;260 261 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,262 SmallVectorImpl<MCFixup> &Fixups,263 const MCSubtargetInfo &STI) const;264 265 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,266 SmallVectorImpl<MCFixup> &Fixups,267 const MCSubtargetInfo &STI) const;268 269private:270 void LowerCompactBranch(MCInst& Inst) const;271};272 273} // end namespace llvm274 275#endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H276