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1//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes microMIPS32r6 instruction formats.10//11//===----------------------------------------------------------------------===//12 13class MMR6Arch<string opstr> {14 string Arch = "micromipsr6";15 string BaseOpcode = opstr;16 string DecoderNamespace = "MicroMipsR6";17}18 19//===----------------------------------------------------------------------===//20//21// Disambiguators22//23//===----------------------------------------------------------------------===//24//25// Some encodings are ambiguous except by comparing field values.26 27class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {28 string DecoderNamespace = "MicroMipsR6_Ambiguous";29}30 31//===----------------------------------------------------------------------===//32//33// Encoding Formats34//35//===----------------------------------------------------------------------===//36 37class BC16_FM_MM16R6 {38 bits<10> offset;39 40 bits<16> Inst;41 42 let Inst{15-10} = 0x33;43 let Inst{9-0} = offset;44}45 46class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {47 bits<3> rs;48 bits<7> offset;49 50 bits<16> Inst;51 52 let Inst{15-10} = op;53 let Inst{9-7} = rs;54 let Inst{6-0} = offset;55}56 57class POOL16C_JALRC_FM_MM16R6<bits<5> op> {58 bits<5> rs;59 60 bits<16> Inst;61 62 let Inst{15-10} = 0x11;63 let Inst{9-5} = rs;64 let Inst{4-0} = op;65}66 67class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {68 bits<5> rt;69 bits<5> rs;70 bits<16> offset;71 72 bits<32> Inst;73 74 let Inst{31-26} = 0b011101;75 let Inst{25-21} = rt;76 let Inst{20-16} = rs;77 let Inst{15-0} = offset;78}79 80class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {81 bits<5> rt;82 bits<5> rs;83 bits<16> offset;84 85 bits<32> Inst;86 87 let Inst{31-26} = 0b011111;88 let Inst{25-21} = rt;89 let Inst{20-16} = rs;90 let Inst{15-0} = offset;91}92 93class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {94 bits<5> imm;95 96 bits<16> Inst;97 98 let Inst{15-10} = 0x11;99 let Inst{9-5} = imm;100 let Inst{4-0} = op;101}102 103class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {104 bits<2> rt;105 bits<4> addr;106 107 bits<16> Inst;108 109 let Inst{15-10} = 0x11;110 let Inst{9-8} = rt;111 let Inst{7-4} = addr;112 let Inst{3-0} = funct;113}114 115class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {116 bits<5> rd;117 bits<5> rt;118 119 bits<32> Inst;120 121 let Inst{31-26} = 0b000000;122 let Inst{25-21} = rt;123 let Inst{20-16} = rd;124 let Inst{15-12} = 0b0000;125 let Inst{11-6} = funct;126 let Inst{5-0} = 0b111100;127}128 129class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {130 bits<21> addr;131 bits<5> hint;132 133 bits<32> Inst;134 135 let Inst{31-26} = opgroup;136 let Inst{25-21} = hint;137 let Inst{20-16} = addr{20-16};138 let Inst{15-12} = funct;139 let Inst{11-0} = addr{11-0};140}141 142class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {143 bits<5> rd;144 bits<5> rt;145 bits<5> rs;146 147 bits<32> Inst;148 149 let Inst{31-26} = 0;150 let Inst{25-21} = rt;151 let Inst{20-16} = rs;152 let Inst{15-11} = rd;153 let Inst{10} = 0;154 let Inst{9-0} = funct;155}156 157class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {158 bits<5> rt;159 bits<5> rs;160 bits<16> imm16;161 162 bits<32> Inst;163 164 let Inst{31-26} = op;165 let Inst{25-21} = rt;166 let Inst{20-16} = rs;167 let Inst{15-0} = imm16;168}169 170class LB32_FM_MMR6 : MipsR6Inst {171 bits<21> addr;172 bits<5> rt;173 bits<5> base = addr{20-16};174 bits<16> offset = addr{15-0};175 176 bits<32> Inst;177 178 let Inst{31-26} = 0b000111;179 let Inst{25-21} = rt;180 let Inst{20-16} = base;181 let Inst{15-0} = offset;182}183 184class LBU32_FM_MMR6 : MipsR6Inst {185 bits<21> addr;186 bits<5> rt;187 bits<5> base = addr{20-16};188 bits<16> offset = addr{15-0};189 190 bits<32> Inst;191 192 let Inst{31-26} = 0b000101;193 let Inst{25-21} = rt;194 let Inst{20-16} = base;195 let Inst{15-0} = offset;196}197 198class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {199 bits<5> rt;200 bits<19> imm;201 202 bits<32> Inst;203 204 let Inst{31-26} = 0b011110;205 let Inst{25-21} = rt;206 let Inst{20-19} = funct;207 let Inst{18-0} = imm;208}209 210class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {211 bits<5> rt;212 bits<16> imm;213 214 bits<32> Inst;215 216 let Inst{31-26} = 0b011110;217 let Inst{25-21} = rt;218 let Inst{20-16} = funct;219 let Inst{15-0} = imm;220}221 222class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {223 bits<5> rd;224 bits<5> rs;225 bits<5> rt;226 227 bits<32> Inst;228 229 let Inst{31-26} = 0b000000;230 let Inst{25-21} = rt;231 let Inst{20-16} = rs;232 let Inst{15-11} = rd;233 let Inst{10} = 0;234 let Inst{9-0} = funct;235}236 237class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op>238 : MMR6Arch<instr_asm> {239 bits<32> Inst;240 241 let Inst{31-26} = 0;242 let Inst{25-21} = 0;243 let Inst{20-16} = 0;244 let Inst{15-11} = op;245 let Inst{10-6} = 0;246 let Inst{5-0} = 0;247}248 249class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {250 bits<5> rt;251 bits<5> rd;252 bits<32> Inst;253 254 let Inst{31-26} = 0;255 let Inst{25-21} = rt;256 let Inst{20-16} = rd;257 let Inst{15-6} = funct;258 let Inst{5-0} = 0b111100;259}260 261class POOL32A_RDHWR_FM_MMR6 {262 bits<5> rt;263 bits<5> rs;264 bits<3> sel;265 bits<32> Inst;266 267 let Inst{31-26} = 0;268 let Inst{25-21} = rt;269 let Inst{20-16} = rs;270 let Inst{15-14} = 0;271 let Inst{13-11} = sel;272 let Inst{10} = 0;273 let Inst{9-0} = 0b0111000000;274}275 276class POOL32A_SYNC_FM_MMR6 {277 bits<5> stype;278 279 bits<32> Inst;280 281 let Inst{31-26} = 0;282 let Inst{25-21} = 0;283 let Inst{20-16} = stype;284 let Inst{15-6} = 0b0110101101;285 let Inst{5-0} = 0b111100;286}287 288class POOL32I_SYNCI_FM_MMR6 {289 bits<21> addr;290 bits<5> base = addr{20-16};291 bits<16> immediate = addr{15-0};292 293 bits<32> Inst;294 295 let Inst{31-26} = 0b010000;296 let Inst{25-21} = 0b01100;297 let Inst{20-16} = base;298 let Inst{15-0} = immediate;299}300 301class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {302 bits<5> rs;303 bits<5> rt;304 305 bits<32> Inst;306 307 let Inst{31-26} = 0b000000;308 let Inst{25-21} = rt;309 let Inst{20-16} = rs;310 let Inst{15-6} = funct;311 let Inst{5-0} = 0b111100;312}313 314class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {315 bits<5> rs;316 bits<5> rt;317 318 bits<32> Inst;319 320 let Inst{31-26} = 0b000000;321 let Inst{25-21} = rs;322 let Inst{20-16} = 0b00000;323 let Inst{15-11} = rt;324 let Inst{10-6} = 0b00001;325 let Inst{5-0} = funct;326}327 328class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {329 bits<5> rd;330 bits<5> rs;331 bits<5> rt;332 bits<2> bp;333 334 bits<32> Inst;335 336 let Inst{31-26} = 0b000000;337 let Inst{25-21} = rs;338 let Inst{20-16} = rt;339 let Inst{15-11} = rd;340 let Inst{10-9} = bp;341 let Inst{8-6} = 0b000;342 let Inst{5-0} = funct;343}344 345class AUI_FM_MMR6 : MipsR6Inst {346 bits<5> rs;347 bits<5> rt;348 bits<16> imm;349 350 bits<32> Inst;351 352 let Inst{31-26} = 0b000100;353 let Inst{25-21} = rt;354 let Inst{20-16} = rs;355 let Inst{15-0} = imm;356}357 358class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {359 bits<5> rd;360 bits<5> rs;361 bits<5> rt;362 bits<2> imm2;363 364 bits<32> Inst;365 366 let Inst{31-26} = 0b000000;367 let Inst{25-21} = rt;368 let Inst{20-16} = rs;369 let Inst{15-11} = rd;370 let Inst{10-9} = imm2;371 let Inst{8-6} = 0b000;372 let Inst{5-0} = funct;373}374 375class SB32_SH32_STORE_FM_MMR6<bits<6> op> {376 bits<5> rt;377 bits<21> addr;378 bits<5> base = addr{20-16};379 bits<16> offset = addr{15-0};380 381 bits<32> Inst;382 383 let Inst{31-26} = op;384 let Inst{25-21} = rt;385 let Inst{20-16} = base;386 let Inst{15-0} = offset;387}388 389class LOAD_WORD_FM_MMR6 {390 bits<5> rt;391 bits<21> addr;392 bits<5> base = addr{20-16};393 bits<16> offset = addr{15-0};394 395 bits<32> Inst;396 397 let Inst{31-26} = 0b111111;398 let Inst{25-21} = rt;399 let Inst{20-16} = base;400 let Inst{15-0} = offset;401}402 403class LOAD_UPPER_IMM_FM_MMR6 {404 bits<5> rt;405 bits<16> imm16;406 407 bits<32> Inst;408 409 let Inst{31-26} = 0b000100;410 let Inst{25-21} = rt;411 let Inst{20-16} = 0;412 let Inst{15-0} = imm16;413}414 415class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>416 : MMR6Arch<instr_asm>, MipsR6Inst {417 bits<5> rt;418 bits<16> offset;419 420 bits<32> Inst;421 422 let Inst{31-26} = funct;423 let Inst{25-21} = rt;424 let Inst{20-16} = 0b00000;425 let Inst{15-0} = offset;426}427 428class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>429 : MMR6Arch<instr_asm>, MipsR6Inst {430 bits<5> rt;431 bits<16> offset;432 433 bits<32> Inst;434 435 let Inst{31-26} = funct;436 let Inst{25-21} = rt;437 let Inst{20-16} = rt;438 let Inst{15-0} = offset;439}440 441class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>442 : MipsR6Inst, MMR6Arch<instr_asm> {443 bits<5> rt;444 bits<5> rs;445 446 bits<32> Inst;447 448 let Inst{31-26} = 0;449 let Inst{25-21} = rt;450 let Inst{20-16} = rs;451 let Inst{15-6} = funct;452 let Inst{5-0} = 0b111100;453}454 455class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>456 : MMR6Arch<instr_asm>, MipsR6Inst {457 bits<5> rt;458 bits<5> rs;459 bits<5> size;460 bits<5> pos;461 462 bits<32> Inst;463 464 let Inst{31-26} = 0;465 let Inst{25-21} = rt;466 let Inst{20-16} = rs;467 let Inst{15-11} = size;468 let Inst{10-6} = pos;469 let Inst{5-0} = funct;470}471 472class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>473 : MMR6Arch<instr_asm> {474 bits<32> Inst;475 476 let Inst{31-26} = 0x00;477 let Inst{25-16} = 0x00;478 let Inst{15-6} = funct;479 let Inst{5-0} = 0x3c;480}481 482class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {483 bits<32> Inst;484 485 let Inst{31-26} = 0x00;486 let Inst{25-17} = 0x00;487 let Inst{16-16} = 0x01;488 let Inst{15-6} = 0x3cd;489 let Inst{5-0} = 0x3c;490}491 492class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {493 bits<10> code_1;494 bits<10> code_2;495 bits<32> Inst;496 let Inst{31-26} = 0x0;497 let Inst{25-16} = code_1;498 let Inst{15-6} = code_2;499 let Inst{5-0} = 0x07;500}501 502class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {503 bits<32> Inst;504 505 let Inst{31-26} = 0x0;506 let Inst{25-21} = 0x0;507 let Inst{20-16} = 0x0;508 let Inst{15-11} = op;509 let Inst{10-6} = 0x0;510 let Inst{5-0} = 0x0;511}512 513class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>514 : MMR6Arch<instr_asm> {515 bits<32> Inst;516 bits<5> rt; // Actually rs but we're sharing code with the standard encodings517 // which call it rt518 519 let Inst{31-26} = 0x00;520 let Inst{25-21} = 0x00;521 let Inst{20-16} = rt;522 let Inst{15-6} = funct;523 let Inst{5-0} = 0x3c;524}525 526class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate>527 : MMR6Arch<instr_asm> {528 bits<5> rd;529 bits<5> rt;530 bits<5> shamt;531 532 bits<32> Inst;533 534 let Inst{31-26} = 0;535 let Inst{25-21} = rd;536 let Inst{20-16} = rt;537 let Inst{15-11} = shamt;538 let Inst{10} = rotate;539 let Inst{9-0} = funct;540}541 542class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {543 bits<5> rt;544 bits<21> addr;545 546 bits<32> Inst;547 548 let Inst{31-26} = op;549 let Inst{25-21} = rt;550 let Inst{20-16} = addr{20-16};551 let Inst{15-0} = addr{15-0};552}553 554class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>555 : MMR6Arch<instr_asm>, MipsR6Inst {556 bits<5> ft;557 bits<5> fs;558 bits<5> fd;559 560 bits<32> Inst;561 562 let Inst{31-26} = 0b010101;563 let Inst{25-21} = ft;564 let Inst{20-16} = fs;565 let Inst{15-11} = fd;566 let Inst{10} = 0;567 let Inst{9-8} = fmt;568 let Inst{7-0} = funct;569}570 571class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>572 : MMR6Arch<instr_asm>, MipsR6Inst {573 bits<5> ft;574 bits<5> fs;575 bits<5> fd;576 577 bits<32> Inst;578 579 let Inst{31-26} = 0b010101;580 let Inst{25-21} = ft;581 let Inst{20-16} = fs;582 let Inst{15-11} = fd;583 let Inst{10-9} = fmt;584 let Inst{8-0} = funct;585}586 587class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>588 : MMR6Arch<instr_asm>, MipsR6Inst {589 bits<5> ft;590 bits<5> fs;591 592 bits<32> Inst;593 594 let Inst{31-26} = 0b010101;595 let Inst{25-21} = ft;596 let Inst{20-16} = fs;597 let Inst{15} = 0;598 let Inst{14-13} = fmt;599 let Inst{12-6} = funct;600 let Inst{5-0} = 0b111011;601}602 603class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>604 : MMR6Arch<instr_asm>, MipsR6Inst {605 bits<5> ft;606 bits<5> fs;607 bits<5> fd;608 609 bits<32> Inst;610 611 let Inst{31-26} = 0b010101;612 let Inst{25-21} = ft;613 let Inst{20-16} = fs;614 let Inst{15-11} = fd;615 let Inst{10-9} = fmt;616 let Inst{8-0} = funct;617}618 619class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>620 : MMR6Arch<instr_asm>, MipsR6Inst {621 bits<5> ft;622 bits<5> fs;623 bits<5> fd;624 625 bits<32> Inst;626 627 let Inst{31-26} = 0b010101;628 let Inst{25-21} = ft;629 let Inst{20-16} = fs;630 let Inst{15-11} = fd;631 let Inst{10-6} = Cond.Value;632 let Inst{5-0} = format;633}634 635class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>636 : MMR6Arch<instr_asm>, MipsR6Inst {637 bits<5> ft;638 bits<5> fs;639 640 bits<32> Inst;641 let Inst{31-26} = 0b010101;642 let Inst{25-21} = ft;643 let Inst{20-16} = fs;644 let Inst{15} = 0;645 let Inst{14} = fmt;646 let Inst{13-6} = funct;647 let Inst{5-0} = 0b111011;648}649 650class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>651 : MMR6Arch<instr_asm>, MipsR6Inst {652 bits<5> ft;653 bits<5> fs;654 655 bits<32> Inst;656 let Inst{31-26} = 0b010101;657 let Inst{25-21} = ft;658 let Inst{20-16} = fs;659 let Inst{15} = 0;660 let Inst{14-13} = fmt;661 let Inst{12-6} = funct;662 let Inst{5-0} = 0b111011;663}664 665class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>666 : MMR6Arch<instr_asm>, MipsR6Inst {667 bits<5> ft;668 bits<5> fs;669 670 bits<32> Inst;671 672 let Inst{31-26} = 0b010101;673 let Inst{25-21} = ft;674 let Inst{20-16} = fs;675 let Inst{15} = 0;676 let Inst{14-13} = fmt;677 let Inst{12-6} = funct;678 let Inst{5-0} = 0b111011;679}680 681class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>682 : MMR6Arch<instr_asm>, MipsR6Inst {683 bits<5> ft;684 bits<5> fs;685 686 bits<32> Inst;687 688 let Inst{31-26} = 0b010101;689 let Inst{25-21} = ft;690 let Inst{20-16} = fs;691 let Inst{15} = 0;692 let Inst{14} = fmt;693 let Inst{13-6} = funct;694 let Inst{5-0} = 0b111011;695}696 697class POOL16A_ADDU16_FM_MMR6 {698 bits<3> rs;699 bits<3> rt;700 bits<3> rd;701 702 bits<16> Inst;703 704 let Inst{15-10} = 0b000001;705 let Inst{9-7} = rs;706 let Inst{6-4} = rt;707 let Inst{3-1} = rd;708 let Inst{0} = 0;709}710 711class POOL16C_AND16_FM_MMR6 {712 bits<3> rt;713 bits<3> rs;714 715 bits<16> Inst;716 717 let Inst{15-10} = 0b010001;718 let Inst{9-7} = rt;719 let Inst{6-4} = rs;720 let Inst{3-0} = 0b0001;721}722 723class POOL16C_NOT16_FM_MMR6 {724 bits<3> rt;725 bits<3> rs;726 727 bits<16> Inst;728 729 let Inst{15-10} = 0x11;730 let Inst{9-7} = rt;731 let Inst{6-4} = rs;732 let Inst{3-0} = 0b0000;733}734 735class POOL16C_MOVEP16_FM_MMR6 {736 bits<3> rt;737 bits<3> rs;738 739 bits<16> Inst;740 741 let Inst{15-10} = 0b010001;742 // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a743 // special encoding of both rd1 and rd2.744 let Inst{9-7} = ?;745 let Inst{6-4} = rt;746 let Inst{3} = rs{2};747 let Inst{2} = 0b1;748 let Inst{1-0} = rs{1-0};749}750 751class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {752 bits<3> rt;753 bits<3> rs;754 755 bits<16> Inst;756 757 let Inst{15-10} = 0b010001;758 let Inst{9-7} = rt;759 let Inst{6-4} = rs;760 let Inst{3-0} = op;761}762 763class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {764 bits<4> code_;765 bits<16> Inst;766 767 let Inst{15-10} = 0b010001;768 let Inst{9-6} = code_;769 let Inst{5-0} = op;770}771 772class POOL16A_SUBU16_FM_MMR6 {773 bits<3> rs;774 bits<3> rt;775 bits<3> rd;776 777 bits<16> Inst;778 779 let Inst{15-10} = 0b000001;780 let Inst{9-7} = rs;781 let Inst{6-4} = rt;782 let Inst{3-1} = rd;783 let Inst{0} = 0b1;784}785 786class POOL32A_WRPGPR_WSBH_FM_MMR6<string instr_asm, bits<10> funct>787 : MMR6Arch<instr_asm>, MipsR6Inst {788 bits<5> rt;789 bits<5> rs;790 791 bits<32> Inst;792 793 let Inst{31-26} = 0x00;794 let Inst{25-21} = rt;795 let Inst{20-16} = rs;796 let Inst{15-6} = funct;797 let Inst{5-0} = 0x3c;798}799 800class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>801 : MMR6Arch<instr_asm>, MipsR6Inst {802 bits<5> ft;803 bits<5> fs;804 805 bits<32> Inst;806 807 let Inst{31-26} = 0b010101;808 let Inst{25-21} = ft;809 let Inst{20-16} = fs;810 let Inst{15} = 0;811 let Inst{14} = fmt;812 let Inst{13-6} = funct;813 let Inst{5-0} = 0b111011;814}815 816class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> : MMR6Arch<instr_asm>,817 MipsR6Inst {818 bits<5> fs;819 bits<5> fd;820 821 bits<32> Inst;822 823 let Inst{31-26} = 0b010101;824 let Inst{25-21} = fs;825 let Inst{20-16} = fd;826 let Inst{15-11} = 0;827 let Inst{10-9} = fmt;828 let Inst{8-0} = 0b000100000;829}830 831class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>832 : MMR6Arch<instr_asm>, MipsR6Inst {833 bits<5> ft;834 bits<5> fs;835 bits<5> fd;836 837 bits<32> Inst;838 839 let Inst{31-26} = 0b010101;840 let Inst{25-21} = ft;841 let Inst{20-16} = fs;842 let Inst{15-11} = fd;843 let Inst{10-9} = fmt;844 let Inst{8-0} = funct;845}846 847class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>848 : MMR6Arch<instr_asm>, MipsR6Inst {849 bits<5> fs;850 bits<5> fd;851 852 bits<32> Inst;853 854 let Inst{31-26} = 0b010101;855 let Inst{25-21} = fs;856 let Inst{20-16} = fd;857 let Inst{15-11} = 0b00000;858 let Inst{10-9} = fmt;859 let Inst{8-0} = funct;860}861 862class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>863 : MMR6Arch<instr_asm>, MipsR6Inst {864 bits<32> Inst;865 866 let Inst{31-26} = 0x0;867 let Inst{25-16} = 0x0;868 let Inst{15-6} = funct;869 let Inst{5-0} = 0b111100;870}871 872class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>873 : MMR6Arch<instr_asm>, MipsR6Inst {874 bits<5> rt;875 bits<5> rs;876 bits<3> sel;877 878 bits<32> Inst;879 880 let Inst{31-26} = 0b000000;881 let Inst{25-21} = rt;882 let Inst{20-16} = rs;883 let Inst{15-14} = 0;884 let Inst{13-11} = sel;885 let Inst{10-6} = funct;886 let Inst{5-0} = opcode;887}888 889class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv>890 : MMR6Arch<instr_asm>, MipsR6Inst {891 bits<5> rs;892 bits<2> type;893 894 bits<32> Inst;895 896 let Inst{31-26} = 0x0;897 let Inst{25-21} = 0x0;898 let Inst{20-16} = rs;899 let Inst{15-13} = 0b011;900 let Inst{12-11} = ginv;901 let Inst{10-9} = type;902 let Inst{8-6} = 0b101;903 let Inst{5-0} = 0b111100;904}905 906class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>907 : MMR6Arch<instr_asm> {908 bits<5> rt;909 bits<5> fs;910 911 bits<32> Inst;912 913 let Inst{31-26} = 0b010101;914 let Inst{25-21} = rt;915 let Inst{20-16} = fs;916 let Inst{15-14} = 0;917 let Inst{13-6} = funct;918 let Inst{5-0} = 0b111011;919}920 921class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>922 : MMR6Arch<instr_asm>, MipsR6Inst {923 bits<5> rt;924 bits<5> impl;925 926 bits<32> Inst;927 928 let Inst{31-26} = 0b000000;929 let Inst{25-21} = rt;930 let Inst{20-16} = impl;931 let Inst{15-6} = funct;932 let Inst{5-0} = 0b111100;933}934 935class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>936 : MipsR6Inst, MMR6Arch<opstr> {937 bits<5> rt;938 bits<5> rs;939 bits<16> offset;940 941 bits<32> Inst;942 943 let Inst{31-26} = funct;944 let Inst{25-21} = rt;945 let Inst{20-16} = rs;946 let Inst{15-0} = offset;947}948 949class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>950 : MMR6Arch<instr_asm>, MipsR6Inst {951 bits<5> rs;952 953 bits<32> Inst;954 955 let Inst{31-26} = 0b000000;956 let Inst{25-21} = 0b00000;957 let Inst{20-16} = rs;958 let Inst{15-6} = funct;959 let Inst{5-0} = 0b111100;960}961 962class CMP_BRANCH_OFF21_FM_MMR6<bits<6> funct> : MipsR6Inst {963 bits<5> rs;964 bits<21> offset;965 966 bits<32> Inst;967 968 let Inst{31-26} = funct;969 let Inst{25-21} = rs;970 let Inst{20-0} = offset;971}972 973class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>974 : MMR6Arch<instr_asm> {975 bits<5> rt;976 bits<16> offset;977 978 bits<32> Inst;979 980 let Inst{31-26} = 0b010000;981 let Inst{25-21} = funct;982 let Inst{20-16} = rt;983 let Inst{15-0} = offset;984}985 986class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>987 : MMR6Arch<instr_asm> {988 bits<5> ft;989 bits<21> addr;990 bits<5> base = addr{20-16};991 bits<16> offset = addr{15-0};992 993 bits<32> Inst;994 995 let Inst{31-26} = funct;996 let Inst{25-21} = ft;997 let Inst{20-16} = base;998 let Inst{15-0} = offset;999}1000 1001class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>1002 : MMR6Arch<instr_asm>, MipsR6Inst {1003 bits<5> rt;1004 bits<21> addr;1005 bits<5> base = addr{20-16};1006 bits<11> offset = addr{10-0};1007 1008 bits<32> Inst;1009 1010 let Inst{31-26} = 0b001000;1011 let Inst{25-21} = rt;1012 let Inst{20-16} = base;1013 let Inst{15-12} = funct;1014 let Inst{11} = 0;1015 let Inst{10-0} = offset;1016}1017 1018class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc,1019 bits<3> minorFunc> : MMR6Arch<instr_asm>,1020 MipsR6Inst {1021 bits<5> rt;1022 bits<21> addr;1023 bits<5> base = addr{20-16};1024 bits<9> offset = addr{8-0};1025 1026 bits<32> Inst;1027 1028 let Inst{31-26} = 0b011000;1029 let Inst{25-21} = rt;1030 let Inst{20-16} = base;1031 let Inst{15-12} = majorFunc;1032 let Inst{11-9} = minorFunc;1033 let Inst{8-0} = offset;1034}1035