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1//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the microMIPS FPU instruction set.10//11//===----------------------------------------------------------------------===//12 13multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm,14 SDPatternOperator OpNode = null_frag> {15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,16 FGR_32 {17 string DecoderNamespace = "MicroMips";18 }19 // FIXME: This needs to be part of the instruction mapping tables.20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {21 string DecoderNamespace = "MicroMipsFP64";22 }23}24 25def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,26 ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS;27def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,28 ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS;29def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,30 ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS;31def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,32 ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS;33 34defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,35 ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS;36defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,37 ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS;38defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,39 ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS;40defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,41 ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS;42 43let DecoderNamespace = "MicroMips" in {44 def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,45 LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;46 def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,47 SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;48 49 def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>,50 LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;51 def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>,52 SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;53}54let isCodeGenOnly = 1 in {55def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,56 CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 {57 // FIXME: This is a required to work around the fact that these instructions58 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the59 // fcc register set is used directly.60 bits<3> fcc = 0;61}62 63def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,64 CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 {65 // FIXME: This is a required to work around the fact that these instructions66 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the67 // fcc register set is used directly.68 bits<3> fcc = 0;69}70 71}72 73let DecoderNamespace = "MicroMips" in {74 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,75 BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;76 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,77 BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;78 def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,79 ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;80}81 82let DecoderNamespace = "MicroMips" in {83 def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd,84 FGR32Opnd, II_ROUND>,85 ROUND_W_FM_MM<0, 0xec>, ISA_MICROMIPS;86 87 def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,88 ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32;89 def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,90 ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;91 def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd,92 AFGR64Opnd, II_ROUND>,93 ROUND_W_FM_MM<1, 0xec>, ISA_MICROMIPS, FGR_32;94 def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,95 ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;96 97 def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,98 ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;99 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,100 ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;101 102 def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,103 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;104}105let DecoderNamespace = "MicroMipsFP64" in {106 def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>,107 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64;108}109 110multiclass ABSS_MMM<string opstr, InstrItinClass Itin,111 SDPatternOperator OpNode = null_frag> {112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,113 ISA_MICROMIPS, FGR_32 {114 string DecoderNamespace = "MicroMips";115 }116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,117 ISA_MICROMIPS, FGR_64 {118 string DecoderNamespace = "MicroMipsFP64";119 }120}121 122defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;123defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;124 125let DecoderNamespace = "MicroMips", AdditionalPredicates = [UseAbs] in {126 def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,127 ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;128}129 130def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,131 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS {132 let isMoveReg = 1;133}134def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,135 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;136 137let DecoderNamespace = "MicroMips" in {138 def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,139 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32;140 def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,141 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32;142}143 144let DecoderNamespace = "MicroMipsFP64" in {145 def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,146 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64;147 def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,148 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64;149 def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,150 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64;151}152 153let DecoderNamespace = "MicroMips" in {154 def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,155 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;156 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,157 ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;158}159 160 161defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;162defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;163 164let DecoderNamespace = "MicroMips" in {165 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,166 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,167 ISA_MICROMIPS32_NOT_MIPS32R6;168 def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,169 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>,170 ISA_MICROMIPS32_NOT_MIPS32R6;171 def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,172 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,173 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;174 def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,175 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>,176 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;177 178 def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,179 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>,180 ISA_MICROMIPS32_NOT_MIPS32R6;181 def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,182 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,183 ISA_MICROMIPS32_NOT_MIPS32R6;184 def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,185 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,186 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;187 def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,188 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,189 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;190 191 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,192 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,193 ISA_MICROMIPS;194 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,195 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,196 ISA_MICROMIPS;197 198 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,199 MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;200 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,201 MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;202 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {203 def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,204 MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;205 def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,206 MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;207 }208 def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>,209 MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,210 MADD4;211 def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,212 MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,213 MADD4;214 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {215 def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,216 MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;217 def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,218 MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;219 }220 221 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,222 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>,223 ISA_MICROMIPS;224 def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,225 FGR32Opnd, II_TRUNC>,226 ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;227 def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,228 ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;229 230 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,231 fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;232 233 def MTHC1_D32_MM : MMRel,234 MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,235 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;236 def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,237 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;238}239 240let DecoderNamespace = "MicroMipsFP64" in {241 def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,242 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64;243 def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,244 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64;245 def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>,246 MFC1_FM_MM<0xa0>, ISA_MICROMIPS, FGR_64;247}248 249let DecoderNamespace = "MicroMips" in {250 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,251 MFC1_FM_MM<0x40>, ISA_MICROMIPS;252 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,253 MFC1_FM_MM<0x60>, ISA_MICROMIPS;254 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,255 II_RECIP_S>,256 ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS;257 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,258 II_RECIP_D>,259 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 {260 let BaseOpcode = "RECIP_D32";261 }262 let DecoderNamespace = "MicroMipsFP64" in263 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,264 II_RECIP_D>,265 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64;266 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,267 II_RECIP_S>,268 ROUND_W_FM_MM<0b0, 0b00001000>, ISA_MICROMIPS;269 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,270 II_RECIP_D>,271 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 {272 let BaseOpcode = "RSQRT_D32";273 }274 let DecoderNamespace = "MicroMipsFP64" in275 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,276 II_RECIP_D>,277 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64;278}279 280let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {281 def LDC1_MM_D32 : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,282 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 {283 let BaseOpcode = "LDC132";284 }285 def SDC1_MM_D32 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,286 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32 {287 let BaseOpcode = "SDC164";288 }289 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,290 LW_FM_MM<0x27>, ISA_MICROMIPS;291 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,292 LW_FM_MM<0x26>, ISA_MICROMIPS;293}294 295let DecoderNamespace = "Mips64", DecoderMethod = "DecodeFMemMMR2" in {296 def LDC1_MM_D64 : MMRel, LW_FT<"ldc1", FGR64Opnd, mem_mm_16, II_LDC1, load>,297 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_64 {298 let BaseOpcode = "LDC164";299 }300 def SDC1_MM_D64 : MMRel, SW_FT<"sdc1", FGR64Opnd, mem_mm_16, II_SDC1, store>,301 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_64 {302 let BaseOpcode = "SDC164";303 }304}305 306 307multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,308 InstrItinClass itin> {309 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,310 C_COND_FM_MM<fmt, 0> {311 let BaseOpcode = "c.f."#NAME;312 let isCommutable = 1;313 }314 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,315 C_COND_FM_MM<fmt, 1> {316 let BaseOpcode = "c.un."#NAME;317 let isCommutable = 1;318 }319 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,320 C_COND_FM_MM<fmt, 2> {321 let BaseOpcode = "c.eq."#NAME;322 let isCommutable = 1;323 }324 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,325 C_COND_FM_MM<fmt, 3> {326 let BaseOpcode = "c.ueq."#NAME;327 let isCommutable = 1;328 }329 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,330 C_COND_FM_MM<fmt, 4> {331 let BaseOpcode = "c.olt."#NAME;332 }333 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,334 C_COND_FM_MM<fmt, 5> {335 let BaseOpcode = "c.ult."#NAME;336 }337 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,338 C_COND_FM_MM<fmt, 6> {339 let BaseOpcode = "c.ole."#NAME;340 }341 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,342 C_COND_FM_MM<fmt, 7> {343 let BaseOpcode = "c.ule."#NAME;344 }345 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,346 C_COND_FM_MM<fmt, 8> {347 let BaseOpcode = "c.sf."#NAME;348 let isCommutable = 1;349 }350 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,351 C_COND_FM_MM<fmt, 9> {352 let BaseOpcode = "c.ngle."#NAME;353 }354 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,355 C_COND_FM_MM<fmt, 10> {356 let BaseOpcode = "c.seq."#NAME;357 let isCommutable = 1;358 }359 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,360 C_COND_FM_MM<fmt, 11> {361 let BaseOpcode = "c.ngl."#NAME;362 }363 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,364 C_COND_FM_MM<fmt, 12> {365 let BaseOpcode = "c.lt."#NAME;366 }367 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,368 C_COND_FM_MM<fmt, 13> {369 let BaseOpcode = "c.nge."#NAME;370 }371 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,372 C_COND_FM_MM<fmt, 14> {373 let BaseOpcode = "c.le."#NAME;374 }375 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,376 C_COND_FM_MM<fmt, 15> {377 let BaseOpcode = "c.ngt."#NAME;378 }379}380let DecoderNamespace = "MicroMips" in {381 defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,382 ISA_MICROMIPS32_NOT_MIPS32R6;383 defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,384 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;385}386 387let DecoderNamespace = "Mips64" in388 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,389 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64;390 391defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,392 ISA_MICROMIPS32_NOT_MIPS32R6;393defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,394 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;395defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,396 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64;397 398defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,399 ISA_MICROMIPS32_NOT_MIPS32R6, HARDFLOAT;400 401 402// To generate NMADD and NMSUB instructions when fneg node is present403let AdditionalPredicates = [NoNaNsFPMath, HasMadd4,404 InMicroMips, NotMips32r6] in {405 defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>,406 ISA_MICROMIPS32_NOT_MIPS32R6;407 defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>,408 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;409}410 411//===----------------------------------------------------------------------===//412// Floating Point Patterns413//===----------------------------------------------------------------------===//414 415// Patterns for loads/stores with a reg+imm operand.416let AddedComplexity = 40 in {417 def : LoadRegImmPat<LDC1_MM_D32, f64, load>, ISA_MICROMIPS, FGR_32;418 def : StoreRegImmPat<SDC1_MM_D32, f64>, ISA_MICROMIPS, FGR_32;419 def : LoadRegImmPat<LDC1_MM_D64, f64, load>, ISA_MICROMIPS, FGR_64;420 def : StoreRegImmPat<SDC1_MM_D64, f64>, ISA_MICROMIPS, FGR_64;421 def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS;422 def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS;423}424 425def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),426 (MTC1_D64_MM GPR32Opnd:$src)>, ISA_MICROMIPS, FGR_64;427 428def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6;429def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>,430 ISA_MICROMIPS32_NOT_MIPS32R6;431 432def : MipsPat<(f32 (fpround FGR64Opnd:$src)),433 (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64;434def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),435 (CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64;436def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),437 (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32;438def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),439 (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32;440def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),441 (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,442 FGR_32;443def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),444 (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,445 FGR_64;446def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),447 (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6;448 449// Selects450defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,451 ISA_MICROMIPS32_NOT_MIPS32R6;452defm : MovzPats1<GPR32, FGR32, MOVZ_I_S_MM, XOR_MM>,453 ISA_MICROMIPS32_NOT_MIPS32R6;454 455defm : MovnPats<GPR32, FGR32, MOVN_I_S_MM, XOR_MM>,456 ISA_MICROMIPS32_NOT_MIPS32R6;457 458defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32_MM, SLT_MM, SLTu_MM, SLTi_MM,459 SLTiu_MM>,460 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;461defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32_MM, XOR_MM>,462 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;463defm : MovnPats<GPR32, AFGR64, MOVN_I_D32_MM, XOR_MM>,464 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;465