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1//===--- MicroMipsInstrFormats.td - microMIPS Inst Defs -*- tablegen -*----===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This files describes the definitions of the microMIPSr3 instructions.10//11//===----------------------------------------------------------------------===//12 13def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;14def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;15def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;16def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;17 18def simm9_addiusp : Operand<i32> {19 let EncoderMethod = "getSImm9AddiuspValue";20 let DecoderMethod = "DecodeSimm9SP";21}22 23def uimm3_shift : Operand<i32> {24 let EncoderMethod = "getUImm3Mod8Encoding";25 let DecoderMethod = "DecodePOOL16BEncodedField";26}27 28def simm3_lsa2 : Operand<i32> {29 let EncoderMethod = "getSImm3Lsa2Value";30 let DecoderMethod = "DecodeAddiur2Simm7";31}32 33def uimm4_andi : Operand<i32> {34 let EncoderMethod = "getUImm4AndValue";35 let DecoderMethod = "DecodeANDI16Imm";36}37 38def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||39 ((Imm % 4 == 0) &&40 Imm < 28 && Imm > 0);}]>;41 42def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;43 44def immZExtAndi16 : ImmLeaf<i32,45 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||46 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||47 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;48 49def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;50 51def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;52 53def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {54 let Name = "MicroMipsMem";55 let RenderMethod = "addMicroMipsMemOperands";56 let ParserMethod = "parseMemOperand";57 let PredicateMethod = "isMemWithGRPMM16Base";58}59 60class mem_mm_4_generic : Operand<i32> {61 let PrintMethod = "printMemOperand";62 let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);63 let OperandType = "OPERAND_MEMORY";64 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;65}66 67def mem_mm_4 : mem_mm_4_generic {68 let EncoderMethod = "getMemEncodingMMImm4";69}70 71def mem_mm_4_lsl1 : mem_mm_4_generic {72 let EncoderMethod = "getMemEncodingMMImm4Lsl1";73}74 75def mem_mm_4_lsl2 : mem_mm_4_generic {76 let EncoderMethod = "getMemEncodingMMImm4Lsl2";77}78 79def MicroMipsMemSPAsmOperand : AsmOperandClass {80 let Name = "MicroMipsMemSP";81 let RenderMethod = "addMemOperands";82 let ParserMethod = "parseMemOperand";83 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";84}85 86def MicroMipsMemGPAsmOperand : AsmOperandClass {87 let Name = "MicroMipsMemGP";88 let RenderMethod = "addMemOperands";89 let ParserMethod = "parseMemOperand";90 let PredicateMethod = "isMemWithSimmWordAlignedOffsetGP<9>";91}92 93def mem_mm_sp_imm5_lsl2 : Operand<i32> {94 let PrintMethod = "printMemOperand";95 let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);96 let OperandType = "OPERAND_MEMORY";97 let ParserMatchClass = MicroMipsMemSPAsmOperand;98 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";99}100 101def mem_mm_gp_simm7_lsl2 : Operand<i32> {102 let PrintMethod = "printMemOperand";103 let MIOperandInfo = (ops ptr_gp_rc:$base, simm7_lsl2:$offset);104 let OperandType = "OPERAND_MEMORY";105 let ParserMatchClass = MicroMipsMemGPAsmOperand;106 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";107}108 109def mem_mm_9 : Operand<i32> {110 let PrintMethod = "printMemOperand";111 let MIOperandInfo = (ops mips_ptr_rc, simm9);112 let EncoderMethod = "getMemEncodingMMImm9";113 let ParserMatchClass = MipsMemSimmAsmOperand<9>;114 let OperandType = "OPERAND_MEMORY";115}116 117def mem_mm_11 : Operand<i32> {118 let PrintMethod = "printMemOperand";119 let MIOperandInfo = (ops GPR32, simm11);120 let EncoderMethod = "getMemEncodingMMImm11";121 let ParserMatchClass = MipsMemSimmAsmOperand<11>;122 let OperandType = "OPERAND_MEMORY";123}124 125def mem_mm_12 : Operand<i32> {126 let PrintMethod = "printMemOperand";127 let MIOperandInfo = (ops mips_ptr_rc, simm12);128 let EncoderMethod = "getMemEncodingMMImm12";129 let ParserMatchClass = MipsMemAsmOperand;130 let OperandType = "OPERAND_MEMORY";131}132 133def mem_mm_16 : Operand<i32> {134 let PrintMethod = "printMemOperand";135 let MIOperandInfo = (ops mips_ptr_rc, simm16);136 let EncoderMethod = "getMemEncodingMMImm16";137 let DecoderMethod = "DecodeMemMMImm16";138 let ParserMatchClass = MipsMemSimmAsmOperand<16>;139 let OperandType = "OPERAND_MEMORY";140}141 142def MipsMemUimm4AsmOperand : AsmOperandClass {143 let Name = "MemOffsetUimm4";144 let SuperClasses = [MipsMemAsmOperand];145 let RenderMethod = "addMemOperands";146 let ParserMethod = "parseMemOperand";147 let PredicateMethod = "isMemWithUimmOffsetSP<6>";148}149 150def mem_mm_4sp : Operand<i32> {151 let PrintMethod = "printMemOperand";152 let MIOperandInfo = (ops ptr_sp_rc, uimm8);153 let EncoderMethod = "getMemEncodingMMImm4sp";154 let ParserMatchClass = MipsMemUimm4AsmOperand;155 let OperandType = "OPERAND_MEMORY";156}157 158def jmptarget_mm : Operand<OtherVT> {159 let EncoderMethod = "getJumpTargetOpValueMM";160 let PrintMethod = "printJumpOperand";161}162 163def calltarget_mm : Operand<iPTR> {164 let EncoderMethod = "getJumpTargetOpValueMM";165 let PrintMethod = "printJumpOperand";166}167 168def brtarget7_mm : Operand<OtherVT> {169 let EncoderMethod = "getBranchTarget7OpValueMM";170 let OperandType = "OPERAND_PCREL";171 let DecoderMethod = "DecodeBranchTarget7MM";172 let ParserMatchClass = MipsJumpTargetAsmOperand;173 let PrintMethod = "printBranchOperand";174}175 176def brtarget10_mm : Operand<OtherVT> {177 let EncoderMethod = "getBranchTargetOpValueMMPC10";178 let OperandType = "OPERAND_PCREL";179 let DecoderMethod = "DecodeBranchTarget10MM";180 let ParserMatchClass = MipsJumpTargetAsmOperand;181 let PrintMethod = "printBranchOperand";182}183 184def brtarget_mm : Operand<OtherVT> {185 let EncoderMethod = "getBranchTargetOpValueMM";186 let OperandType = "OPERAND_PCREL";187 let DecoderMethod = "DecodeBranchTargetMM";188 let ParserMatchClass = MipsJumpTargetAsmOperand;189 let PrintMethod = "printBranchOperand";190}191 192def simm23_lsl2 : Operand<i32> {193 let EncoderMethod = "getSimm23Lsl2Encoding";194 let DecoderMethod = "DecodeSimm23Lsl2";195}196 197class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :198 InstSE<(outs), (ins RO:$rs, opnd:$offset),199 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {200 let isBranch = 1;201 let isTerminator = 1;202 let hasDelaySlot = 0;203 let Defs = [AT];204}205 206let canFoldAsLoad = 1 in207class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,208 Operand MemOpnd, InstrItinClass Itin> :209 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),210 !strconcat(opstr, "\t$rt, $addr"),211 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],212 Itin, FrmI> {213 let DecoderMethod = "DecodeMemMMImm12";214 string Constraints = "$src = $rt";215 let BaseOpcode = opstr;216 bit mayLoad = 1;217 bit mayStore = 0;218}219 220class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,221 Operand MemOpnd, InstrItinClass Itin>:222 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),223 !strconcat(opstr, "\t$rt, $addr"),224 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {225 let DecoderMethod = "DecodeMemMMImm12";226 let BaseOpcode = opstr;227 bit mayLoad = 0;228 bit mayStore = 1;229}230 231class MovePMM16<string opstr, RegisterOperand RO1, RegisterOperand RO2,232 RegisterOperand RO3> :233MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),234 !strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],235 NoItinerary, FrmR> {236 let isReMaterializable = 1;237 let isMoveReg = 1;238 let DecoderMethod = "DecodeMovePOperands";239}240 241class StorePairMM<string opstr>242 : InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),243 !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {244 let DecoderMethod = "DecodeMemMMImm12";245 let mayStore = 1;246 let AsmMatchConverter = "ConvertXWPOperands";247}248 249class LoadPairMM<string opstr>250 : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),251 !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {252 let DecoderMethod = "DecodeMemMMImm12";253 let mayLoad = 1;254 let AsmMatchConverter = "ConvertXWPOperands";255}256 257class LLBaseMM<string opstr, RegisterOperand RO> :258 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),259 !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {260 let DecoderMethod = "DecodeMemMMImm12";261 let mayLoad = 1;262}263 264class LLEBaseMM<string opstr, RegisterOperand RO> :265 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),266 !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {267 let DecoderMethod = "DecodeMemMMImm9";268 string BaseOpcode = opstr;269 let mayLoad = 1;270}271 272class SCBaseMM<string opstr, RegisterOperand RO> :273 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),274 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {275 let DecoderMethod = "DecodeMemMMImm12";276 let mayStore = 1;277 let Constraints = "$rt = $dst";278}279 280class SCEBaseMM<string opstr, RegisterOperand RO> :281 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),282 !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {283 let DecoderMethod = "DecodeMemMMImm9";284 string BaseOpcode = opstr;285 let mayStore = 1;286 let Constraints = "$rt = $dst";287}288 289class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,290 InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :291 InstSE<(outs RO:$rt), (ins MO:$addr),292 !strconcat(opstr, "\t$rt, $addr"),293 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {294 let DecoderMethod = "DecodeMemMMImm12";295 let canFoldAsLoad = 1;296 let mayLoad = 1;297}298 299class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,300 InstrItinClass Itin = NoItinerary,301 SDPatternOperator OpNode = null_frag> :302 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),303 !strconcat(opstr, "\t$rd, $rs, $rt"),304 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {305 let isCommutable = isComm;306}307 308class AndImmMM16<string opstr, RegisterOperand RO,309 InstrItinClass Itin = NoItinerary> :310 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),311 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;312 313class LogicRMM16<string opstr, RegisterOperand RO,314 InstrItinClass Itin = NoItinerary,315 SDPatternOperator OpNode = null_frag> :316 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),317 !strconcat(opstr, "\t$rt, $rs"),318 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {319 let isCommutable = 1;320 let Constraints = "$rt = $dst";321}322 323class NotMM16<string opstr, RegisterOperand RO> :324 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),325 !strconcat(opstr, "\t$rt, $rs"),326 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;327 328class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,329 InstrItinClass Itin = NoItinerary> :330 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),331 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;332 333class LoadMM16<string opstr, DAGOperand RO,334 InstrItinClass Itin, Operand MemOpnd> :335 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),336 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {337 let DecoderMethod = "DecodeMemMMImm4";338 let canFoldAsLoad = 1;339 let mayLoad = 1;340}341 342class StoreMM16<string opstr, DAGOperand RTOpnd, InstrItinClass Itin,343 Operand MemOpnd> :344 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),345 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {346 let DecoderMethod = "DecodeMemMMImm4";347 let mayStore = 1;348}349 350class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,351 Operand MemOpnd> :352 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),353 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {354 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";355 let canFoldAsLoad = 1;356 let mayLoad = 1;357}358 359class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,360 Operand MemOpnd> :361 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),362 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {363 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";364 let mayStore = 1;365}366 367class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,368 Operand MemOpnd> :369 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),370 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {371 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";372 let canFoldAsLoad = 1;373 let mayLoad = 1;374}375 376class AddImmUR2<string opstr, RegisterOperand RO> :377 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),378 !strconcat(opstr, "\t$rd, $rs, $imm"),379 [], II_ADDIU, FrmR> {380 let isCommutable = 1;381}382 383class AddImmUS5<string opstr, RegisterOperand RO> :384 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),385 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {386 let Constraints = "$rd = $dst";387}388 389class AddImmUR1SP<string opstr, RegisterOperand RO> :390 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),391 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;392 393class AddImmUSP<string opstr> :394 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),395 !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;396 397class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :398 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),399 [], II_MFHI_MFLO, FrmR> {400 let Uses = [UseReg];401 let hasSideEffects = 0;402 let isMoveReg = 1;403}404 405class MoveMM16<string opstr, RegisterOperand RO>406 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),407 !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {408 let isReMaterializable = 1;409 let isMoveReg = 1;410}411 412class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :413 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),414 !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {415 let isReMaterializable = 1;416}417 418// 16-bit Jump and Link (Call)419class JumpLinkRegMM16<string opstr, RegisterOperand RO> :420 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),421 [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {422 let isCall = 1;423 let hasDelaySlot = 1;424 let Defs = [RA];425 let hasPostISelHook = 1;426}427 428// 16-bit Jump Reg429class JumpRegMM16<string opstr, RegisterOperand RO> :430 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),431 [], II_JR, FrmR> {432 let hasDelaySlot = 1;433 let isBranch = 1;434 let isIndirectBranch = 1;435}436 437// Base class for JRADDIUSP instruction.438class JumpRAddiuStackMM16 :439 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",440 [], II_JRADDIUSP, FrmR> {441 let isTerminator = 1;442 let isBarrier = 1;443 let isBranch = 1;444 let isIndirectBranch = 1;445}446 447// 16-bit Jump and Link (Call) - Short Delay Slot448class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :449 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),450 [], II_JALRS, FrmR> {451 let isCall = 1;452 let hasDelaySlot = 1;453 let Defs = [RA];454}455 456// 16-bit Jump Register Compact - No delay slot457class JumpRegCMM16<string opstr, RegisterOperand RO> :458 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),459 [], II_JRC, FrmR> {460 let isTerminator = 1;461 let isBarrier = 1;462 let isBranch = 1;463 let isIndirectBranch = 1;464}465 466// Break16 and Sdbbp16467class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :468 MicroMipsInst16<(outs), (ins uimm4:$code_),469 !strconcat(opstr, "\t$code_"),470 [], Itin, FrmOther>;471 472class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :473 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),474 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {475 let isBranch = 1;476 let isTerminator = 1;477 let hasDelaySlot = 1;478 let Defs = [AT];479}480 481// MicroMIPS Jump and Link (Call) - Short Delay Slot482let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {483 class JumpLinkMM<string opstr, DAGOperand opnd> :484 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),485 [], II_JALS, FrmJ, opstr> {486 let DecoderMethod = "DecodeJumpTargetMM";487 }488 489 class JumpLinkRegMM<string opstr, RegisterOperand RO>:490 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),491 [], II_JALRS, FrmR>;492 493 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,494 RegisterOperand RO> :495 InstSE<(outs), (ins RO:$rs, opnd:$offset),496 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;497}498 499class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO> :500 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),501 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;502 503class PrefetchIndexed<string opstr> :504 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),505 !strconcat(opstr, "\t$hint, ${index}(${base})"),506 [], II_PREF, FrmOther>;507 508class AddImmUPC<string opstr, RegisterOperand RO> :509 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),510 !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;511 512/// A list of registers used by load/store multiple instructions.513def RegListAsmOperand : AsmOperandClass {514 let Name = "RegList";515 let ParserMethod = "parseRegisterList";516}517 518def reglist : Operand<i32> {519 let EncoderMethod = "getRegisterListOpValue";520 let ParserMatchClass = RegListAsmOperand;521 let PrintMethod = "printRegisterList";522 let DecoderMethod = "DecodeRegListOperand";523}524 525def RegList16AsmOperand : AsmOperandClass {526 let Name = "RegList16";527 let ParserMethod = "parseRegisterList";528 let PredicateMethod = "isRegList16";529 let RenderMethod = "addRegListOperands";530}531 532def reglist16 : Operand<i32> {533 let EncoderMethod = "getRegisterListOpValue16";534 let DecoderMethod = "DecodeRegListOperand16";535 let PrintMethod = "printRegisterList";536 let ParserMatchClass = RegList16AsmOperand;537}538 539class StoreMultMM<string opstr, InstrItinClass Itin> :540 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),541 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {542 let DecoderMethod = "DecodeMemMMImm12";543 let mayStore = 1;544}545 546class LoadMultMM<string opstr, InstrItinClass Itin> :547 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),548 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {549 let DecoderMethod = "DecodeMemMMImm12";550 let mayLoad = 1;551}552 553class StoreMultMM16<string opstr, InstrItinClass Itin> :554 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),555 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {556 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";557 let mayStore = 1;558}559 560class LoadMultMM16<string opstr, InstrItinClass Itin> :561 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),562 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {563 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";564 let mayLoad = 1;565}566 567class UncondBranchMM16<string opstr> :568 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),569 !strconcat(opstr, "\t$offset"),570 [], II_B, FrmI> {571 let isBranch = 1;572 let isTerminator = 1;573 let isBarrier = 1;574 let hasDelaySlot = 1;575 let Predicates = [RelocPIC, InMicroMips];576 let Defs = [AT];577}578 579class HypcallMM<string opstr> :580 InstSE<(outs), (ins uimm10:$code_),581 !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther> {582 let BaseOpcode = opstr;583}584 585class TLBINVMM<string opstr, InstrItinClass Itin> :586 InstSE<(outs), (ins), opstr, [], Itin, FrmOther> {587 let BaseOpcode = opstr;588}589 590class MfCop0MM<string opstr, RegisterOperand DstRC,591 RegisterOperand SrcRC, InstrItinClass Itin> :592 InstSE<(outs DstRC:$rt), (ins SrcRC:$rs, uimm3:$sel),593 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {594 let BaseOpcode = opstr;595}596 597class MtCop0MM<string opstr, RegisterOperand DstRC,598 RegisterOperand SrcRC, InstrItinClass Itin> :599 InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),600 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {601 let BaseOpcode = opstr;602}603 604let FastISelShouldIgnore = 1 in {605 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,606 ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;607 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,608 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;609}610 611def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,612 ISA_MICROMIPS32_NOT_MIPS32R6;613def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,614 ISA_MICROMIPS32_NOT_MIPS32R6;615let FastISelShouldIgnore = 1 in616 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,617 ISA_MICROMIPS32_NOT_MIPS32R6;618def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,619 SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;620def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,621 SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;622 623let FastISelShouldIgnore = 1 in {624 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,625 ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;626 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,627 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;628}629def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, II_LBU, mem_mm_4>,630 LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;631def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, II_LHU, mem_mm_4_lsl1>,632 LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;633def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, II_LW, mem_mm_4_lsl2>,634 LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;635def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>,636 LOAD_STORE_FM_MM16<0x22>,637 ISA_MICROMIPS32_NOT_MIPS32R6;638def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>,639 LOAD_STORE_FM_MM16<0x2a>,640 ISA_MICROMIPS32_NOT_MIPS32R6;641def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>,642 LOAD_STORE_FM_MM16<0x3a>,643 ISA_MICROMIPS32_NOT_MIPS32R6;644def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,645 LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;646def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,647 LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;648def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,649 LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;650def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,651 ISA_MICROMIPS;652def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,653 ISA_MICROMIPS;654def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,655 ISA_MICROMIPS;656def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;657def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,658 MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;659def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,660 MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;661def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>,662 ISA_MICROMIPS32_NOT_MIPS32R6;663def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,664 GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,665 MOVEP_FM_MM16, ISA_MICROMIPS32_NOT_MIPS32R6;666def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,667 IsAsCheapAsAMove, ISA_MICROMIPS32_NOT_MIPS32R6;668def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,669 ISA_MICROMIPS32_NOT_MIPS32R6;670def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>,671 ISA_MICROMIPS32_NOT_MIPS32R6;672def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>,673 ISA_MICROMIPS32_NOT_MIPS32R6;674def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>,675 ISA_MICROMIPS32_NOT_MIPS32R6;676def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>,677 ISA_MICROMIPS32_NOT_MIPS32R6;678def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,679 BEQNEZ_FM_MM16<0x23>, ISA_MICROMIPS32_NOT_MIPS32R6;680def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,681 BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;682def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;683def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,684 ISA_MICROMIPS32_NOT_MIPS32R6;685def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,686 ISA_MICROMIPS32_NOT_MIPS32R6;687 688class WaitMM<string opstr> :689 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],690 II_WAIT, FrmOther, opstr>;691 692let DecoderNamespace = "MicroMips" in {693 /// Load and Store Instructions - multiple694 def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,695 ISA_MICROMIPS32_NOT_MIPS32R6;696 def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,697 ISA_MICROMIPS32_NOT_MIPS32R6;698 def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),699 "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,700 POOL32A_CFTC2_FM_MM<0b1100110100>, ISA_MICROMIPS;701 def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),702 "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,703 POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;704 705 /// Compact Branch Instructions706 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, GPR32Opnd>,707 COMPACT_BRANCH_FM_MM<0x7>, ISA_MICROMIPS32_NOT_MIPS32R6;708 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, GPR32Opnd>,709 COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;710 711 /// Arithmetic Instructions (ALU Immediate)712 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,713 ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;714 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,715 ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;716 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,717 SLTI_FM_MM<0x24>, ISA_MICROMIPS;718 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,719 SLTI_FM_MM<0x2c>, ISA_MICROMIPS;720 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,721 ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;722 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,723 or>, ADDI_FM_MM<0x14>,724 ISA_MICROMIPS32_NOT_MIPS32R6;725 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,726 immZExt16, xor>, ADDI_FM_MM<0x1c>,727 ISA_MICROMIPS32_NOT_MIPS32R6;728 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,729 ISA_MICROMIPS32_NOT_MIPS32R6;730 731 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,732 LW_FM_MM<0xc>, ISA_MICROMIPS;733 734 /// Arithmetic Instructions (3-Operand, R-Type)735 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,736 ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;737 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,738 ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;739 let Defs = [HI0, LO0] in740 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,741 ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;742 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,743 ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;744 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,745 ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;746 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,747 ISA_MICROMIPS;748 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,749 ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;750 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,751 ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;752 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,753 ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;754 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,755 ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;756 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>,757 ISA_MICROMIPS32_NOT_MIPS32R6;758 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,759 MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;760 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,761 MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;762 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,763 MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;764 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,765 MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;766 767 /// Arithmetic Instructions with PC and Immediate768 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM,769 ISA_MICROMIPS32_NOT_MIPS32R6;770 771 /// Shift Instructions772 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,773 SRA_FM_MM<0, 0>, ISA_MICROMIPS;774 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,775 SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;776 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,777 SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;778 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,779 SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;780 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,781 SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;782 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,783 SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;784 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,785 SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {786 list<dag> Pattern = [(set GPR32Opnd:$rd,787 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];788 }789 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,790 SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {791 list<dag> Pattern = [(set GPR32Opnd:$rd,792 (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];793 }794 795 /// Load and Store Instructions - aligned796 let DecoderMethod = "DecodeMemMMImm16" in {797 def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,798 MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;799 def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,800 MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;801 def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,802 addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;803 def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,804 MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;805 def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,806 ISA_MICROMIPS;807 def SB_MM : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,808 LW_FM_MM<0x6>, ISA_MICROMIPS;809 def SH_MM : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,810 LW_FM_MM<0xe>, ISA_MICROMIPS;811 def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,812 LW_FM_MM<0x3e>, ISA_MICROMIPS;813 }814 815 let DecoderMethod = "DecodeMemMMImm9" in {816 def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,817 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;818 def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,819 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;820 def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,821 II_LHE>,822 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;823 def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,824 II_LHUE>,825 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;826 def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,827 II_LWE>,828 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;829 def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,830 II_SBE>,831 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;832 def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,833 II_SHE>,834 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;835 def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,836 II_SWE>,837 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;838 def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,839 II_LWLE>,840 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,841 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;842 def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,843 II_LWRE>,844 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,845 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;846 def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,847 II_SWLE>,848 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,849 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;850 def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,851 II_SWRE>,852 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,853 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;854 }855 856 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>,857 ISA_MICROMIPS;858 859 /// Load and Store Instructions - unaligned860 def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12,861 II_LWL>, LWL_FM_MM<0x0>,862 ISA_MICROMIPS32_NOT_MIPS32R6;863 def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12,864 II_LWR>, LWL_FM_MM<0x1>,865 ISA_MICROMIPS32_NOT_MIPS32R6;866 def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12,867 II_SWL>, LWL_FM_MM<0x8>,868 ISA_MICROMIPS32_NOT_MIPS32R6;869 def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12,870 II_SWR>, LWL_FM_MM<0x9>,871 ISA_MICROMIPS32_NOT_MIPS32R6;872 873 /// Load and Store Instructions - multiple874 def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;875 def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;876 877 /// Load and Store Pair Instructions878 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;879 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>, ISA_MICROMIPS;880 881 /// Load and Store multiple pseudo Instructions882 class LoadWordMultMM<string instr_asm > :883 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),884 !strconcat(instr_asm, "\t$rt, $addr")> ;885 886 class StoreWordMultMM<string instr_asm > :887 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),888 !strconcat(instr_asm, "\t$rt, $addr")> ;889 890 891 def SWM_MM : StoreWordMultMM<"swm">, ISA_MICROMIPS;892 def LWM_MM : LoadWordMultMM<"lwm">, ISA_MICROMIPS;893 894 /// Move Conditional895 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,896 II_MOVZ>, ADD_FM_MM<0, 0x58>,897 ISA_MICROMIPS32_NOT_MIPS32R6;898 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,899 II_MOVN>, ADD_FM_MM<0, 0x18>,900 ISA_MICROMIPS32_NOT_MIPS32R6;901 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,902 CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;903 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,904 CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;905 /// Move to/from HI/LO906 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,907 MTLO_FM_MM<0x0b5>, ISA_MICROMIPS32_NOT_MIPS32R6;908 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,909 MTLO_FM_MM<0x0f5>, ISA_MICROMIPS32_NOT_MIPS32R6;910 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,911 MFLO_FM_MM<0x035>, ISA_MICROMIPS32_NOT_MIPS32R6;912 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,913 MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;914 915 /// Multiply Add/Sub Instructions916 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,917 ISA_MICROMIPS32_NOT_MIPS32R6;918 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,919 ISA_MICROMIPS32_NOT_MIPS32R6;920 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,921 ISA_MICROMIPS32_NOT_MIPS32R6;922 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,923 ISA_MICROMIPS32_NOT_MIPS32R6;924 925 /// Count Leading926 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,927 ISA_MICROMIPS;928 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,929 ISA_MICROMIPS;930 931 /// Sign Ext In Register Instructions.932 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,933 SEB_FM_MM<0x0ac>, ISA_MICROMIPS;934 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,935 SEB_FM_MM<0x0ec>, ISA_MICROMIPS;936 937 /// Word Swap Bytes Within Halfwords938 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,939 SEB_FM_MM<0x1ec>, ISA_MICROMIPS;940 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction941 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,942 immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,943 ISA_MICROMIPS32_NOT_MIPS32R6;944 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,945 immZExt5, immZExt5Plus1>,946 EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;947 948 /// Jump Instructions949 let DecoderMethod = "DecodeJumpTargetMM" in {950 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,951 J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,952 IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;953 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,954 ISA_MICROMIPS32_NOT_MIPS32R6;955 }956 957 let DecoderMethod = "DecodeJumpTargetXMM" in958 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,959 ISA_MICROMIPS32_NOT_MIPS32R6;960 961 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,962 ISA_MICROMIPS32_NOT_MIPS32R6;963 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,964 ISA_MICROMIPS32_NOT_MIPS32R6;965 966 /// Jump Instructions - Short Delay Slot967 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,968 ISA_MICROMIPS32_NOT_MIPS32R6;969 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>,970 ISA_MICROMIPS32_NOT_MIPS32R6;971 972 /// Branch Instructions973 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,974 BEQ_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;975 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,976 BEQ_FM_MM<0x2d>, ISA_MICROMIPS32_NOT_MIPS32R6;977 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,978 BGEZ_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;979 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,980 BGEZ_FM_MM<0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;981 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,982 BGEZ_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;983 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,984 BGEZ_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6;985 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,986 BGEZAL_FM_MM<0x03>, ISA_MICROMIPS32_NOT_MIPS32R6;987 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,988 BGEZAL_FM_MM<0x01>, ISA_MICROMIPS32_NOT_MIPS32R6;989 def BAL_BR_MM : BAL_BR_Pseudo<BGEZAL_MM, brtarget_mm>,990 ISA_MICROMIPS32_NOT_MIPS32R6;991 992 /// Branch Instructions - Short Delay Slot993 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,994 GPR32Opnd>, BGEZAL_FM_MM<0x13>,995 ISA_MICROMIPS32_NOT_MIPS32R6;996 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,997 GPR32Opnd>, BGEZAL_FM_MM<0x11>,998 ISA_MICROMIPS32_NOT_MIPS32R6;999 def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch,1000 ISA_MICROMIPS32_NOT_MIPS32R6;1001 1002 /// Control Instructions1003 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;1004 let DecoderMethod = "DecodeSyncI_MM" in1005 def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,1006 ISA_MICROMIPS32_NOT_MIPS32R6;1007 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;1008 def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,1009 ISA_MICROMIPS;1010 def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;1011 def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,1012 ISA_MICROMIPS;1013 def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,1014 ISA_MICROMIPS;1015 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,1016 ISA_MICROMIPS;1017 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,1018 ISA_MICROMIPS;1019 def TRAP_MM : TrapBase<BREAK_MM>, ISA_MICROMIPS;1020 1021 /// Trap Instructions1022 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,1023 ISA_MICROMIPS;1024 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>,1025 ISA_MICROMIPS;1026 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,1027 TEQ_FM_MM<0x10>, ISA_MICROMIPS;1028 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>,1029 ISA_MICROMIPS;1030 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,1031 TEQ_FM_MM<0x28>, ISA_MICROMIPS;1032 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>,1033 ISA_MICROMIPS;1034 1035 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>,1036 ISA_MICROMIPS32_NOT_MIPS32R6;1037 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>,1038 ISA_MICROMIPS32_NOT_MIPS32R6;1039 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,1040 TEQI_FM_MM<0x0b>, ISA_MICROMIPS32_NOT_MIPS32R6;1041 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>,1042 ISA_MICROMIPS32_NOT_MIPS32R6;1043 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,1044 TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6;1045 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>,1046 ISA_MICROMIPS32_NOT_MIPS32R6;1047 1048 /// Load-linked, Store-conditional1049 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>,1050 ISA_MICROMIPS32_NOT_MIPS32R6;1051 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>,1052 ISA_MICROMIPS32_NOT_MIPS32R6;1053 1054 def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,1055 ISA_MICROMIPS, ASE_EVA;1056 def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,1057 ISA_MICROMIPS, ASE_EVA;1058 1059 let DecoderMethod = "DecodeCacheOpMM" in {1060 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,1061 CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;1062 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,1063 CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;1064 }1065 1066 let DecoderMethod = "DecodePrefeOpMM" in {1067 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,1068 CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;1069 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,1070 CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;1071 }1072 def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,1073 ISA_MICROMIPS;1074 def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,1075 ISA_MICROMIPS;1076 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,1077 ISA_MICROMIPS;1078 1079 def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>,1080 ISA_MICROMIPS;1081 def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>,1082 ISA_MICROMIPS;1083 def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>,1084 ISA_MICROMIPS;1085 def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>,1086 ISA_MICROMIPS;1087 1088 def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM,1089 ISA_MICROMIPS;1090 1091 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,1092 ISA_MICROMIPS32_NOT_MIPS32R6;1093}1094 1095let AdditionalPredicates = [NotDSP] in {1096 def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,1097 ISA_MICROMIPS32_NOT_MIPS32R6;1098 def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,1099 ISA_MICROMIPS32_NOT_MIPS32R6;1100 def PseudoMFHI_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>,1101 ISA_MICROMIPS32_NOT_MIPS32R6;1102 def PseudoMFLO_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>,1103 ISA_MICROMIPS32_NOT_MIPS32R6;1104 def PseudoMTLOHI_MM : PseudoMTLOHI<ACC64, GPR32>,1105 ISA_MICROMIPS32_NOT_MIPS32R6;1106 def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,1107 ISA_MICROMIPS32_NOT_MIPS32R6;1108 def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,1109 ISA_MICROMIPS32_NOT_MIPS32R6;1110 def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,1111 ISA_MICROMIPS32_NOT_MIPS32R6;1112 def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,1113 ISA_MICROMIPS32_NOT_MIPS32R6;1114}1115 1116def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>,1117 ISA_MICROMIPS32_NOT_MIPS32R6;1118 1119def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>,1120 ISA_MICROMIPS32_NOT_MIPS32R6;1121 1122def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,1123 ISA_MICROMIPS32_NOT_MIPS32R6;1124 1125let DecoderNamespace = "MicroMips" in {1126 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,1127 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;1128 def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,1129 mem_simm12>, LL_FM_MM<0xe>,1130 ISA_MICROMIPS32_NOT_MIPS32R6;1131 1132 def MFGC0_MM : MMRel, MfCop0MM<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,1133 POOL32A_MFTC0_FM_MM<0b10011, 0b111100>,1134 ISA_MICROMIPS32R5, ASE_VIRT;1135 def MFHGC0_MM : MMRel, MfCop0MM<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,1136 POOL32A_MFTC0_FM_MM<0b10011, 0b110100>,1137 ISA_MICROMIPS32R5, ASE_VIRT;1138 def MTGC0_MM : MMRel, MtCop0MM<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,1139 POOL32A_MFTC0_FM_MM<0b11011, 0b111100>,1140 ISA_MICROMIPS32R5, ASE_VIRT;1141 def MTHGC0_MM : MMRel, MtCop0MM<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,1142 POOL32A_MFTC0_FM_MM<0b11011, 0b110100>,1143 ISA_MICROMIPS32R5, ASE_VIRT;1144 def HYPCALL_MM : MMRel, HypcallMM<"hypcall">, POOL32A_HYPCALL_FM_MM,1145 ISA_MICROMIPS32R5, ASE_VIRT;1146 def TLBGINV_MM : MMRel, TLBINVMM<"tlbginv", II_TLBGINV>,1147 POOL32A_TLBINV_FM_MM<0x105>, ISA_MICROMIPS32R5, ASE_VIRT;1148 def TLBGINVF_MM : MMRel, TLBINVMM<"tlbginvf", II_TLBGINVF>,1149 POOL32A_TLBINV_FM_MM<0x145>, ISA_MICROMIPS32R5, ASE_VIRT;1150 def TLBGP_MM : MMRel, TLBINVMM<"tlbgp", II_TLBGP>,1151 POOL32A_TLBINV_FM_MM<0x5>, ISA_MICROMIPS32R5, ASE_VIRT;1152 def TLBGR_MM : MMRel, TLBINVMM<"tlbgr", II_TLBGR>,1153 POOL32A_TLBINV_FM_MM<0x45>, ISA_MICROMIPS32R5, ASE_VIRT;1154 def TLBGWI_MM : MMRel, TLBINVMM<"tlbgwi", II_TLBGWI>,1155 POOL32A_TLBINV_FM_MM<0x85>, ISA_MICROMIPS32R5, ASE_VIRT;1156 def TLBGWR_MM : MMRel, TLBINVMM<"tlbgwr", II_TLBGWR>,1157 POOL32A_TLBINV_FM_MM<0xc5>, ISA_MICROMIPS32R5, ASE_VIRT;1158}1159 1160//===----------------------------------------------------------------------===//1161// MicroMips arbitrary patterns that map to one or more instructions1162//===----------------------------------------------------------------------===//1163 1164defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, ZERO, GPR32Opnd>, ISA_MICROMIPS;1165 1166def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi_MM tglobaladdr:$in)>,1167 ISA_MICROMIPS;1168def : MipsPat<(MipsGotHi texternalsym:$in), (LUi_MM texternalsym:$in)>,1169 ISA_MICROMIPS;1170 1171def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi_MM tglobaltlsaddr:$in)>,1172 ISA_MICROMIPS;1173 1174// gp_rel relocs1175def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),1176 (ADDiu_MM GPR32:$gp, tglobaladdr:$in)>, ISA_MICROMIPS;1177def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),1178 (ADDiu_MM GPR32:$gp, tconstpool:$in)>, ISA_MICROMIPS;1179 1180def : WrapperPat<tglobaladdr, ADDiu_MM, GPR32>, ISA_MICROMIPS;1181def : WrapperPat<tconstpool, ADDiu_MM, GPR32>, ISA_MICROMIPS;1182def : WrapperPat<texternalsym, ADDiu_MM, GPR32>, ISA_MICROMIPS;1183def : WrapperPat<tblockaddress, ADDiu_MM, GPR32>, ISA_MICROMIPS;1184def : WrapperPat<tjumptable, ADDiu_MM, GPR32>, ISA_MICROMIPS;1185def : WrapperPat<tglobaltlsaddr, ADDiu_MM, GPR32>, ISA_MICROMIPS;1186 1187def : MipsPat<(atomic_load_asext_8 addr:$a), (LB_MM addr:$a)>, ISA_MICROMIPS;1188def : MipsPat<(atomic_load_asext_16 addr:$a), (LH_MM addr:$a)>, ISA_MICROMIPS;1189def : MipsPat<(atomic_load_nonext_32 addr:$a), (LW_MM addr:$a)>, ISA_MICROMIPS;1190 1191def : MipsPat<(i32 immLi16:$imm),1192 (LI16_MM immLi16:$imm)>, ISA_MICROMIPS;1193 1194defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;1195 1196def : MipsPat<(not GPRMM16:$in),1197 (NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS;1198def : MipsPat<(not GPR32:$in),1199 (NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS;1200 1201def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),1202 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>, ISA_MICROMIPS;1203def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),1204 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>, ISA_MICROMIPS;1205def : MipsPat<(add GPR32:$src, immSExt16:$imm),1206 (ADDiu_MM GPR32:$src, immSExt16:$imm)>, ISA_MICROMIPS;1207 1208def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),1209 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>, ISA_MICROMIPS;1210def : MipsPat<(and GPR32:$src, immZExt16:$imm),1211 (ANDi_MM GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS;1212 1213def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),1214 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;1215def : MipsPat<(shl GPR32:$src, immZExt5:$imm),1216 (SLL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;1217def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),1218 (SLLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;1219 1220def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),1221 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;1222def : MipsPat<(srl GPR32:$src, immZExt5:$imm),1223 (SRL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;1224def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),1225 (SRLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;1226 1227def : MipsPat<(sra GPR32:$src, immZExt5:$imm),1228 (SRA_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;1229def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),1230 (SRAV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;1231 1232def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),1233 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS;1234def : MipsPat<(store GPR32:$src, addr:$addr),1235 (SW_MM GPR32:$src, addr:$addr)>, ISA_MICROMIPS;1236 1237def : MipsPat<(load addrimm4lsl2:$addr),1238 (LW16_MM addrimm4lsl2:$addr)>, ISA_MICROMIPS;1239def : MipsPat<(load addr:$addr),1240 (LW_MM addr:$addr)>, ISA_MICROMIPS;1241def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),1242 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;1243 1244def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>,1245 ISA_MICROMIPS;1246 1247def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>,1248 ISA_MICROMIPS;1249 1250def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,1251 ISA_MICROMIPS;1252 1253let AddedComplexity = 40 in1254 def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),1255 (LH_MM addrRegImm:$a)>, ISA_MICROMIPS;1256 1257 1258def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,1259 ISA_MICROMIPS;1260 1261def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),1262 (JAL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;1263def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),1264 (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;1265def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),1266 (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;1267 1268defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,1269 SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;1270 1271def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),1272 (BLEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;1273def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),1274 (BGEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;1275 1276defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>, ISA_MICROMIPS;1277defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;1278defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>, ISA_MICROMIPS;1279defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;1280defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>, ISA_MICROMIPS;1281 1282// Select patterns1283 1284// Instantiation of conditional move patterns.1285defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,1286 ISA_MICROMIPS32_NOT_MIPS32R6;1287defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,1288 ISA_MICROMIPS32_NOT_MIPS32R6;1289defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,1290 ISA_MICROMIPS32_NOT_MIPS32R6;1291 1292 1293defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, INSN_MIPS4_32_NOT_32R6_64R6;1294 1295// Instantiation of conditional move patterns.1296defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,1297 ISA_MICROMIPS32_NOT_MIPS32R6;1298defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,1299 ISA_MICROMIPS32_NOT_MIPS32R6;1300defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,1301 ISA_MICROMIPS32_NOT_MIPS32R6;1302 1303defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, ISA_MICROMIPS32_NOT_MIPS32R6;1304 1305//===----------------------------------------------------------------------===//1306// MicroMips instruction aliases1307//===----------------------------------------------------------------------===//1308 1309class UncondBranchMMPseudo<string opstr> :1310 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),1311 !strconcat(opstr, "\t$offset")>;1312 1313def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;1314 1315let EncodingPredicates = [InMicroMips] in {1316 def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,1317 II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;1318 def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,1319 II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;1320 1321 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;1322 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;1323 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;1324 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;1325 def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;1326 def : MipsInstAlias<"neg $rt, $rs",1327 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,1328 ISA_MICROMIPS32_NOT_MIPS32R6;1329 def : MipsInstAlias<"neg $rt",1330 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,1331 ISA_MICROMIPS32_NOT_MIPS32R6;1332 def : MipsInstAlias<"negu $rt, $rs",1333 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,1334 ISA_MICROMIPS32_NOT_MIPS32R6;1335 def : MipsInstAlias<"negu $rt",1336 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,1337 ISA_MICROMIPS32_NOT_MIPS32R6;1338 def : MipsInstAlias<"teq $rs, $rt",1339 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1340 def : MipsInstAlias<"tge $rs, $rt",1341 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1342 def : MipsInstAlias<"tgeu $rs, $rt",1343 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1344 def : MipsInstAlias<"tlt $rs, $rt",1345 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1346 def : MipsInstAlias<"tltu $rs, $rt",1347 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1348 def : MipsInstAlias<"tne $rs, $rt",1349 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;1350 def : MipsInstAlias<1351 "sgt $rd, $rs, $rt",1352 (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1353 def : MipsInstAlias<1354 "sgt $rs, $rt",1355 (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1356 def : MipsInstAlias<1357 "sgtu $rd, $rs, $rt",1358 (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1359 def : MipsInstAlias<1360 "sgtu $rs, $rt",1361 (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1362 def : MipsInstAlias<"sll $rd, $rt, $rs",1363 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1364 def : MipsInstAlias<"sra $rd, $rt, $rs",1365 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1366 def : MipsInstAlias<"srl $rd, $rt, $rs",1367 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;1368 def : MipsInstAlias<"sll $rd, $rt",1369 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;1370 def : MipsInstAlias<"sra $rd, $rt",1371 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;1372 def : MipsInstAlias<"srl $rd, $rt",1373 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;1374 def : MipsInstAlias<"sll $rd, $shamt",1375 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;1376 def : MipsInstAlias<"sra $rd, $shamt",1377 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;1378 def : MipsInstAlias<"srl $rd, $shamt",1379 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;1380 def : MipsInstAlias<"rotr $rt, $imm",1381 (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;1382 def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS;1383 1384 def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;1385 1386 defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;1387 1388 defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;1389 1390 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS;1391 1392 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS;1393 1394 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>, ISA_MICROMIPS;1395 1396 defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>, ISA_MICROMIPS;1397 1398 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;1399 1400 def : MipsInstAlias<"not $rt, $rs",1401 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,1402 ISA_MICROMIPS32_NOT_MIPS32R6;1403 def : MipsInstAlias<"not $rt",1404 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,1405 ISA_MICROMIPS32_NOT_MIPS32R6;1406 def : MipsInstAlias<"bnez $rs,$offset",1407 (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,1408 ISA_MICROMIPS;1409 def : MipsInstAlias<"beqz $rs,$offset",1410 (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,1411 ISA_MICROMIPS;1412 def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,1413 ISA_MICROMIPS;1414 def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,1415 ISA_MICROMIPS;1416 def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;1417 def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,1418 ISA_MICROMIPS;1419 def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,1420 ISA_MICROMIPS32_NOT_MIPS32R6;1421 1422 def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,1423 ISA_MICROMIPS32_NOT_MIPS32R6;1424}1425def : MipsInstAlias<"rdhwr $rt, $rs",1426 (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,1427 ISA_MICROMIPS32_NOT_MIPS32R6;1428 1429def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,1430 ISA_MICROMIPS32R5, ASE_VIRT;1431def : MipsInstAlias<"mfgc0 $rt, $rs",1432 (MFGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,1433 ISA_MICROMIPS32R5, ASE_VIRT;1434def : MipsInstAlias<"mfhgc0 $rt, $rs",1435 (MFHGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,1436 ISA_MICROMIPS32R5, ASE_VIRT;1437def : MipsInstAlias<"mtgc0 $rt, $rs",1438 (MTGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,1439 ISA_MICROMIPS32R5, ASE_VIRT;1440def : MipsInstAlias<"mthgc0 $rt, $rs",1441 (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,1442 ISA_MICROMIPS32R5, ASE_VIRT;1443def : MipsInstAlias<"sw $rt, $offset",1444 (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,1445 ISA_MICROMIPS;1446