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1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// This is the top level entry point for the Mips target.9//===----------------------------------------------------------------------===//10 11//===----------------------------------------------------------------------===//12// Target-independent interfaces13//===----------------------------------------------------------------------===//14 15include "llvm/Target/Target.td"16 17// The overall idea of the PredicateControl class is to chop the Predicates list18// into subsets that are usually overridden independently. This allows19// subclasses to partially override the predicates of their superclasses without20// having to re-add all the existing predicates.21class PredicateControl {22 // Predicates for the encoding scheme in use such as HasStdEnc23 list<Predicate> EncodingPredicates = [];24 // Predicates for the GPR size such as IsGP64bit25 list<Predicate> GPRPredicates = [];26 // Predicates for the PTR size such as IsPTR64bit27 list<Predicate> PTRPredicates = [];28 // Predicates for a symbol's size such as hasSym32.29 list<Predicate> SYMPredicates = [];30 // Predicates for the FGR size and layout such as IsFP64bit31 list<Predicate> FGRPredicates = [];32 // Predicates for the instruction group membership such as ISA's.33 list<Predicate> InsnPredicates = [];34 // Predicate for the ASE that an instruction belongs to.35 list<Predicate> ASEPredicate = [];36 // Predicate for marking the instruction as usable in hard-float mode only.37 list<Predicate> HardFloatPredicate = [];38 // Predicates for anything else39 list<Predicate> AdditionalPredicates = [];40 list<Predicate> Predicates = !listconcat(EncodingPredicates,41 GPRPredicates,42 PTRPredicates,43 SYMPredicates,44 FGRPredicates,45 InsnPredicates,46 HardFloatPredicate,47 ASEPredicate,48 AdditionalPredicates);49}50 51// Like Requires<> but for the AdditionalPredicates list52class AdditionalRequires<list<Predicate> preds> {53 list<Predicate> AdditionalPredicates = preds;54}55 56//===----------------------------------------------------------------------===//57// Mips Subtarget features //58//===----------------------------------------------------------------------===//59 60def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",61 "Disable SVR4-style position-independent code">;62def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",63 "Pointers are 64-bit wide">;64def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",65 "General Purpose Registers are 64-bit wide">;66def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",67 "Support 64-bit FP registers">;68def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",69 "Support for FPXX">;70def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",71 "IEEE 754-2008 NaN encoding">;72def FeatureAbs2008 : SubtargetFeature<"abs2008", "Abs2008", "true",73 "Disable IEEE 754-2008 abs.fmt mode">;74def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",75 "true", "Only supports single precision float">;76def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",77 "Does not support floating point instructions">;78def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",79 "Disable odd numbered single-precision "80 "registers">;81def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",82 "true", "Enable vector FPU instructions">;83def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",84 "Mips I ISA Support [highly experimental]">;85def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",86 "Mips II ISA Support [highly experimental]",87 [FeatureMips1]>;88def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",89 "Subset of MIPS-III that is also in MIPS32 "90 "[highly experimental]">;91def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",92 "Subset of MIPS-III that is also in MIPS32r2 "93 "[highly experimental]">;94def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",95 "MIPS III ISA Support [highly experimental]",96 [FeatureMips2, FeatureMips3_32,97 FeatureMips3_32r2, FeatureGP64Bit,98 FeatureFP64Bit]>;99def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",100 "Subset of MIPS-IV that is also in MIPS32 "101 "[highly experimental]">;102def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",103 "Subset of MIPS-IV that is also in MIPS32r2 "104 "[highly experimental]">;105def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",106 "Mips4", "MIPS IV ISA Support",107 [FeatureMips3, FeatureMips4_32,108 FeatureMips4_32r2]>;109def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",110 "Subset of MIPS-V that is also in MIPS32r2 "111 "[highly experimental]">;112def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",113 "MIPS V ISA Support [highly experimental]",114 [FeatureMips4, FeatureMips5_32r2]>;115def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",116 "Mips32 ISA Support",117 [FeatureMips2, FeatureMips3_32,118 FeatureMips4_32]>;119def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",120 "Mips32r2", "Mips32r2 ISA Support",121 [FeatureMips3_32r2, FeatureMips4_32r2,122 FeatureMips5_32r2, FeatureMips32]>;123def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",124 "Mips32r3", "Mips32r3 ISA Support",125 [FeatureMips32r2]>;126def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",127 "Mips32r5", "Mips32r5 ISA Support",128 [FeatureMips32r3]>;129def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",130 "Mips32r6",131 "Mips32r6 ISA Support [experimental]",132 [FeatureMips32r5, FeatureFP64Bit,133 FeatureNaN2008, FeatureAbs2008]>;134def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",135 "Mips64", "Mips64 ISA Support",136 [FeatureMips5, FeatureMips32]>;137def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",138 "Mips64r2", "Mips64r2 ISA Support",139 [FeatureMips64, FeatureMips32r2]>;140def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",141 "Mips64r3", "Mips64r3 ISA Support",142 [FeatureMips64r2, FeatureMips32r3]>;143def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",144 "Mips64r5", "Mips64r5 ISA Support",145 [FeatureMips64r3, FeatureMips32r5]>;146def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",147 "Mips64r6",148 "Mips64r6 ISA Support [experimental]",149 [FeatureMips32r6, FeatureMips64r5,150 FeatureNaN2008, FeatureAbs2008]>;151def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",152 "Symbols are 32 bit on Mips64">;153 154def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",155 "Mips16 mode">;156 157def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;158def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",159 "Mips DSP-R2 ASE", [FeatureDSP]>;160def FeatureDSPR3161 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",162 [ FeatureDSP, FeatureDSPR2 ]>;163 164def FeatureMips3D : SubtargetFeature<"mips3d", "Has3D", "true", "Mips 3D ASE">;165 166def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;167 168def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;169 170def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;171 172def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",173 "Mips Virtualization ASE">;174 175def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",176 "Mips Global Invalidate ASE">;177 178def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",179 "microMips mode">;180 181def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",182 "true", "Octeon cnMIPS Support",183 [FeatureMips64r2]>;184 185def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",186 "true", "Octeon+ cnMIPS Support",187 [FeatureCnMips]>;188 189def FeatureUseTCCInDIV : SubtargetFeature<190 "use-tcc-in-div",191 "UseTCCInDIV", "false",192 "Force the assembler to use trapping">;193 194def FeatureNoMadd4195 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",196 "Disable 4-operand madd.fmt and related instructions">;197 198def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;199 200def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",201 "Disable use of the jal instruction">;202 203def FeatureXGOT204 : SubtargetFeature<"xgot", "UseXGOT", "true", "Assume 32-bit GOT">;205 206def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",207 "UseIndirectJumpsHazard",208 "true", "Use indirect jump"209 " guards to prevent certain speculation based attacks">;210 211def FeatureStrictAlign212 : SubtargetFeature<"strict-align", "StrictAlign", "true",213 "Disable unaligned load store for r6">;214 215//===----------------------------------------------------------------------===//216// Mips Instruction Predicate Definitions.217//===----------------------------------------------------------------------===//218 219def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,220 AssemblerPredicate<(all_of FeaturePTR64Bit)>;221def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,222 AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;223 224//===----------------------------------------------------------------------===//225// HwModes226//===----------------------------------------------------------------------===//227 228defvar MIPS32 = DefaultMode;229def MIPS64 : HwMode<[IsPTR64bit]>;230 231//===----------------------------------------------------------------------===//232// Register File, Calling Conv, Instruction Descriptions233//===----------------------------------------------------------------------===//234 235include "MipsRegisterInfo.td"236include "MipsSchedule.td"237include "MipsInstrInfo.td"238include "MipsCallingConv.td"239include "MipsRegisterBanks.td"240include "MipsCombine.td"241 242// Avoid forward declaration issues.243include "MipsScheduleI6400.td"244include "MipsScheduleP5600.td"245include "MipsScheduleGeneric.td"246 247defm : RemapAllTargetPseudoPointerOperands<mips_ptr_rc>;248 249def MipsInstrInfo : InstrInfo {250}251 252//===----------------------------------------------------------------------===//253// Mips processors supported.254//===----------------------------------------------------------------------===//255 256def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",257 "MipsSubtarget::CPU::P5600",258 "The P5600 Processor", [FeatureMips32r5]>;259 260// The I6500 is the multi-cluster version of the I6400. Both are based on the261// same CPU architecture.262def ImplI6400263 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",264 "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;265 266def ImplI6500267 : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",268 "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;269 270class Proc<string Name, list<SubtargetFeature> Features>271 : ProcessorModel<Name, MipsGenericModel, Features>;272 273def : Proc<"generic", [FeatureMips32]>;274def : Proc<"mips1", [FeatureMips1]>;275def : Proc<"mips2", [FeatureMips2]>;276def : Proc<"mips32", [FeatureMips32]>;277def : Proc<"mips32r2", [FeatureMips32r2]>;278def : Proc<"mips32r3", [FeatureMips32r3]>;279def : Proc<"mips32r5", [FeatureMips32r5]>;280def : Proc<"mips32r6", [FeatureMips32r6]>;281 282def : Proc<"mips3", [FeatureMips3]>;283def : Proc<"mips4", [FeatureMips4]>;284def : Proc<"mips5", [FeatureMips5]>;285def : Proc<"mips64", [FeatureMips64]>;286def : Proc<"mips64r2", [FeatureMips64r2]>;287def : Proc<"mips64r3", [FeatureMips64r3]>;288def : Proc<"mips64r5", [FeatureMips64r5]>;289def : Proc<"mips64r6", [FeatureMips64r6]>;290def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;291def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;292def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;293def : ProcessorModel<"i6400", MipsI6400Model, [ImplI6400]>;294def : ProcessorModel<"i6500", MipsI6400Model, [ImplI6500]>;295 296def MipsAsmParser : AsmParser {297 let ShouldEmitMatchRegisterName = 0;298}299 300def MipsAsmParserVariant : AsmParserVariant {301 int Variant = 0;302 303 // Recognize hard coded registers.304 string RegisterPrefix = "$";305}306 307def MipsAsmWriter : AsmWriter {308 int PassSubtarget = 1;309}310 311def Mips : Target {312 let InstructionSet = MipsInstrInfo;313 let AssemblyWriters = [MipsAsmWriter];314 let AssemblyParsers = [MipsAsmParser];315 let AssemblyParserVariants = [MipsAsmParserVariant];316 let AllowRegisterRenaming = 1;317}318 319//===----------------------------------------------------------------------===//320// Pfm Counters321//===----------------------------------------------------------------------===//322 323include "MipsPfmCounters.td"324