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1//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Describe MIPS instructions format11//12// CPU INSTRUCTION FORMATS13//14// funct or f Function field15//16// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or17// or imm address displacement18//19// op 5-bit major operation code20//21// rx 3-bit source or destination register22//23// ry 3-bit source or destination register24//25// rz 3-bit source or destination register26//27// sa 3- or 5-bit shift amount28//29//===----------------------------------------------------------------------===//30 31 32// Base class for Mips 16 Format33// This class does not depend on the instruction size34//35class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,36 InstrItinClass itin>: Instruction37{38 39 let Namespace = "Mips";40 41 let OutOperandList = outs;42 let InOperandList = ins;43 44 let AsmString = asmstr;45 let Pattern = pattern;46 let Itinerary = itin;47 48 let Predicates = [InMips16Mode];49}50 51//52// Generic Mips 16 Format53//54class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,55 InstrItinClass itin>:56 MipsInst16_Base<outs, ins, asmstr, pattern, itin>57{58 field bits<16> Inst;59 bits<5> Opcode = 0;60 61 // Top 5 bits are the 'opcode' field62 let Inst{15-11} = Opcode;63 64 let Size=2;65}66 67//68// For 32 bit extended instruction forms.69//70class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,71 InstrItinClass itin>:72 MipsInst16_Base<outs, ins, asmstr, pattern, itin>73{74 field bits<32> Inst;75 76 let Size=4;77}78 79class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,80 InstrItinClass itin>:81 MipsInst16_32<outs, ins, asmstr, pattern, itin>82{83 let Inst{31-27} = 0b11110;84}85 86 87 88// Mips Pseudo Instructions Format89class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:90 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {91 let isCodeGenOnly = 1;92 let isPseudo = 1;93}94 95 96//===----------------------------------------------------------------------===//97// Format I instruction class in Mips : <|opcode|imm11|>98//===----------------------------------------------------------------------===//99 100class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,101 InstrItinClass itin>:102 MipsInst16<outs, ins, asmstr, pattern, itin>103{104 bits<11> imm11;105 106 let Opcode = op;107 108 let Inst{10-0} = imm11;109}110 111//===----------------------------------------------------------------------===//112// Format RI instruction class in Mips : <|opcode|rx|imm8|>113//===----------------------------------------------------------------------===//114 115class FRI16<bits<5> op, dag outs, dag ins, string asmstr,116 list<dag> pattern, InstrItinClass itin>:117 MipsInst16<outs, ins, asmstr, pattern, itin>118{119 bits<3> rx;120 bits<8> imm8;121 122 let Opcode = op;123 124 let Inst{10-8} = rx;125 let Inst{7-0} = imm8;126}127 128//===----------------------------------------------------------------------===//129// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>130//===----------------------------------------------------------------------===//131 132class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,133 list<dag> pattern, InstrItinClass itin>:134 MipsInst16<outs, ins, asmstr, pattern, itin>135{136 bits<3> rx;137 bits<3> ry;138 bits<5> funct;139 140 let Opcode = 0b11101;141 let funct = _funct;142 143 let Inst{10-8} = rx;144 let Inst{7-5} = ry;145 let Inst{4-0} = funct;146}147 148class FRRBreak16<dag outs, dag ins, string asmstr,149 list<dag> pattern, InstrItinClass itin>:150 MipsInst16<outs, ins, asmstr, pattern, itin>151{152 bits<6> Code;153 bits<5> funct;154 155 let Opcode = 0b11101;156 let funct = 0b00101;157 158 let Inst{10-5} = Code;159 let Inst{4-0} = funct;160}161 162//163// For conversion functions.164//165class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,166 string asmstr, list<dag> pattern, InstrItinClass itin>:167 MipsInst16<outs, ins, asmstr, pattern, itin>168{169 bits<3> rx;170 bits<3> subfunct;171 bits<5> funct;172 173 let Opcode = 0b11101; // RR174 let funct = _funct;175 let subfunct = _subfunct;176 177 let Inst{10-8} = rx;178 let Inst{7-5} = subfunct;179 let Inst{4-0} = funct;180}181 182//183// just used for breakpoint (hardware and software) instructions.184//185class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,186 list<dag> pattern, InstrItinClass itin>:187 MipsInst16<outs, ins, asmstr, pattern, itin>188{189 bits<6> _code; // code is a keyword in tablegen190 bits<5> funct;191 192 let Opcode = 0b11101; // RR193 let funct = _funct;194 195 let Inst{10-5} = _code;196 let Inst{4-0} = funct;197}198 199//200// J(AL)R(C) subformat201//202class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,203 dag outs, dag ins, string asmstr,204 list<dag> pattern, InstrItinClass itin>:205 MipsInst16<outs, ins, asmstr, pattern, itin>206{207 bits<3> rx;208 bits<1> nd;209 bits<1> l;210 bits<1> ra;211 212 let nd = _nd;213 let l = _l;214 let ra = r_a;215 216 let Opcode = 0b11101;217 218 let Inst{10-8} = rx;219 let Inst{7} = nd;220 let Inst{6} = l;221 let Inst{5} = ra;222 let Inst{4-0} = 0;223}224 225//===----------------------------------------------------------------------===//226// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>227//===----------------------------------------------------------------------===//228 229class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,230 list<dag> pattern, InstrItinClass itin>:231 MipsInst16<outs, ins, asmstr, pattern, itin>232{233 bits<3> rx;234 bits<3> ry;235 bits<5> imm5;236 237 let Opcode = op;238 239 240 let Inst{10-8} = rx;241 let Inst{7-5} = ry;242 let Inst{4-0} = imm5;243}244 245//===----------------------------------------------------------------------===//246// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>247//===----------------------------------------------------------------------===//248 249class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,250 list<dag> pattern, InstrItinClass itin>:251 MipsInst16<outs, ins, asmstr, pattern, itin>252{253 bits<3> rx;254 bits<3> ry;255 bits<3> rz;256 bits<2> f;257 258 let Opcode = 0b11100;259 let f = _f;260 261 let Inst{10-8} = rx;262 let Inst{7-5} = ry;263 let Inst{4-2} = rz;264 let Inst{1-0} = f;265}266 267//===----------------------------------------------------------------------===//268// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>269//===----------------------------------------------------------------------===//270 271class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,272 list<dag> pattern, InstrItinClass itin>:273 MipsInst16<outs, ins, asmstr, pattern, itin>274{275 bits<3> rx;276 bits<3> ry;277 bits<1> f;278 bits<4> imm4;279 280 let Opcode = 0b01000;281 let f = _f;282 283 let Inst{10-8} = rx;284 let Inst{7-5} = ry;285 let Inst{4} = f;286 let Inst{3-0} = imm4;287}288 289//===----------------------------------------------------------------------===//290// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>291//===----------------------------------------------------------------------===//292 293class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,294 list<dag> pattern, InstrItinClass itin>:295 MipsInst16<outs, ins, asmstr, pattern, itin>296{297 bits<3> rx;298 bits<3> ry;299 bits<3> sa;300 bits<2> f;301 302 let Opcode = 0b00110;303 let f = _f;304 305 let Inst{10-8} = rx;306 let Inst{7-5} = ry;307 let Inst{4-2} = sa;308 let Inst{1-0} = f;309}310 311//===----------------------------------------------------------------------===//312// Format i8 instruction class in Mips : <|opcode|funct|imm8>313//===----------------------------------------------------------------------===//314 315class FI816<bits<3> _func, dag outs, dag ins, string asmstr,316 list<dag> pattern, InstrItinClass itin>:317 MipsInst16<outs, ins, asmstr, pattern, itin>318{319 bits<3> func;320 bits<8> imm8;321 322 let Opcode = 0b01100;323 let func = _func;324 325 let Inst{10-8} = func;326 let Inst{7-0} = imm8;327}328 329//===----------------------------------------------------------------------===//330// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>331//===----------------------------------------------------------------------===//332 333class FI8_MOVR3216<dag outs, dag ins, string asmstr,334 list<dag> pattern, InstrItinClass itin>:335 MipsInst16<outs, ins, asmstr, pattern, itin>336{337 // FIXME: this seems wrong? 'ry' should be 3 bits, and 'r32' 5?338 bits<4> ry;339 bits<4> r32;340 341 let Opcode = 0b01100;342 343 let Inst{10-8} = 0b111;344 let Inst{7-4} = ry;345 let Inst{3-0} = r32;346 347}348 349 350 351//===----------------------------------------------------------------------===//352// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>353//===----------------------------------------------------------------------===//354 355class FI8_MOV32R16<dag outs, dag ins, string asmstr,356 list<dag> pattern, InstrItinClass itin>:357 MipsInst16<outs, ins, asmstr, pattern, itin>358{359 360 bits<3> func;361 bits<5> r32;362 bits<3> rz;363 364 365 let Opcode = 0b01100;366 367 let Inst{10-8} = 0b101;368 let Inst{7-5} = r32{2-0};369 let Inst{4-3} = r32{4-3};370 let Inst{2-0} = rz;371 372}373 374//===----------------------------------------------------------------------===//375// Format i8_SVRS instruction class in Mips :376// <|opcode|svrs|s|ra|s0|s1|framesize>377//===----------------------------------------------------------------------===//378 379class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,380 list<dag> pattern, InstrItinClass itin>:381 MipsInst16<outs, ins, asmstr, pattern, itin>382{383 bits<1> s;384 bits<1> ra = 0;385 bits<1> s0 = 0;386 bits<1> s1 = 0;387 bits<4> framesize = 0;388 389 let s =_s;390 let Opcode = 0b01100;391 392 let Inst{10-8} = 0b100;393 let Inst{7} = s;394 let Inst{6} = ra;395 let Inst{5} = s0;396 let Inst{4} = s1;397 let Inst{3-0} = framesize;398 399}400 401//===----------------------------------------------------------------------===//402// Format JAL instruction class in Mips16 :403// <|opcode|svrs|s|ra|s0|s1|framesize>404//===----------------------------------------------------------------------===//405 406class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,407 list<dag> pattern, InstrItinClass itin>:408 MipsInst16_32<outs, ins, asmstr, pattern, itin>409{410 bits<1> X;411 bits<26> imm26;412 413 414 let X = _X;415 416 let Inst{31-27} = 0b00011;417 let Inst{26} = X;418 let Inst{25-21} = imm26{20-16};419 let Inst{20-16} = imm26{25-21};420 let Inst{15-0} = imm26{15-0};421 422}423 424//===----------------------------------------------------------------------===//425// Format EXT-I instruction class in Mips16 :426// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>427//===----------------------------------------------------------------------===//428 429class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,430 list<dag> pattern, InstrItinClass itin>:431 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>432{433 bits<16> imm16;434 bits<5> eop;435 436 let eop = _eop;437 438 let Inst{26-21} = imm16{10-5};439 let Inst{20-16} = imm16{15-11};440 let Inst{15-11} = eop;441 let Inst{10-5} = 0;442 let Inst{4-0} = imm16{4-0};443 444}445 446//===----------------------------------------------------------------------===//447// Format ASMACRO instruction class in Mips16 :448// <EXTEND|select|p4|p3|RRR|p2|p1|p0>449//===----------------------------------------------------------------------===//450 451class FASMACRO16<dag outs, dag ins, string asmstr,452 list<dag> pattern, InstrItinClass itin>:453 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>454{455 bits<3> select;456 bits<3> p4;457 bits<5> p3;458 bits<5> RRR = 0b11100;459 bits<3> p2;460 bits<3> p1;461 bits<5> p0;462 463 464 let Inst{26-24} = select;465 let Inst{23-21} = p4;466 let Inst{20-16} = p3;467 let Inst{15-11} = RRR;468 let Inst{10-8} = p2;469 let Inst{7-5} = p1;470 let Inst{4-0} = p0;471 472}473 474 475//===----------------------------------------------------------------------===//476// Format EXT-RI instruction class in Mips16 :477// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>478//===----------------------------------------------------------------------===//479 480class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,481 list<dag> pattern, InstrItinClass itin>:482 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>483{484 bits<16> imm16;485 bits<5> op;486 bits<3> rx;487 488 let op = _op;489 490 let Inst{26-21} = imm16{10-5};491 let Inst{20-16} = imm16{15-11};492 let Inst{15-11} = op;493 let Inst{10-8} = rx;494 let Inst{7-5} = 0;495 let Inst{4-0} = imm16{4-0};496 497}498 499//===----------------------------------------------------------------------===//500// Format EXT-RRI instruction class in Mips16 :501// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>502//===----------------------------------------------------------------------===//503 504class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,505 list<dag> pattern, InstrItinClass itin>:506 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>507{508 bits<5> op;509 bits<16> imm16;510 bits<3> rx;511 bits<3> ry;512 513 let op=_op;514 515 let Inst{26-21} = imm16{10-5};516 let Inst{20-16} = imm16{15-11};517 let Inst{15-11} = op;518 let Inst{10-8} = rx;519 let Inst{7-5} = ry;520 let Inst{4-0} = imm16{4-0};521 522}523 524//===----------------------------------------------------------------------===//525// Format EXT-RRI-A instruction class in Mips16 :526// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>527//===----------------------------------------------------------------------===//528 529class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,530 list<dag> pattern, InstrItinClass itin>:531 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>532{533 bits<15> imm15;534 bits<3> rx;535 bits<3> ry;536 bits<1> f;537 538 let f = _f;539 540 let Inst{26-20} = imm15{10-4};541 let Inst{19-16} = imm15{14-11};542 let Inst{15-11} = 0b01000;543 let Inst{10-8} = rx;544 let Inst{7-5} = ry;545 let Inst{4} = f;546 let Inst{3-0} = imm15{3-0};547 548}549 550//===----------------------------------------------------------------------===//551// Format EXT-SHIFT instruction class in Mips16 :552// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>553//===----------------------------------------------------------------------===//554 555class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,556 list<dag> pattern, InstrItinClass itin>:557 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>558{559 bits<6> sa6;560 bits<3> rx;561 bits<3> ry;562 bits<2> f;563 564 let f = _f;565 566 let Inst{26-22} = sa6{4-0};567 let Inst{21} = sa6{5};568 let Inst{20-16} = 0;569 let Inst{15-11} = 0b00110;570 let Inst{10-8} = rx;571 let Inst{7-5} = ry;572 let Inst{4-2} = 0;573 let Inst{1-0} = f;574 575}576 577//===----------------------------------------------------------------------===//578// Format EXT-I8 instruction class in Mips16 :579// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>580//===----------------------------------------------------------------------===//581 582class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,583 list<dag> pattern, InstrItinClass itin>:584 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>585{586 bits<16> imm16;587 bits<5> I8;588 bits<3> funct;589 590 let funct = _funct;591 let I8 = 0b00110;592 593 let Inst{26-21} = imm16{10-5};594 let Inst{20-16} = imm16{15-11};595 let Inst{15-11} = I8;596 let Inst{10-8} = funct;597 let Inst{7-5} = 0;598 let Inst{4-0} = imm16{4-0};599 600}601 602//===----------------------------------------------------------------------===//603// Format EXT-I8_SVRS instruction class in Mips16 :604// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>605//===----------------------------------------------------------------------===//606 607class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,608 list<dag> pattern, InstrItinClass itin>:609 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>610{611 bits<3> xsregs =0;612 bits<8> framesize =0;613 bits<3> aregs =0;614 bits<5> I8 = 0b01100;615 bits<3> SVRS = 0b100;616 bits<1> s;617 bits<1> ra = 0;618 bits<1> s0 = 0;619 bits<1> s1 = 0;620 621 let s= s_;622 623 let Inst{26-24} = xsregs;624 let Inst{23-20} = framesize{7-4};625 let Inst{19} = 0;626 let Inst{18-16} = aregs;627 let Inst{15-11} = I8;628 let Inst{10-8} = SVRS;629 let Inst{7} = s;630 let Inst{6} = ra;631 let Inst{5} = s0;632 let Inst{4} = s1;633 let Inst{3-0} = framesize{3-0};634 635 636}637 638