485 lines · cpp
1//===- Mips16InstrInfo.cpp - Mips16 Instruction Information ---------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the Mips16 implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#include "Mips16InstrInfo.h"14#include "llvm/ADT/BitVector.h"15#include "llvm/CodeGen/MachineBasicBlock.h"16#include "llvm/CodeGen/MachineFrameInfo.h"17#include "llvm/CodeGen/MachineFunction.h"18#include "llvm/CodeGen/MachineInstr.h"19#include "llvm/CodeGen/MachineInstrBuilder.h"20#include "llvm/CodeGen/MachineMemOperand.h"21#include "llvm/CodeGen/MachineOperand.h"22#include "llvm/CodeGen/RegisterScavenging.h"23#include "llvm/CodeGen/TargetRegisterInfo.h"24#include "llvm/IR/DebugLoc.h"25#include "llvm/Support/ErrorHandling.h"26#include "llvm/Support/MathExtras.h"27#include <cassert>28#include <cctype>29#include <cstdint>30#include <cstdlib>31#include <cstring>32#include <iterator>33#include <vector>34 35using namespace llvm;36 37#define DEBUG_TYPE "mips16-instrinfo"38 39Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)40 : MipsInstrInfo(STI, RI, Mips::Bimm16), RI(STI) {}41 42/// isLoadFromStackSlot - If the specified machine instruction is a direct43/// load from a stack slot, return the virtual or physical register number of44/// the destination along with the FrameIndex of the loaded stack slot. If45/// not, return 0. This predicate must return 0 if the instruction has46/// any side effects other than loading from the stack slot.47Register Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,48 int &FrameIndex) const {49 return 0;50}51 52/// isStoreToStackSlot - If the specified machine instruction is a direct53/// store to a stack slot, return the virtual or physical register number of54/// the source reg along with the FrameIndex of the loaded stack slot. If55/// not, return 0. This predicate must return 0 if the instruction has56/// any side effects other than storing to the stack slot.57Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,58 int &FrameIndex) const {59 return 0;60}61 62void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,63 MachineBasicBlock::iterator I,64 const DebugLoc &DL, Register DestReg,65 Register SrcReg, bool KillSrc,66 bool RenamableDest, bool RenamableSrc) const {67 unsigned Opc = 0;68 69 if (Mips::CPU16RegsRegClass.contains(DestReg) &&70 Mips::GPR32RegClass.contains(SrcReg))71 Opc = Mips::MoveR3216;72 else if (Mips::GPR32RegClass.contains(DestReg) &&73 Mips::CPU16RegsRegClass.contains(SrcReg))74 Opc = Mips::Move32R16;75 else if ((SrcReg == Mips::HI0) &&76 (Mips::CPU16RegsRegClass.contains(DestReg)))77 Opc = Mips::Mfhi16, SrcReg = 0;78 else if ((SrcReg == Mips::LO0) &&79 (Mips::CPU16RegsRegClass.contains(DestReg)))80 Opc = Mips::Mflo16, SrcReg = 0;81 82 assert(Opc && "Cannot copy registers");83 84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));85 86 if (DestReg)87 MIB.addReg(DestReg, RegState::Define);88 89 if (SrcReg)90 MIB.addReg(SrcReg, getKillRegState(KillSrc));91}92 93std::optional<DestSourcePair>94Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {95 if (MI.isMoveReg())96 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};97 return std::nullopt;98}99 100void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,101 MachineBasicBlock::iterator I,102 Register SrcReg, bool isKill, int FI,103 const TargetRegisterClass *RC,104 int64_t Offset,105 MachineInstr::MIFlag Flags) const {106 DebugLoc DL;107 if (I != MBB.end()) DL = I->getDebugLoc();108 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);109 unsigned Opc = 0;110 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))111 Opc = Mips::SwRxSpImmX16;112 assert(Opc && "Register class not handled!");113 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).114 addFrameIndex(FI).addImm(Offset)115 .addMemOperand(MMO);116}117 118void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,119 MachineBasicBlock::iterator I,120 Register DestReg, int FI,121 const TargetRegisterClass *RC,122 int64_t Offset,123 MachineInstr::MIFlag Flags) const {124 DebugLoc DL;125 if (I != MBB.end()) DL = I->getDebugLoc();126 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);127 unsigned Opc = 0;128 129 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))130 Opc = Mips::LwRxSpImmX16;131 assert(Opc && "Register class not handled!");132 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)133 .addMemOperand(MMO);134}135 136bool Mips16InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {137 MachineBasicBlock &MBB = *MI.getParent();138 switch (MI.getDesc().getOpcode()) {139 default:140 return false;141 case Mips::RetRA16:142 ExpandRetRA16(MBB, MI, Mips::JrcRa16);143 break;144 }145 146 MBB.erase(MI.getIterator());147 return true;148}149 150/// GetOppositeBranchOpc - Return the inverse of the specified151/// opcode, e.g. turning BEQ to BNE.152unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {153 switch (Opc) {154 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;155 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;156 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;157 case Mips::BnezRxImm16: return Mips::BeqzRxImm16;158 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;159 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;160 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;161 case Mips::Btnez16: return Mips::Bteqz16;162 case Mips::BtnezX16: return Mips::BteqzX16;163 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;164 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;165 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;166 case Mips::Bteqz16: return Mips::Btnez16;167 case Mips::BteqzX16: return Mips::BtnezX16;168 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;169 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;170 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;171 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;172 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;173 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;174 }175 llvm_unreachable("Illegal opcode!");176}177 178static void addSaveRestoreRegs(MachineInstrBuilder &MIB,179 ArrayRef<CalleeSavedInfo> CSI,180 unsigned Flags = 0) {181 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {182 // Add the callee-saved register as live-in. Do not add if the register is183 // RA and return address is taken, because it has already been added in184 // method MipsTargetLowering::lowerRETURNADDR.185 // It's killed at the spill, unless the register is RA and return address186 // is taken.187 Register Reg = CSI[e-i-1].getReg();188 switch (Reg) {189 case Mips::RA:190 case Mips::S0:191 case Mips::S1:192 MIB.addReg(Reg, Flags);193 break;194 case Mips::S2:195 break;196 default:197 llvm_unreachable("unexpected mips16 callee saved register");198 199 }200 }201}202 203// Adjust SP by FrameSize bytes. Save RA, S0, S1204void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,205 MachineBasicBlock &MBB,206 MachineBasicBlock::iterator I) const {207 DebugLoc DL;208 MachineFunction &MF = *MBB.getParent();209 MachineFrameInfo &MFI = MF.getFrameInfo();210 const BitVector Reserved = RI.getReservedRegs(MF);211 bool SaveS2 = Reserved[Mips::S2];212 MachineInstrBuilder MIB;213 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;214 MIB = BuildMI(MBB, I, DL, get(Opc));215 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();216 addSaveRestoreRegs(MIB, CSI);217 if (SaveS2)218 MIB.addReg(Mips::S2);219 if (isUInt<11>(FrameSize))220 MIB.addImm(FrameSize);221 else {222 int Base = 2040; // should create template function like isUInt that223 // returns largest possible n bit unsigned integer224 int64_t Remainder = FrameSize - Base;225 MIB.addImm(Base);226 if (isInt<16>(-Remainder))227 BuildAddiuSpImm(MBB, I, -Remainder);228 else229 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);230 }231}232 233// Adjust SP by FrameSize bytes. Restore RA, S0, S1234void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,235 MachineBasicBlock &MBB,236 MachineBasicBlock::iterator I) const {237 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();238 MachineFunction *MF = MBB.getParent();239 MachineFrameInfo &MFI = MF->getFrameInfo();240 const BitVector Reserved = RI.getReservedRegs(*MF);241 bool SaveS2 = Reserved[Mips::S2];242 MachineInstrBuilder MIB;243 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?244 Mips::Restore16:Mips::RestoreX16;245 246 if (!isUInt<11>(FrameSize)) {247 unsigned Base = 2040;248 int64_t Remainder = FrameSize - Base;249 FrameSize = Base; // should create template function like isUInt that250 // returns largest possible n bit unsigned integer251 252 if (isInt<16>(Remainder))253 BuildAddiuSpImm(MBB, I, Remainder);254 else255 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);256 }257 MIB = BuildMI(MBB, I, DL, get(Opc));258 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();259 addSaveRestoreRegs(MIB, CSI, RegState::Define);260 if (SaveS2)261 MIB.addReg(Mips::S2, RegState::Define);262 MIB.addImm(FrameSize);263}264 265// Adjust SP by Amount bytes where bytes can be up to 32bit number.266// This can only be called at times that we know that there is at least one free267// register.268// This is clearly safe at prologue and epilogue.269void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,270 MachineBasicBlock &MBB,271 MachineBasicBlock::iterator I,272 unsigned Reg1, unsigned Reg2) const {273 DebugLoc DL;274 //275 // li reg1, constant276 // move reg2, sp277 // add reg1, reg1, reg2278 // move sp, reg1279 //280 //281 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);282 MIB1.addImm(Amount).addImm(-1);283 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);284 MIB2.addReg(Mips::SP, RegState::Kill);285 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);286 MIB3.addReg(Reg1);287 MIB3.addReg(Reg2, RegState::Kill);288 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),289 Mips::SP);290 MIB4.addReg(Reg1, RegState::Kill);291}292 293void Mips16InstrInfo::adjustStackPtrBigUnrestricted(294 unsigned SP, int64_t Amount, MachineBasicBlock &MBB,295 MachineBasicBlock::iterator I) const {296 llvm_unreachable("adjust stack pointer amount exceeded");297}298 299/// Adjust SP by Amount bytes.300void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,301 MachineBasicBlock &MBB,302 MachineBasicBlock::iterator I) const {303 if (Amount == 0)304 return;305 306 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>307 BuildAddiuSpImm(MBB, I, Amount);308 else309 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);310}311 312/// This function generates the sequence of instructions needed to get the313/// result of adding register REG and immediate IMM.314unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,315 MachineBasicBlock &MBB,316 MachineBasicBlock::iterator II,317 const DebugLoc &DL,318 unsigned &NewImm) const {319 //320 // given original instruction is:321 // Instr rx, T[offset] where offset is too big.322 //323 // lo = offset & 0xFFFF324 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;325 //326 // let T = temporary register327 // li T, hi328 // shl T, 16329 // add T, Rx, T330 //331 RegScavenger rs;332 int32_t lo = Imm & 0xFFFF;333 NewImm = lo;334 int Reg =0;335 int SpReg = 0;336 337 rs.enterBasicBlockEnd(MBB);338 rs.backward(std::next(II));339 //340 // We need to know which registers can be used, in the case where there341 // are not enough free registers. We exclude all registers that342 // are used in the instruction that we are helping.343 // // Consider all allocatable registers in the register class initially344 BitVector Candidates =345 RI.getAllocatableSet346 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);347 // Exclude all the registers being used by the instruction.348 for (MachineOperand &MO : II->operands()) {349 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&350 !MO.getReg().isVirtual())351 Candidates.reset(MO.getReg());352 }353 354 // If the same register was used and defined in an instruction, then355 // it will not be in the list of candidates.356 //357 // we need to analyze the instruction that we are helping.358 // we need to know if it defines register x but register x is not359 // present as an operand of the instruction. this tells360 // whether the register is live before the instruction. if it's not361 // then we don't need to save it in case there are no free registers.362 int DefReg = 0;363 for (MachineOperand &MO : II->operands()) {364 if (MO.isReg() && MO.isDef()) {365 DefReg = MO.getReg();366 break;367 }368 }369 370 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);371 Available &= Candidates;372 //373 // we use T0 for the first register, if we need to save something away.374 // we use T1 for the second register, if we need to save something away.375 //376 unsigned FirstRegSaved =0, SecondRegSaved=0;377 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;378 379 Reg = Available.find_first();380 381 if (Reg == -1) {382 Reg = Candidates.find_first();383 Candidates.reset(Reg);384 if (DefReg != Reg) {385 FirstRegSaved = Reg;386 FirstRegSavedTo = Mips::T0;387 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);388 }389 }390 else391 Available.reset(Reg);392 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);393 NewImm = 0;394 if (FrameReg == Mips::SP) {395 SpReg = Available.find_first();396 if (SpReg == -1) {397 SpReg = Candidates.find_first();398 // Candidates.reset(SpReg); // not really needed399 if (DefReg!= SpReg) {400 SecondRegSaved = SpReg;401 SecondRegSavedTo = Mips::T1;402 }403 if (SecondRegSaved)404 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);405 } else {406 Available.reset(SpReg);407 }408 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);409 BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)410 .addReg(SpReg, RegState::Kill)411 .addReg(Reg);412 }413 else414 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)415 .addReg(Reg, RegState::Kill);416 if (FirstRegSaved || SecondRegSaved) {417 II = std::next(II);418 if (FirstRegSaved)419 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);420 if (SecondRegSaved)421 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);422 }423 return Reg;424}425 426unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {427 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||428 Opc == Mips::Bimm16 ||429 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||430 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||431 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||432 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||433 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||434 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||435 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||436 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||437 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||438 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;439}440 441void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,442 MachineBasicBlock::iterator I,443 unsigned Opc) const {444 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));445}446 447const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {448 if (validSpImm8(Imm))449 return get(Mips::AddiuSpImm16);450 else451 return get(Mips::AddiuSpImmX16);452}453 454void Mips16InstrInfo::BuildAddiuSpImm455 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {456 DebugLoc DL;457 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);458}459 460const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {461 return new Mips16InstrInfo(STI);462}463 464bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,465 int64_t Amount) {466 switch (Opcode) {467 case Mips::LbRxRyOffMemX16:468 case Mips::LbuRxRyOffMemX16:469 case Mips::LhRxRyOffMemX16:470 case Mips::LhuRxRyOffMemX16:471 case Mips::SbRxRyOffMemX16:472 case Mips::ShRxRyOffMemX16:473 case Mips::LwRxRyOffMemX16:474 case Mips::SwRxRyOffMemX16:475 case Mips::SwRxSpImmX16:476 case Mips::LwRxSpImmX16:477 return isInt<16>(Amount);478 case Mips::AddiuRxRyOffMemX16:479 if ((Reg == Mips::PC) || (Reg == Mips::SP))480 return isInt<16>(Amount);481 return isInt<15>(Amount);482 }483 llvm_unreachable("unexpected Opcode in validImmediate");484}485