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1//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes Mips32r6 instructions.10//11//===----------------------------------------------------------------------===//12 13include "Mips32r6InstrFormats.td"14 15//===----------------------------------------------------------------------===//16//17// Mips profiles and nodes18//19//===----------------------------------------------------------------------===//20 21def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>,22 SDTCisSameAs<0,2>,23 SDTCisSameAs<2,3>]>;24 25def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>;26 27//===----------------------------------------------------------------------===//28//29// Mips Operands30//31//===----------------------------------------------------------------------===//32 33// Notes about removals/changes from MIPS32r6:34// Reencoded: jr -> jalr35// Reencoded: jr.hb -> jalr.hb36 37def brtarget21 : Operand<OtherVT> {38 let EncoderMethod = "getBranchTarget21OpValue";39 let OperandType = "OPERAND_PCREL";40 let DecoderMethod = "DecodeBranchTarget21";41 let ParserMatchClass = MipsJumpTargetAsmOperand;42 let PrintMethod = "printBranchOperand";43}44 45def brtarget26 : Operand<OtherVT> {46 let EncoderMethod = "getBranchTarget26OpValue";47 let OperandType = "OPERAND_PCREL";48 let DecoderMethod = "DecodeBranchTarget26";49 let ParserMatchClass = MipsJumpTargetAsmOperand;50 let PrintMethod = "printBranchOperand";51}52 53def jmpoffset16 : Operand<OtherVT> {54 let EncoderMethod = "getJumpOffset16OpValue";55 let ParserMatchClass = MipsJumpTargetAsmOperand;56}57 58def calloffset16 : Operand<iPTR> {59 let EncoderMethod = "getJumpOffset16OpValue";60 let ParserMatchClass = MipsJumpTargetAsmOperand;61}62 63//===----------------------------------------------------------------------===//64//65// Instruction Encodings66//67//===----------------------------------------------------------------------===//68 69class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;70class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;71class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;72class AUI_ENC : AUI_FM;73class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;74 75class BAL_ENC : BAL_FM;76class NAL_ENC : NAL_FM;77class BALC_ENC : BRANCH_OFF26_FM<0b111010>;78class BC_ENC : BRANCH_OFF26_FM<0b110010>;79class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,80 DecodeDisambiguates<"AddiGroupBranch">;81class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,82 DecodeDisambiguatedBy<"DaddiGroupBranch">;83class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,84 DecodeDisambiguates<"DaddiGroupBranch">;85class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,86 DecodeDisambiguatedBy<"DaddiGroupBranch">;87 88class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,89 DecodeDisambiguates<"BgtzlGroupBranch">;90class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,91 DecodeDisambiguatedBy<"BlezlGroupBranch">;92class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,93 DecodeDisambiguatedBy<"BlezGroupBranch">;94class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,95 DecodeDisambiguates<"BlezlGroupBranch">;96class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,97 DecodeDisambiguatedBy<"BgtzGroupBranch">;98 99class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,100 DecodeDisambiguatedBy<"BgtzlGroupBranch">;101class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,102 DecodeDisambiguatedBy<"BgtzGroupBranch">;103 104class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,105 DecodeDisambiguatedBy<"BlezlGroupBranch">;106class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,107 DecodeDisambiguates<"BgtzGroupBranch">;108class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,109 DecodeDisambiguatedBy<"BgtzlGroupBranch">;110 111class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;112class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,113 DecodeDisambiguates<"BlezGroupBranch">;114class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;115 116class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;117class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;118class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;119class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;120 121class DVP_ENC : COP0_EVP_DVP_FM<0b1>;122class EVP_ENC : COP0_EVP_DVP_FM<0b0>;123 124class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;125class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;126class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;127class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;128class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,129 DecodeDisambiguatedBy<"BlezGroupBranch">;130class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,131 DecodeDisambiguatedBy<"DaddiGroupBranch">;132class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,133 DecodeDisambiguatedBy<"AddiGroupBranch">;134class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;135class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;136class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;137class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;138class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;139class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;140class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;141class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;142 143class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;144class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;145class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;146class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;147 148class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;149class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;150 151class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;152class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;153 154class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;155 156class MAX_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;157class MAX_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;158class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;159class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;160 161class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;162class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;163class MINA_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;164class MINA_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;165 166class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;167class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;168class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;169class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;170 171class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;172class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;173class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;174class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;175 176class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;177class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;178 179class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;180class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;181class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;182class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;183 184class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;185 186class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;187class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;188 189class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;190class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;191 192class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;193 194class CRC32B_ENC : SPECIAL3_2R_SZ_CRC<0,0>;195class CRC32H_ENC : SPECIAL3_2R_SZ_CRC<1,0>;196class CRC32W_ENC : SPECIAL3_2R_SZ_CRC<2,0>;197class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;198class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;199class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;200 201class GINVI_ENC : SPECIAL3_GINV<0>;202class GINVT_ENC : SPECIAL3_GINV<2>;203 204class SIGRIE_ENC : SIGRIE_FM;205 206//===----------------------------------------------------------------------===//207//208// Instruction Multiclasses209//210//===----------------------------------------------------------------------===//211 212class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,213 RegisterOperand FGROpnd,214 InstrItinClass Itin,215 SDPatternOperator Op = null_frag> {216 dag OutOperandList = (outs FGRCCOpnd:$fd);217 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);218 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");219 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];220 bit isCTI = 1;221 InstrItinClass Itinerary = Itin;222}223 224multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,225 RegisterOperand FGROpnd, InstrItinClass Itin>{226 let AdditionalPredicates = [NotInMicroMips] in {227 def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,228 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>,229 MipsR6Arch<!strconcat("cmp.af.", Typestr)>,230 ISA_MIPS32R6, HARDFLOAT;231 def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,232 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>,233 MipsR6Arch<!strconcat("cmp.un.", Typestr)>,234 ISA_MIPS32R6, HARDFLOAT;235 def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,236 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin,237 setoeq>,238 MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,239 ISA_MIPS32R6, HARDFLOAT;240 def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,241 FIELD_CMP_COND_UEQ>,242 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin,243 setueq>,244 MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,245 ISA_MIPS32R6, HARDFLOAT;246 def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,247 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin,248 setolt>,249 MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,250 ISA_MIPS32R6, HARDFLOAT;251 def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,252 FIELD_CMP_COND_ULT>,253 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin,254 setult>,255 MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,256 ISA_MIPS32R6, HARDFLOAT;257 def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,258 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin,259 setole>,260 MipsR6Arch<!strconcat("cmp.le.", Typestr)>,261 ISA_MIPS32R6, HARDFLOAT;262 def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,263 FIELD_CMP_COND_ULE>,264 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin,265 setule>,266 MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,267 ISA_MIPS32R6, HARDFLOAT;268 def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,269 FIELD_CMP_COND_SAF>,270 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>,271 MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,272 ISA_MIPS32R6, HARDFLOAT;273 def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,274 FIELD_CMP_COND_SUN>,275 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>,276 MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,277 ISA_MIPS32R6, HARDFLOAT;278 def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,279 FIELD_CMP_COND_SEQ>,280 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>,281 MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,282 ISA_MIPS32R6, HARDFLOAT;283 def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,284 FIELD_CMP_COND_SUEQ>,285 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>,286 MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,287 ISA_MIPS32R6, HARDFLOAT;288 def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,289 FIELD_CMP_COND_SLT>,290 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>,291 MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,292 ISA_MIPS32R6, HARDFLOAT;293 def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,294 FIELD_CMP_COND_SULT>,295 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>,296 MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,297 ISA_MIPS32R6, HARDFLOAT;298 def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,299 FIELD_CMP_COND_SLE>,300 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>,301 MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,302 ISA_MIPS32R6, HARDFLOAT;303 def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,304 FIELD_CMP_COND_SULE>,305 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>,306 MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,307 ISA_MIPS32R6, HARDFLOAT;308 }309}310 311//===----------------------------------------------------------------------===//312//313// Instruction Descriptions314//315//===----------------------------------------------------------------------===//316 317class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,318 Operand ImmOpnd, InstrItinClass itin>319 : MipsR6Arch<instr_asm> {320 dag OutOperandList = (outs GPROpnd:$rs);321 dag InOperandList = (ins ImmOpnd:$imm);322 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");323 list<dag> Pattern = [];324 InstrItinClass Itinerary = itin;325}326 327class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,328 II_ADDIUPC>;329class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;330 331class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,332 Operand ImmOpnd, InstrItinClass itin>333 : MipsR6Arch<instr_asm> {334 dag OutOperandList = (outs GPROpnd:$rd);335 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);336 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");337 list<dag> Pattern = [];338 InstrItinClass Itinerary = itin;339}340 341class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;342 343class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,344 InstrItinClass itin = NoItinerary>345 : MipsR6Arch<instr_asm> {346 dag OutOperandList = (outs GPROpnd:$rs);347 dag InOperandList = (ins simm16:$imm);348 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");349 list<dag> Pattern = [];350 InstrItinClass Itinerary = itin;351}352 353class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;354class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;355 356class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,357 InstrItinClass itin = NoItinerary>358 : MipsR6Arch<instr_asm> {359 dag OutOperandList = (outs GPROpnd:$rt);360 dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);361 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");362 list<dag> Pattern = [];363 InstrItinClass Itinerary = itin;364}365 366class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;367 368class BRANCH_DESC_BASE {369 bit isBranch = 1;370 bit isTerminator = 1;371 bit hasDelaySlot = 0;372 bit isCTI = 1;373}374 375class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,376 MipsR6Arch<instr_asm> {377 dag InOperandList = (ins opnd:$offset);378 dag OutOperandList = (outs);379 string AsmString = !strconcat(instr_asm, "\t$offset");380 bit isBarrier = 1;381 InstrItinClass Itinerary = II_BC;382 bit isCTI = 1;383}384 385class NAL_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE,386 MipsR6Arch<instr_asm> {387 string AsmString = instr_asm;388 bit isCTI = 1;389}390 391class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,392 RegisterOperand GPROpnd> : BRANCH_DESC_BASE,393 MipsR6Arch<instr_asm> {394 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);395 dag OutOperandList = (outs);396 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");397 list<Register> Defs = [AT];398 InstrItinClass Itinerary = II_BCCC;399 bit hasForbiddenSlot = 1;400 bit isCTI = 1;401}402 403class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,404 RegisterOperand GPROpnd>405 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {406 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);407 dag OutOperandList = (outs);408 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");409 list<Register> Defs = [AT];410 InstrItinClass Itinerary = II_BCCZC;411 bit hasForbiddenSlot = 1;412 bit isCTI = 1;413}414 415class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,416 RegisterOperand GPROpnd>417 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {418 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);419 dag OutOperandList = (outs);420 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");421 list<Register> Defs = [AT];422 InstrItinClass Itinerary = II_BCCZC;423 bit hasForbiddenSlot = 1;424 bit isCTI = 1;425}426 427class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {428 bit isCall = 1;429 bit hasDelaySlot = 1;430 list<Register> Defs = [RA];431 bit isCTI = 1;432}433 434class NAL_DESC : NAL_DESC_BASE<"nal"> {435 bit hasDelaySlot = 1;436 list<Register> Defs = [RA];437 bit isCTI = 1;438}439 440class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {441 bit isCall = 1;442 list<Register> Defs = [RA];443 InstrItinClass Itinerary = II_BALC;444 bit isCTI = 1;445}446 447class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;448class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;449class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;450class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;451class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;452 453class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;454class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;455 456class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;457class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;458 459class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;460class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;461 462class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;463class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;464 465class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {466 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);467 dag OutOperandList = (outs);468 string AsmString = instr_asm;469 bit hasDelaySlot = 1;470 InstrItinClass Itinerary = II_BC1CCZ;471}472 473class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;474class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;475 476class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {477 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);478 dag OutOperandList = (outs);479 string AsmString = instr_asm;480 bit hasDelaySlot = 1;481 bit isCTI = 1;482 InstrItinClass Itinerary = II_BC2CCZ;483}484 485class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;486class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;487 488class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;489class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;490 491class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,492 RegisterOperand GPROpnd,493 InstrItinClass itin = NoItinerary>494 : MipsR6Arch<opstr> {495 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);496 string AsmString = !strconcat(opstr, "\t$rt, $offset");497 list<dag> Pattern = [];498 bit hasDelaySlot = 0;499 InstrItinClass Itinerary = itin;500 bit isCTI = 1;501 bit isBranch = 1;502 bit isIndirectBranch = 1;503}504 505class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,506 GPR32Opnd, II_JIALC> {507 bit isCall = 1;508 list<Register> Defs = [RA];509}510 511class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,512 GPR32Opnd, II_JIALC> {513 bit isBarrier = 1;514 bit isTerminator = 1;515 list<Register> Defs = [AT];516}517 518class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {519 bit isBranch = 1;520 bit isIndirectBranch = 1;521 bit hasDelaySlot = 1;522 bit isTerminator=1;523 bit isBarrier=1;524 bit isCTI = 1;525 InstrItinClass Itinerary = II_JR_HB;526}527 528class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,529 InstrItinClass itin>530 : MipsR6Arch<instr_asm> {531 dag OutOperandList = (outs GPROpnd:$rd);532 dag InOperandList = (ins GPROpnd:$rt);533 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");534 list<dag> Pattern = [];535 InstrItinClass Itinerary = itin;536}537 538class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;539 540class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,541 InstrItinClass itin,542 SDPatternOperator Op=null_frag>543 : MipsR6Arch<instr_asm> {544 dag OutOperandList = (outs GPROpnd:$rd);545 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);546 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");547 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];548 InstrItinClass Itinerary = itin;549 // This instruction doesn't trap division by zero itself. We must insert550 // teq instructions as well.551 bit usesCustomInserter = 1;552}553 554class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin>555 : MipsR6Arch<instr_asm> {556 dag OutOperandList = (outs GPR32Opnd:$rt);557 dag InOperandList = (ins);558 string AsmString = !strconcat(instr_asm, "\t$rt");559 list<dag> Pattern = [];560 InstrItinClass Itinerary = Itin;561 bit hasUnModeledSideEffects = 1;562}563 564class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;565class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>;566 567class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;568class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;569class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;570class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;571 572class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {573 list<Register> Defs = [RA];574}575 576class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {577 list<Register> Defs = [RA];578}579 580class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {581 list<Register> Defs = [RA];582}583 584class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {585 list<Register> Defs = [RA];586}587 588class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {589 list<Register> Defs = [RA];590}591 592class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {593 list<Register> Defs = [RA];594}595 596class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,597 InstrItinClass itin,598 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {599 dag OutOperandList = (outs GPROpnd:$rd);600 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);601 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");602 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];603 InstrItinClass Itinerary = itin;604}605 606class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;607class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;608class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;609class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;610 611class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,612 InstrItinClass itin> {613 dag OutOperandList = (outs FGROpnd:$fd);614 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);615 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");616 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,617 FGROpnd:$ft,618 FGROpnd:$fs))];619 string Constraints = "$fd_in = $fd";620 InstrItinClass Itinerary = itin;621}622 623class COP1_SEL_D_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,624 InstrItinClass itin> {625 dag OutOperandList = (outs FGROpnd:$fd);626 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);627 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");628 list<dag> Pattern = [(set FGROpnd:$fd, (MipsFSelect FGROpnd:$fd_in,629 FGROpnd:$ft,630 FGROpnd:$fs))];631 string Constraints = "$fd_in = $fd";632 InstrItinClass Itinerary = itin;633}634 635class SEL_D_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,636 MipsR6Arch<"sel.d">;637class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,638 MipsR6Arch<"sel.s">;639 640class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>641 : MipsR6Arch<instr_asm> {642 dag OutOperandList = (outs GPROpnd:$rd);643 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);644 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");645 list<dag> Pattern = [];646 InstrItinClass Itinerary = II_SELCCZ;647}648 649class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;650class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;651 652class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,653 InstrItinClass itin = NoItinerary> {654 dag OutOperandList = (outs FGROpnd:$fd);655 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);656 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");657 list<dag> Pattern = [];658 string Constraints = "$fd_in = $fd";659 InstrItinClass Itinerary = itin;660}661 662class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;663class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;664class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;665class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;666 667class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,668 InstrItinClass itin> {669 dag OutOperandList = (outs FGROpnd:$fd);670 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);671 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");672 list<dag> Pattern = [];673 InstrItinClass Itinerary = itin;674}675 676class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;677class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;678class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;679class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;680 681class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;682class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;683class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;684class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;685 686class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,687 InstrItinClass itin> {688 dag OutOperandList = (outs FGROpnd:$fd);689 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);690 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");691 list<dag> Pattern = [];692 InstrItinClass Itinerary = itin;693}694 695class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,696 MipsR6Arch<"seleqz.s">;697class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,698 MipsR6Arch<"seleqz.d">;699class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,700 MipsR6Arch<"selnez.s">;701class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,702 MipsR6Arch<"selnez.d">;703 704class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,705 InstrItinClass itin> {706 dag OutOperandList = (outs FGROpnd:$fd);707 dag InOperandList = (ins FGROpnd:$fs);708 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");709 list<dag> Pattern = [];710 InstrItinClass Itinerary = itin;711}712 713class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;714class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;715class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;716class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;717 718class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, InstrItinClass itin>719 : MipsR6Arch<instr_asm> {720 dag OutOperandList = (outs);721 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);722 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");723 list<dag> Pattern = [];724 string DecoderMethod = "DecodeCacheeOp_CacheOpR6";725 InstrItinClass Itinerary = itin;726}727 728class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, II_CACHE>;729class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, II_PREF>;730 731class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,732 InstrItinClass itin> {733 dag OutOperandList = (outs COPOpnd:$rt);734 dag InOperandList = (ins mem_simm11:$addr);735 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");736 list<dag> Pattern = [];737 bit mayLoad = 1;738 string DecoderMethod = "DecodeFMemCop2R6";739 InstrItinClass Itinerary = itin;740}741 742class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;743class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;744 745class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,746 InstrItinClass itin> {747 dag OutOperandList = (outs);748 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);749 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");750 list<dag> Pattern = [];751 bit mayStore = 1;752 string DecoderMethod = "DecodeFMemCop2R6";753 InstrItinClass Itinerary = itin;754}755 756class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;757class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;758 759class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,760 Operand ImmOpnd, InstrItinClass itin>761 : MipsR6Arch<instr_asm> {762 dag OutOperandList = (outs GPROpnd:$rd);763 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);764 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");765 list<dag> Pattern = [];766 InstrItinClass Itinerary = itin;767}768 769class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;770 771class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,772 Operand MemOpnd, InstrItinClass itin>773 : MipsR6Arch<instr_asm> {774 dag OutOperandList = (outs GPROpnd:$rt);775 dag InOperandList = (ins MemOpnd:$addr);776 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");777 list<dag> Pattern = [];778 bit mayLoad = 1;779 InstrItinClass Itinerary = itin;780}781 782class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp, II_LL>;783 784class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,785 InstrItinClass itin> {786 dag OutOperandList = (outs GPROpnd:$dst);787 dag InOperandList = (ins GPROpnd:$rt, mem_simm9_exp:$addr);788 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");789 list<dag> Pattern = [];790 bit mayStore = 1;791 string Constraints = "$rt = $dst";792 InstrItinClass Itinerary = itin;793}794 795class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;796 797class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,798 InstrItinClass itin>799 : MipsR6Arch<instr_asm> {800 dag OutOperandList = (outs GPROpnd:$rd);801 dag InOperandList = (ins GPROpnd:$rs);802 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");803 InstrItinClass Itinerary = itin;804}805 806class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,807 InstrItinClass itin> :808 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {809 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];810}811 812class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,813 InstrItinClass itin> :814 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {815 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];816}817 818class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;819class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;820 821class SDBBP_R6_DESC {822 dag OutOperandList = (outs);823 dag InOperandList = (ins uimm20:$code_);824 string AsmString = "sdbbp\t$code_";825 list<dag> Pattern = [];826 bit isCTI = 1;827 InstrItinClass Itinerary = II_SDBBP;828}829 830class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,831 InstrItinClass itin> : MipsR6Arch<instr_asm> {832 dag OutOperandList = (outs GPROpnd:$rd);833 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);834 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");835 list<dag> Pattern = [];836 InstrItinClass Itinerary = itin;837}838 839class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;840class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;841class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;842class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;843class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;844class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;845 846class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,847 InstrItinClass itin> : MipsR6Arch<instr_asm> {848 dag OutOperandList = (outs);849 dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);850 string AsmString = !strconcat(instr_asm, "\t$rs, $type_");851 list<dag> Pattern = [];852 InstrItinClass Itinerary = itin;853 bit hasSideEffects = 1;854}855 856class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {857 bits<2> type_ = 0b00;858 dag InOperandList = (ins GPR32Opnd:$rs);859 string AsmString = "ginvi\t$rs";860}861class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;862 863class SIGRIE_DESC {864 dag OutOperandList = (outs);865 dag InOperandList = (ins uimm16:$code_);866 string AsmString = "sigrie\t$code_";867 list<dag> Pattern = [];868 InstrItinClass Itinerary = II_SIGRIE;869}870 871//===----------------------------------------------------------------------===//872//873// Instruction Definitions874//875//===----------------------------------------------------------------------===//876 877def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;878def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;879def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;880def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;881def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;882def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;883def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;884def NAL : NAL_ENC, NAL_DESC, ISA_MIPS32R6;885 886let AdditionalPredicates = [NotInMicroMips] in {887 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;888 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;889 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;890 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;891 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;892 def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;893 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;894 def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;895 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;896 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;897 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;898 def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;899 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;900 def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;901}902def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;903let AdditionalPredicates = [NotInMicroMips] in {904 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;905 def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;906 def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;907 def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;908 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;909 def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;910 def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;911 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;912 def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;913 def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;914 def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;915 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;916 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;917 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;918}919def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;920def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;921defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;922defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;923let AdditionalPredicates = [NotInMicroMips] in {924 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;925 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;926}927 928def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;929def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6;930 931def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;932def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;933def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;934let AdditionalPredicates = [NotInMicroMips] in {935 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;936 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;937}938def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;939let AdditionalPredicates = [NotInMicroMips] in {940 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;941}942def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;943let AdditionalPredicates = [NotInMicroMips] in {944 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;945 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;946 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;947 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;948 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;949 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;950 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;951 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;952 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;953 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;954 955 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;956 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;957 958 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;959 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;960 961 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;962 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;963 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;964 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;965}966let AdditionalPredicates = [NotInMicroMips] in {967 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;968 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;969 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;970 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;971 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;972 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;973 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;974 def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,975 HARDFLOAT;976 def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6,977 HARDFLOAT;978 def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,979 HARDFLOAT;980 def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,981 HARDFLOAT;982 def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;983 def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;984 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;985 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;986 def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;987}988 989let AdditionalPredicates = [NotInMicroMips] in {990 def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;991 def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;992 def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;993 def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;994 def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;995 def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;996}997 998let AdditionalPredicates = [NotInMicroMips] in {999 def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;1000 def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;1001}1002 1003//===----------------------------------------------------------------------===//1004//1005// Instruction Aliases1006//1007//===----------------------------------------------------------------------===//1008 1009def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;1010def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;1011 1012let AdditionalPredicates = [NotInMicroMips] in {1013def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;1014def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;1015def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,1016 ISA_MIPS32R6, GPR_32;1017}1018 1019def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;1020 1021let AdditionalPredicates = [NotInMicroMips] in {1022def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>,1023 ISA_MIPS32R6, GPR_32;1024}1025 1026def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,1027 GPR32Opnd:$rt)>, ISA_MIPS32R6;1028def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,1029 GPR32Opnd:$rt)>, ISA_MIPS32R6;1030 1031def : MipsInstAlias<"lapc $rd, $imm",1032 (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;1033 1034//===----------------------------------------------------------------------===//1035//1036// Patterns and Pseudo Instructions1037//1038//===----------------------------------------------------------------------===//1039 1040// comparisons supported via another comparison1041multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {1042def : MipsPat<(setone VT:$lhs, VT:$rhs),1043 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;1044def : MipsPat<(seto VT:$lhs, VT:$rhs),1045 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;1046def : MipsPat<(setune VT:$lhs, VT:$rhs),1047 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;1048def : MipsPat<(seteq VT:$lhs, VT:$rhs),1049 (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>;1050def : MipsPat<(setgt VT:$lhs, VT:$rhs),1051 (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>;1052def : MipsPat<(setge VT:$lhs, VT:$rhs),1053 (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>;1054def : MipsPat<(setlt VT:$lhs, VT:$rhs),1055 (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>;1056def : MipsPat<(setle VT:$lhs, VT:$rhs),1057 (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>;1058def : MipsPat<(setne VT:$lhs, VT:$rhs),1059 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;1060}1061 1062let AdditionalPredicates = [NotInMicroMips] in {1063 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;1064 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;1065}1066 1067// i32 selects1068multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,1069 Instruction SLTiOp, Instruction SLTiuOp,1070 Instruction SELEQZOp, Instruction SELNEZOp,1071 SDPatternOperator imm_type, ValueType Opg> {1072// reg, immz1073def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f),1074 (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;1075def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),1076 (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;1077 1078// reg, immZExt16[_64]1079def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),1080 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),1081 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;1082def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),1083 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),1084 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;1085 1086// reg, immSExt16Plus11087def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),1088 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),1089 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;1090def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),1091 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),1092 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;1093 1094def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz),1095 (SELEQZOp RC:$t, RC:$cond)>;1096def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),1097 (SELNEZOp RC:$t, RC:$cond)>;1098def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f),1099 (SELNEZOp RC:$f, RC:$cond)>;1100def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),1101 (SELEQZOp RC:$f, RC:$cond)>;1102}1103 1104let AdditionalPredicates = [NotInMicroMips] in {1105defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,1106 immZExt16, i32>, ISA_MIPS32R6;1107 1108def : MipsPat<(select i32:$cond, i32:$t, i32:$f),1109 (OR (SELNEZ i32:$t, i32:$cond),1110 (SELEQZ i32:$f, i32:$cond))>,1111 ISA_MIPS32R6;1112def : MipsPat<(select i32:$cond, i32:$t, immz),1113 (SELNEZ i32:$t, i32:$cond)>,1114 ISA_MIPS32R6;1115def : MipsPat<(select i32:$cond, immz, i32:$f),1116 (SELEQZ i32:$f, i32:$cond)>,1117 ISA_MIPS32R6;1118}1119 1120// llvm.fmin/fmax operations.1121let AdditionalPredicates = [NotInMicroMips] in {1122 def : MipsPat<(fmaxnum_ieee f32:$lhs, f32:$rhs),1123 (MAX_S f32:$lhs, f32:$rhs)>,1124 ISA_MIPS32R6;1125 def : MipsPat<(fmaxnum f32:$lhs, f32:$rhs),1126 (MAX_S f32:$lhs, f32:$rhs)>,1127 ISA_MIPS32R6;1128 def : MipsPat<(fmaxnum_ieee f64:$lhs, f64:$rhs),1129 (MAX_D f64:$lhs, f64:$rhs)>,1130 ISA_MIPS32R6;1131 def : MipsPat<(fmaxnum f64:$lhs, f64:$rhs),1132 (MAX_D f64:$lhs, f64:$rhs)>,1133 ISA_MIPS32R6;1134 def : MipsPat<(fminnum_ieee f32:$lhs, f32:$rhs),1135 (MIN_S f32:$lhs, f32:$rhs)>,1136 ISA_MIPS32R6;1137 def : MipsPat<(fminnum f32:$lhs, f32:$rhs),1138 (MIN_S f32:$lhs, f32:$rhs)>,1139 ISA_MIPS32R6;1140 def : MipsPat<(fminnum_ieee f64:$lhs, f64:$rhs),1141 (MIN_D f64:$lhs, f64:$rhs)>,1142 ISA_MIPS32R6;1143 def : MipsPat<(fminnum f64:$lhs, f64:$rhs),1144 (MIN_D f64:$lhs, f64:$rhs)>,1145 ISA_MIPS32R6;1146 def : MipsPat<(f32 (fcanonicalize f32:$src)),1147 (MIN_S f32:$src, f32:$src)>,1148 ISA_MIPS32R6;1149 def : MipsPat<(f64 (fcanonicalize f64:$src)),1150 (MIN_D f64:$src, f64:$src)>,1151 ISA_MIPS32R6;1152}1153 1154// llvm.is_fpclass operations.1155def to_fclass_mask: SDNodeXForm<imm, [{1156 unsigned Check = N->getZExtValue();1157 unsigned Mask = 0;1158 if (Check & fcSNan)1159 Mask |= Mips::FClassMaskSignalingNaN;1160 if (Check & fcQNan)1161 Mask |= Mips::FClassMaskQuietNaN;1162 if (Check & fcPosInf)1163 Mask |= Mips::FClassMaskPositiveInfinity;1164 if (Check & fcNegInf)1165 Mask |= Mips::FClassMaskNegativeInfinity;1166 if (Check & fcPosNormal)1167 Mask |= Mips::FClassMaskPositiveNormal;1168 if (Check & fcNegNormal)1169 Mask |= Mips::FClassMaskNegativeNormal;1170 if (Check & fcPosSubnormal)1171 Mask |= Mips::FClassMaskPositiveSubnormal;1172 if (Check & fcNegSubnormal)1173 Mask |= Mips::FClassMaskNegativeSubnormal;1174 if (Check & fcPosZero)1175 Mask |= Mips::FClassMaskPositiveZero;1176 if (Check & fcNegZero)1177 Mask |= Mips::FClassMaskNegativeZero;1178 return CurDAG->getTargetConstant(Mask, SDLoc(N), MVT::i32);1179}]>;1180let AdditionalPredicates = [NotInMicroMips] in {1181 def : MipsPat<(is_fpclass f32:$lhs, i32:$imm),1182 (SLTu ZERO, (ANDi (MFC1 (CLASS_S f32:$lhs)),1183 (to_fclass_mask imm:$imm)))>,1184 ISA_MIPS32R6;1185 def : MipsPat<(is_fpclass f64:$lhs, i32:$imm),1186 (SLTu ZERO, (ANDi (MFC1_D64 (CLASS_D f64:$lhs)),1187 (to_fclass_mask imm:$imm)))>,1188 ISA_MIPS32R6;1189}1190 1191// Pseudo instructions1192let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,1193 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {1194 class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :1195 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,1196 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;1197}1198 1199class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,1200 RegisterOperand RO> :1201 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],1202 II_IndirectBranchPseudo>,1203 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {1204 let isTerminator=1;1205 let isBarrier=1;1206 let hasDelaySlot = 1;1207 let isBranch = 1;1208 let isIndirectBranch = 1;1209 bit isCTI = 1;1210}1211 1212 1213let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,1214 NoIndirectJumpGuards] in {1215 def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;1216 def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,1217 GPR32Opnd>,1218 ISA_MIPS32R6;1219}1220 1221let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,1222 UseIndirectJumpsHazard] in {1223 def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6;1224 def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6,1225 GPR32Opnd>,1226 ISA_MIPS32R6;1227}1228 1229