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1//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes Mips64r6 instructions.10//11//===----------------------------------------------------------------------===//12 13// Notes about removals/changes from MIPS32r6:14// Reencoded: dclo, dclz15 16//===----------------------------------------------------------------------===//17//18// Instruction Encodings19//20//===----------------------------------------------------------------------===//21 22class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;23class DAUI_ENC : DAUI_FM;24class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;25class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;26class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;27class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;28class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;29class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;30class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;31class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;32class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;33class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;34class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;35class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;36class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;37class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;38class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;39class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;40class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;41class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;42class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>;43class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;44 45//===----------------------------------------------------------------------===//46//47// Instruction Descriptions48//49//===----------------------------------------------------------------------===//50 51class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,52 InstrItinClass itin> {53 dag OutOperandList = (outs GPROpnd:$rs);54 dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);55 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");56 string Constraints = "$rs = $rt";57 InstrItinClass Itinerary = itin;58}59 60class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;61class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;62class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;63class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;64class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;65class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;66class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;67class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;68class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;69class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;70class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;71class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;72class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;73class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;74class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;75class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;76class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;77class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;78class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm9_exp, II_LLD>;79class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;80class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;81class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;82 83class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;84class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;85class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;86class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;87class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;88class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;89class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;90class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;91class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;92class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;93class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;94class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;95 96class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,97 GPR64Opnd, II_JIALC> {98 bit isCall = 1;99 list<Register> Defs = [RA];100}101 102class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,103 II_JIC> {104 bit isBarrier = 1;105 bit isTerminator = 1;106 list<Register> Defs = [AT];107}108 109class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp, II_LL>;110class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;111 112class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {113 bit isBranch = 1;114 bit isIndirectBranch = 1;115 bit hasDelaySlot = 1;116 bit isTerminator=1;117 bit isBarrier=1;118 bit isCTI = 1;119 InstrItinClass Itinerary = II_JR_HB;120}121 122class CRC32D_DESC : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>;123class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>;124 125//===----------------------------------------------------------------------===//126//127// Instruction Definitions128//129//===----------------------------------------------------------------------===//130 131let AdditionalPredicates = [NotInMicroMips] in {132 let DecoderMethod = "DecodeDAHIDATI" in {133 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;134 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;135 }136 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;137 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;138 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;139 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;140 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;141 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;142 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;143 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;144 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;145 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;146 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;147 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;148 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;149 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;150 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;151}152def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;153def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS64R6;154def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;155let DecoderNamespace = "Mips32r6_64r6_GP64" in {156 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;157 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;158 def JR_HB64_R6 : JR_HB_R6_ENC, JR_HB64_R6_DESC, ISA_MIPS32R6;159}160let AdditionalPredicates = [NotInMicroMips],161 DecoderNamespace = "Mips32r6_64r6_PTR64" in {162 def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;163 def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;164}165 166let DecoderNamespace = "Mips32r6_64r6_GP64" in {167// Jump and Branch Instructions168def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;169def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;170 171def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;172def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;173def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;174def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;175def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;176def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;177def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;178def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;179def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;180def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;181}182let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {183def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;184def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;185}186let AdditionalPredicates = [NotInMicroMips] in {187 def CRC32D : R6MMR6Rel, CRC32D_ENC, CRC32D_DESC, ISA_MIPS64R6, ASE_CRC;188 def CRC32CD : R6MMR6Rel, CRC32CD_ENC, CRC32CD_DESC, ISA_MIPS64R6, ASE_CRC;189}190 191//===----------------------------------------------------------------------===//192//193// Instruction Aliases194//195//===----------------------------------------------------------------------===//196 197def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;198 199def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;200 201def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;202//===----------------------------------------------------------------------===//203//204// Patterns and Pseudo Instructions205//206//===----------------------------------------------------------------------===//207 208// i64 selects209def : MipsPat<(select i64:$cond, i64:$t, i64:$f),210 (OR64 (SELNEZ64 i64:$t, i64:$cond),211 (SELEQZ64 i64:$f, i64:$cond))>,212 ISA_MIPS64R6;213def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),214 (OR64 (SELEQZ64 i64:$t, i64:$cond),215 (SELNEZ64 i64:$f, i64:$cond))>,216 ISA_MIPS64R6;217def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),218 (OR64 (SELNEZ64 i64:$t, i64:$cond),219 (SELEQZ64 i64:$f, i64:$cond))>,220 ISA_MIPS64R6;221def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),222 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),223 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,224 ISA_MIPS64R6;225def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),226 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),227 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,228 ISA_MIPS64R6;229def : MipsPat<230 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),231 (OR64 (SELEQZ64 i64:$t,232 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),233 sub_32)),234 (SELNEZ64 i64:$f,235 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),236 sub_32)))>,237 ISA_MIPS64R6;238def : MipsPat<239 (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),240 (OR64 (SELEQZ64 i64:$t,241 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),242 sub_32)),243 (SELNEZ64 i64:$f,244 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),245 sub_32)))>,246 ISA_MIPS64R6;247 248def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),249 (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;250def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),251 (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;252def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),253 (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;254def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),255 (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;256 257// i64 selects from an i32 comparison258// One complicating factor here is that bits 32-63 of an i32 are undefined.259// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.260// This would allow us to remove the sign-extensions here.261def : MipsPat<(select i32:$cond, i64:$t, i64:$f),262 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),263 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,264 ISA_MIPS64R6;265def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),266 (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),267 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,268 ISA_MIPS64R6;269def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),270 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),271 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,272 ISA_MIPS64R6;273def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),274 (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,275 immZExt16:$imm))),276 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,277 immZExt16:$imm))))>,278 ISA_MIPS64R6;279def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),280 (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,281 immZExt16:$imm))),282 (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,283 immZExt16:$imm))))>,284 ISA_MIPS64R6;285 286def : MipsPat<(select i32:$cond, i64:$t, immz),287 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,288 ISA_MIPS64R6;289def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),290 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,291 ISA_MIPS64R6;292def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),293 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,294 ISA_MIPS64R6;295def : MipsPat<(select i32:$cond, immz, i64:$f),296 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,297 ISA_MIPS64R6;298def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),299 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,300 ISA_MIPS64R6;301def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),302 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,303 ISA_MIPS64R6;304 305// Patterns used for matching away redundant sign extensions.306// MIPS32 arithmetic instructions sign extend their result implicitly.307def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),308 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),309 (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;310def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))),311 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),312 (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;313def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))),314 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),315 (DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;316def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))),317 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),318 (MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;319def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),320 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),321 (MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;322 323// Pseudo instructions324 325let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,326 NoIndirectJumpGuards] in {327 def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6;328 def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64,329 GPR64Opnd>,330 ISA_MIPS64R6;331}332 333let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,334 UseIndirectJumpsHazard] in {335 def TAILCALLHB64R6REG : TailCallReg<JR_HB64_R6, GPR64Opnd>,336 ISA_MIPS64R6;337 def PseudoIndrectHazardBranch64R6 : PseudoIndirectBranchBase<JR_HB64_R6,338 GPR64Opnd>,339 ISA_MIPS64R6;340}341