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1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// This describes the calling conventions for Mips architecture.9//===----------------------------------------------------------------------===//10 11/// CCIfSubtarget - Match if the current subtarget has a feature F.12class CCIfSubtarget<string F, CCAction A, string Invert = "">13 : CCIf<!strconcat(Invert,14 "State.getMachineFunction().getSubtarget<MipsSubtarget>().",15 F),16 A>;17 18// The inverse of CCIfSubtarget19class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;20 21/// Match if the original argument (before lowering) was a float.22/// For example, this is true for i32's that were lowered from soft-float.23class CCIfOrigArgWasFloat<CCAction A> : CCIf<"OrigTy->isFloatingPointTy()", A>;24 25/// Match if the original argument (before lowering) was a 128-bit float (i.e.26/// long double).27class CCIfOrigArgWasF128<CCAction A> : CCIf<"OrigTy->isFP128Ty()", A>;28 29/// Match if the return was not a floating point vector.30class CCIfOrigArgWasNotVectorFloat<CCAction A>31 : CCIf<"!OrigTy->isVectorTy() || !OrigTy->isFPOrFPVectorTy()", A>;32 33/// Match if the special calling conv is the specified value.34class CCIfSpecialCallingConv<string CC, CCAction A>35 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "36 "MipsCCState::" # CC, A>;37 38// For soft-float, f128 values are returned in A0_64 rather than V1_64.39def RetCC_F128SoftFloat : CallingConv<[40 CCAssignToReg<[V0_64, A0_64]>41]>;42 43// For hard-float, f128 values are returned as a pair of f64's rather than a44// pair of i64's.45def RetCC_F128HardFloat : CallingConv<[46 CCBitConvertToType<f64>,47 48 // Contrary to the ABI documentation, a struct containing a long double is49 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to50 // match the de facto ABI as implemented by GCC.51 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,52 53 CCAssignToReg<[D0_64, D2_64]>54]>;55 56// Handle F128 specially since we can't identify the original type during the57// tablegen-erated code.58def RetCC_F128 : CallingConv<[59 CCIfSubtarget<"useSoftFloat()",60 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,61 CCIfSubtargetNot<"useSoftFloat()",62 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>63]>;64 65//===----------------------------------------------------------------------===//66// Mips O32 Calling Convention67//===----------------------------------------------------------------------===//68 69def CC_MipsO32 : CallingConv<[70 // Promote i8/i16 arguments to i32.71 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,72 73 // Integer values get stored in stack slots that are 4 bytes in74 // size and 4-byte aligned.75 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,76 77 // Integer values get stored in stack slots that are 8 bytes in78 // size and 8-byte aligned.79 CCIfType<[f64], CCAssignToStack<8, 8>>80]>;81 82// Only the return rules are defined here for O32. The rules for argument83// passing are defined in MipsISelLowering.cpp.84def RetCC_MipsO32 : CallingConv<[85 // Promote i1/i8/i16 return values to i32.86 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,87 88 // i32 are returned in registers V0, V1, A0, A1, unless the original return89 // type was a vector of floats.90 CCIfOrigArgWasNotVectorFloat<CCIfType<[i32],91 CCAssignToReg<[V0, V1, A0, A1]>>>,92 93 // f32 are returned in registers F0, F294 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,95 96 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or97 // in D0 and D1 in FP32bit mode.98 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,99 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>100]>;101 102def CC_MipsO32_FP32 : CustomCallingConv;103def CC_MipsO32_FP64 : CustomCallingConv;104 105def CC_MipsO32_FP : CallingConv<[106 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,107 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>108]>;109 110//===----------------------------------------------------------------------===//111// Mips N32/64 Calling Convention112//===----------------------------------------------------------------------===//113 114def CC_MipsN_SoftFloat : CallingConv<[115 CCAssignToRegWithShadow<[A0, A1, A2, A3,116 T0, T1, T2, T3],117 [D12_64, D13_64, D14_64, D15_64,118 D16_64, D17_64, D18_64, D19_64]>,119 CCAssignToStack<4, 8>120]>;121 122def CC_MipsN : CallingConv<[123 CCIfType<[i8, i16, i32, i64],124 CCIfSubtargetNot<"isLittle()",125 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,126 127 // First deal with f32s that got turned into i32s due to soft-float128 CCIfType<[i32],129 CCIfSubtarget<"useSoftFloat()",130 CCIfOrigArgWasFloat<CCDelegateTo<CC_MipsN_SoftFloat>>>>,131 132 // All remaining integers are promoted to 64-bit.133 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,134 135 // Integer arguments are passed in integer registers.136 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,137 T0_64, T1_64, T2_64, T3_64],138 [D12_64, D13_64, D14_64, D15_64,139 D16_64, D17_64, D18_64, D19_64]>>,140 141 // f32 arguments are passed in single precision FP registers.142 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,143 F16, F17, F18, F19],144 [A0_64, A1_64, A2_64, A3_64,145 T0_64, T1_64, T2_64, T3_64]>>,146 147 // f64 arguments are passed in double precision FP registers.148 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,149 D16_64, D17_64, D18_64, D19_64],150 [A0_64, A1_64, A2_64, A3_64,151 T0_64, T1_64, T2_64, T3_64]>>,152 153 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.154 CCIfType<[f32], CCAssignToStack<4, 8>>,155 CCIfType<[i64, f64], CCAssignToStack<8, 8>>156]>;157 158// N32/64 variable arguments.159// All arguments are passed in integer registers.160def CC_MipsN_VarArg : CallingConv<[161 CCIfType<[i8, i16, i32, i64],162 CCIfSubtargetNot<"isLittle()",163 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,164 165 // All integers are promoted to 64-bit.166 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,167 168 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,169 170 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,171 T0_64, T1_64, T2_64, T3_64]>>,172 173 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.174 CCIfType<[f32], CCAssignToStack<4, 8>>,175 CCIfType<[i64, f64], CCAssignToStack<8, 8>>176]>;177 178def RetCC_MipsN : CallingConv<[179 // f128 needs to be handled similarly to f32 and f64. However, f128 is not180 // legal and is lowered to i128 which is further lowered to a pair of i64's.181 // This presents us with a problem for the calling convention since hard-float182 // still needs to pass them in FPU registers, and soft-float needs to use $v0,183 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a184 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on185 // whether the result was originally an f128 into the tablegen-erated code.186 //187 // f128 should only occur for the N64 ABI where long double is 128-bit. On188 // N32, long double is equivalent to double.189 CCIfSubtargetNot<"isSingleFloat()",190 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>>,191 192 // Aggregate returns are positioned at the lowest address in the slot for193 // both little and big-endian targets. When passing in registers, this194 // requires that big-endian targets shift the value into the upper bits.195 CCIfSubtarget<"isLittle()",196 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,197 CCIfSubtargetNot<"isLittle()",198 CCIfType<[i8, i16, i32, i64],199 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,200 201 // i64 are returned in registers V0_64, V1_64202 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,203 204 // f32 are returned in registers F0, F2205 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,206 207 // f64 are returned in registers D0, D2208 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>209]>;210 211//===----------------------------------------------------------------------===//212// Mips FastCC Calling Convention213//===----------------------------------------------------------------------===//214def CC_MipsO32_FastCC : CallingConv<[215 // f64 arguments are passed in double-precision floating pointer registers.216 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",217 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,218 D7, D8, D9]>>>,219 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",220 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,221 D4_64, D5_64, D6_64, D7_64,222 D8_64, D9_64, D10_64, D11_64,223 D12_64, D13_64, D14_64, D15_64,224 D16_64, D17_64, D18_64,225 D19_64]>>>>,226 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",227 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,228 D8_64, D10_64, D12_64, D14_64,229 D16_64, D18_64]>>>>,230 231 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.232 CCIfType<[f64], CCAssignToStack<8, 8>>233]>;234 235def CC_MipsN_FastCC : CallingConv<[236 // Integer arguments are passed in integer registers.237 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,238 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,239 T8_64, V1_64]>>,240 241 // f64 arguments are passed in double-precision floating pointer registers.242 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,243 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,244 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,245 D18_64, D19_64]>>,246 247 // Stack parameter slots for i64 and f64 are 64-bit doublewords and248 // 8-byte aligned.249 CCIfType<[i64, f64], CCAssignToStack<8, 8>>250]>;251 252def CC_Mips_FastCC : CallingConv<[253 // Handles byval parameters.254 CCIfByVal<CCPassByVal<4, 4>>,255 256 // Promote i8/i16 arguments to i32.257 CCIfType<[i8, i16], CCPromoteToType<i32>>,258 259 // Integer arguments are passed in integer registers. All scratch registers,260 // except for AT, V0 and T9, are available to be used as argument registers.261 CCIfType<[i32],262 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>,263 264 // f32 arguments are passed in single-precision floating pointer registers.265 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",266 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,267 F14, F15, F16, F17, F18, F19]>>>,268 269 // Don't use odd numbered single-precision registers for -mno-odd-spreg.270 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",271 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,272 273 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.274 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,275 276 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,277 CCDelegateTo<CC_MipsN_FastCC>278]>;279 280//===----------------------------------------------------------------------===//281// Mips Calling Convention Dispatch282//===----------------------------------------------------------------------===//283 284def RetCC_Mips : CallingConv<[285 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,286 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,287 CCDelegateTo<RetCC_MipsO32>288]>;289 290def CC_Mips_ByVal : CallingConv<[291 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,292 CCIfByVal<CCPassByVal<8, 8>>293]>;294 295def CC_Mips16RetHelper : CallingConv<[296 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,297 298 // Integer arguments are passed in integer registers.299 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>300]>;301 302def CC_Mips_FixedArg : CallingConv<[303 // Mips16 needs special handling on some functions.304 CCIf<"State.getCallingConv() != CallingConv::Fast",305 CCIfSpecialCallingConv<"Mips16RetHelperConv",306 CCDelegateTo<CC_Mips16RetHelper>>>,307 308 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,309 310 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,311 // f128 is not legal and is lowered to i128 which is further lowered to a pair312 // of i64's.313 // This presents us with a problem for the calling convention since hard-float314 // still needs to pass them in FPU registers. We therefore resort to a315 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on316 // whether the argument was originally an f128 into the tablegen-erated code.317 //318 // f128 should only occur for the N64 ABI where long double is 128-bit. On319 // N32, long double is equivalent to double.320 CCIfType<[i64], 321 CCIfSubtargetNot<"isSingleFloat()",322 CCIfSubtargetNot<"useSoftFloat()", 323 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>>,324 325 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,326 327 CCIfSubtarget<"isABI_O32()", CCIfSubtargetNot<"isGP64bit()", CCDelegateTo<CC_MipsO32_FP>>>,328 CCDelegateTo<CC_MipsN>329]>;330 331def CC_Mips_VarArg : CallingConv<[332 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,333 334 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,335 CCDelegateTo<CC_MipsN_VarArg>336]>;337 338def CC_Mips : CallingConv<[339 CCIfVarArg<CCIfArgVarArg<CCDelegateTo<CC_Mips_VarArg>>>,340 CCDelegateTo<CC_Mips_FixedArg>341]>;342 343//===----------------------------------------------------------------------===//344// Callee-saved register lists.345//===----------------------------------------------------------------------===//346 347def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), RA, FP,348 (sequence "S%u", 7, 0))>;349 350def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,351 (sequence "S%u", 7, 0))> {352 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));353}354 355def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,356 (sequence "S%u", 7, 0))>;357 358def CSR_O32_FP64 :359 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,360 (sequence "S%u", 7, 0))>;361 362def CSR_N32 : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),363 RA_64, FP_64, GP_64, (sequence "S%u_64", 7, 0))>;364 365def CSR_N32_SingleFloat366 : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,367 GP_64, (sequence "S%u_64", 7, 0))>;368 369def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,370 GP_64, (sequence "S%u_64", 7, 0))>;371 372def CSR_N64_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,373 FP_64, GP_64, (sequence "S%u_64", 7, 0))>;374 375def CSR_Mips16RetHelper :376 CalleeSavedRegs<(add V0, V1, FP,377 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),378 (sequence "D%u", 15, 10))>;379 380def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),381 (sequence "S%u", 7, 0),382 (sequence "V%u", 1, 0),383 (sequence "T%u", 9, 0),384 RA, FP, GP, AT)>;385 386def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),387 (sequence "S%u", 7, 0),388 (sequence "V%u", 1, 0),389 (sequence "T%u", 9, 0),390 RA, FP, GP, AT, LO0, HI0)>;391 392def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),393 (sequence "V%u_64", 1, 0),394 (sequence "S%u_64", 7, 0),395 (sequence "T%u_64", 9, 0),396 RA_64, FP_64, GP_64, AT_64)>;397 398def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),399 (sequence "S%u_64", 7, 0),400 (sequence "T%u_64", 9, 0),401 (sequence "V%u_64", 1, 0),402 RA_64, FP_64, GP_64, AT_64,403 LO0_64, HI0_64)>;404