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1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This is the Conditional Moves implementation.10//11//===----------------------------------------------------------------------===//12 13// Conditional moves:14// These instructions are expanded in15// MipsISelLowering::EmitInstrWithCustomInserter if target does not have16// conditional move instructions.17// cond:int, data:int18class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,19 InstrItinClass Itin> :20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),21 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {22 let Constraints = "$F = $rd";23}24 25// cond:int, data:float26class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,27 InstrItinClass Itin> :28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),29 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,30 HARDFLOAT {31 let Constraints = "$F = $fd";32}33 34// cond:float, data:int35class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,36 SDPatternOperator OpNode = null_frag> :37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),38 !strconcat(opstr, "\t$rd, $rs, $fcc"),39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],40 Itin, FrmFR, opstr>, HARDFLOAT {41 let Constraints = "$F = $rd";42}43 44// cond:float, data:float45class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,46 SDPatternOperator OpNode = null_frag> :47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),48 !strconcat(opstr, "\t$fd, $fs, $fcc"),49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],50 Itin, FrmFR, opstr>, HARDFLOAT {51 let Constraints = "$F = $fd";52}53 54// select patterns55multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,56 Instruction MOVZInst, Instruction SLTOp,57 Instruction SLTuOp, Instruction SLTiOp,58 Instruction SLTiuOp> {59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),64 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;65 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),66 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;67 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),68 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;69 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),70 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;71 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),72 DRC:$T, DRC:$F),73 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;74 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),75 DRC:$T, DRC:$F),76 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),77 DRC:$F)>;78}79 80multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,81 Instruction MOVZInst, Instruction XOROp> {82 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),83 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;86}87 88multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,89 Instruction MOVZInst, Instruction XORiOp> {90 def : MipsPat<91 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),92 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;93}94 95multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,96 Instruction XOROp> {97 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),98 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),102 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;103}104 105// Instantiation of instructions.106let AdditionalPredicates = [NotInMicroMips] in {107 def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,108 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;109 110 let isCodeGenOnly = 1 in {111 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,112 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;113 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,114 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;115 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,116 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;117 }118 119 def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,120 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;121 122 let isCodeGenOnly = 1 in {123 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,124 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;125 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,126 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;127 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,128 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;129 }130 def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,131 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;132 133 let isCodeGenOnly = 1 in134 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,135 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;136 137 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,138 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;139 140 let isCodeGenOnly = 1 in141 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,142 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;143 144 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,145 II_MOVZ_D>, CMov_I_F_FM<18, 17>,146 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;147 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,148 II_MOVN_D>, CMov_I_F_FM<19, 17>,149 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;150 151 let DecoderNamespace = "MipsFP64" in {152 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,153 CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;154 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,155 CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;156 let isCodeGenOnly = 1 in {157 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,158 CMov_I_F_FM<18, 17>,159 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;160 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,161 CMov_I_F_FM<19, 17>,162 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;163 }164 }165 166 def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,167 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;168 169 let isCodeGenOnly = 1 in170 def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,171 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;172 173 def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,174 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;175 176 let isCodeGenOnly = 1 in177 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,178 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;179 def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,180 CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;181 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,182 CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;183 184 def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,185 MipsCMovFP_T>, CMov_F_F_FM<17, 1>,186 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;187 def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,188 MipsCMovFP_F>, CMov_F_F_FM<17, 0>,189 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;190 191 let DecoderNamespace = "MipsFP64" in {192 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,193 CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;194 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,195 CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;196 }197 198 // Instantiation of conditional move patterns.199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,200 INSN_MIPS4_32_NOT_32R6_64R6;201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;202 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;203 204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,205 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,207 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,209 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,211 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,213 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,215 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,217 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,219 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,221 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;222 223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;224 225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,226 GPR_64;227 defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,228 GPR_64;229 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>,230 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;231 232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,233 INSN_MIPS4_32_NOT_32R6_64R6;234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;235 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;236 237 defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,238 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;239 defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>,240 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;241 defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,242 GPR_64;243 244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,245 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;246 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,247 FGR_32;248 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,249 FGR_32;250 251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,252 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;253 defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,254 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;255 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,256 FGR_64;257 defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,258 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;259 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,260 FGR_64;261 defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>,262 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;263}264// For targets that don't have conditional-move instructions265// we have to match SELECT nodes with pseudo instructions.266let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {267 class Select_Pseudo<RegisterOperand RC> :268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,270 ISA_MIPS1_NOT_4_32;271 272 class SelectFP_Pseudo_T<RegisterOperand RC> :273 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),274 [(set RC:$dst, (MipsCMovFP_T RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,275 ISA_MIPS1_NOT_4_32;276 277 class SelectFP_Pseudo_F<RegisterOperand RC> :278 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),279 [(set RC:$dst, (MipsCMovFP_F RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,280 ISA_MIPS1_NOT_4_32;281}282 283def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;284def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;285def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;286def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;287def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;288 289def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;290def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;291def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;292def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;293def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;294 295def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;296def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;297def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;298def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;299def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;300 301let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {302class D_SELECT_CLASS<RegisterOperand RC> :303 PseudoSE<(outs RC:$dst1, RC:$dst2),304 (ins GPR32Opnd:$cond, RC:$a1, RC:$a2, RC:$b1, RC:$b2), []>,305 ISA_MIPS1_NOT_4_32;306}307 308def PseudoD_SELECT_I : D_SELECT_CLASS<GPR32Opnd>;309def PseudoD_SELECT_I64 : D_SELECT_CLASS<GPR64Opnd>;310