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1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes Mips DSP ASE instructions.10//11//===----------------------------------------------------------------------===//12 13// ImmLeaf14def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;15def timmZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}], NOOP_SDNodeXForm, timm>;16def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;17def timmZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}], NOOP_SDNodeXForm, timm>;18def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;19def timmZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}], NOOP_SDNodeXForm, timm>;20def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;21def timmZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}], NOOP_SDNodeXForm, timm>;22def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;23def timmZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}], NOOP_SDNodeXForm, timm>;24def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;25def timmZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}], NOOP_SDNodeXForm, timm>;26def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;27def timmSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}], NOOP_SDNodeXForm, timm>;28def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;29 30// Mips-specific dsp nodes31def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,32 SDTCisVT<2, untyped>]>;33def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,34 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;35def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,36 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;37def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,38 SDTCisVT<2, i32>]>;39 40class MipsDSPBase<string Opc, SDTypeProfile Prof> :41 SDNode<!strconcat("MipsISD::", Opc), Prof>;42 43class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :44 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;45 46def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;47def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;48def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;49def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;50def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;51def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;52 53def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;54def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;55 56def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;57def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;58def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;59def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;60def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;61 62def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;63def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;64def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;65def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;66def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;67def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;68def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;69def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;70 71def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;72def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;73def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;74def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;75def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;76def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;77def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;78def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;79def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;80 81def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;82def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;83def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;84def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;85def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;86def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;87def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;88def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;89def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;90def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;91def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;92 93// Flags.94class Uses<list<Register> Regs> {95 list<Register> Uses = Regs;96}97 98class Defs<list<Register> Regs> {99 list<Register> Defs = Regs;100}101 102// Instruction encoding.103class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;104class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;105class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;106class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;107class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;108class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;109class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;110class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;111class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;112class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;113class ADDSC_ENC : ADDU_QB_FMT<0b10000>;114class ADDWC_ENC : ADDU_QB_FMT<0b10001>;115class MODSUB_ENC : ADDU_QB_FMT<0b10010>;116class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;117class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;118class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;119class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;120class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;121class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;122class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;123class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;124class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;125class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;126class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;127class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;128class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;129class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;130class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;131class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;132class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;133class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;134class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;135class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;136class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;137class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;138class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;139class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;140class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;141class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;142class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;143class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;144class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;145class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;146class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;147class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;148class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;149class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;150class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;151class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;152class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;153class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;154class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;155class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;156class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;157class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;158class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;159class MFHI_ENC : MFHI_FMT<0b010000>;160class MFLO_ENC : MFHI_FMT<0b010010>;161class MTHI_ENC : MTHI_FMT<0b010001>;162class MTLO_ENC : MTHI_FMT<0b010011>;163class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;164class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;165class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;166class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;167class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;168class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;169class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;170class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;171class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;172class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;173class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;174class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;175class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;176class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;177class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;178class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;179class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;180class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;181class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;182class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;183class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;184class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;185class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;186class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;187class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;188class REPL_QB_ENC : REPL_FMT<0b00010>;189class REPL_PH_ENC : REPL_FMT<0b01010>;190class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;191class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;192class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;193class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;194class LWX_ENC : LX_FMT<0b00000>;195class LHX_ENC : LX_FMT<0b00100>;196class LBUX_ENC : LX_FMT<0b00110>;197class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;198class INSV_ENC : INSV_FMT<0b001100>;199 200class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;201class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;202class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;203class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;204class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;205class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;206class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;207class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;208class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;209class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;210class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;211class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;212class SHILO_ENC : SHILO_R1_FMT<0b11010>;213class SHILOV_ENC : SHILO_R2_FMT<0b11011>;214class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;215 216class RDDSP_ENC : RDDSP_FMT<0b10010>;217class WRDSP_ENC : WRDSP_FMT<0b10011>;218class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;219class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;220class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;221class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;222class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;223class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;224class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;225class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;226class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;227class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;228class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;229class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;230class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;231class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;232class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;233class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;234class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;235class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;236class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;237class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;238class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;239class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;240class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;241class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;242class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;243class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;244class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;245class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;246class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;247class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;248class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;249class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;250class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;251class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;252class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;253class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;254class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;255class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;256class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;257class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;258class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;259class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;260class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;261class APPEND_ENC : APPEND_FMT<0b00000>;262class BALIGN_ENC : APPEND_FMT<0b10000>;263class PREPEND_ENC : APPEND_FMT<0b00001>;264 265// Instruction desc.266class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,267 InstrItinClass itin, RegisterOperand ROD,268 RegisterOperand ROS, RegisterOperand ROT = ROS> {269 dag OutOperandList = (outs ROD:$rd);270 dag InOperandList = (ins ROS:$rs, ROT:$rt);271 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];273 InstrItinClass Itinerary = itin;274 string BaseOpcode = instr_asm;275}276 277class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,278 InstrItinClass itin, RegisterOperand ROD,279 RegisterOperand ROS = ROD> {280 dag OutOperandList = (outs ROD:$rd);281 dag InOperandList = (ins ROS:$rs);282 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];284 InstrItinClass Itinerary = itin;285 string BaseOpcode = instr_asm;286}287 288class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,289 InstrItinClass itin, RegisterOperand ROS,290 RegisterOperand ROT = ROS> {291 dag OutOperandList = (outs);292 dag InOperandList = (ins ROS:$rs, ROT:$rt);293 string AsmString = !strconcat(instr_asm, "\t$rs, $rt");294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];295 InstrItinClass Itinerary = itin;296 string BaseOpcode = instr_asm;297}298 299class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,300 InstrItinClass itin, RegisterOperand ROD,301 RegisterOperand ROS, RegisterOperand ROT = ROS> {302 dag OutOperandList = (outs ROD:$rd);303 dag InOperandList = (ins ROS:$rs, ROT:$rt);304 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];306 InstrItinClass Itinerary = itin;307 string BaseOpcode = instr_asm;308}309 310class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,311 InstrItinClass itin, RegisterOperand ROT,312 RegisterOperand ROS = ROT> {313 dag OutOperandList = (outs ROT:$rt);314 dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);315 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];317 InstrItinClass Itinerary = itin;318 string Constraints = "$src = $rt";319 string BaseOpcode = instr_asm;320}321 322class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,323 InstrItinClass itin, RegisterOperand ROD,324 RegisterOperand ROT = ROD> {325 dag OutOperandList = (outs ROD:$rd);326 dag InOperandList = (ins ROT:$rt);327 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");328 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];329 InstrItinClass Itinerary = itin;330 string BaseOpcode = instr_asm;331}332 333class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,334 Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,335 RegisterOperand RO> {336 dag OutOperandList = (outs RO:$rd);337 dag InOperandList = (ins ImmOp:$imm);338 string AsmString = !strconcat(instr_asm, "\t$rd, $imm");339 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];340 InstrItinClass Itinerary = itin;341 string BaseOpcode = instr_asm;342}343 344class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,345 InstrItinClass itin, RegisterOperand RO> {346 dag OutOperandList = (outs RO:$rd);347 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);348 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");349 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];350 InstrItinClass Itinerary = itin;351 string BaseOpcode = instr_asm;352}353 354class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,355 SDPatternOperator ImmPat, InstrItinClass itin,356 RegisterOperand RO, Operand ImmOpnd> {357 dag OutOperandList = (outs RO:$rd);358 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);359 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");360 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];361 InstrItinClass Itinerary = itin;362 bit hasSideEffects = 1;363 string BaseOpcode = instr_asm;364}365 366class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,367 InstrItinClass itin> {368 dag OutOperandList = (outs GPR32Opnd:$rd);369 dag InOperandList = (ins PtrRC:$base, PtrRC:$index);370 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");371 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];372 InstrItinClass Itinerary = itin;373 bit mayLoad = 1;374 string BaseOpcode = instr_asm;375}376 377class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,378 InstrItinClass itin, RegisterOperand ROD,379 RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {380 dag OutOperandList = (outs ROD:$rd);381 dag InOperandList = (ins ROS:$rs, ROT:$rt);382 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");383 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];384 InstrItinClass Itinerary = itin;385 string BaseOpcode = instr_asm;386}387 388class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,389 Operand ImmOp, SDPatternOperator Imm,390 InstrItinClass itin> {391 dag OutOperandList = (outs GPR32Opnd:$rt);392 dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);393 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");394 list<dag> Pattern = [(set GPR32Opnd:$rt,395 (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];396 InstrItinClass Itinerary = itin;397 string Constraints = "$src = $rt";398 string BaseOpcode = instr_asm;399}400 401class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, InstrItinClass itin> {402 dag OutOperandList = (outs GPR32Opnd:$rt);403 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);404 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");405 InstrItinClass Itinerary = itin;406 string BaseOpcode = instr_asm;407}408 409class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, InstrItinClass itin> {410 dag OutOperandList = (outs GPR32Opnd:$rt);411 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);412 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");413 InstrItinClass Itinerary = itin;414 string BaseOpcode = instr_asm;415}416 417class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {418 dag OutOperandList = (outs ACC64DSPOpnd:$ac);419 dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);420 string AsmString = !strconcat(instr_asm, "\t$ac, $shift");421 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,422 (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];423 string Constraints = "$acin = $ac";424 string BaseOpcode = instr_asm;425}426 427class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {428 dag OutOperandList = (outs ACC64DSPOpnd:$ac);429 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);430 string AsmString = !strconcat(instr_asm, "\t$ac, $rs");431 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,432 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];433 string Constraints = "$acin = $ac";434 string BaseOpcode = instr_asm;435}436 437class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {438 dag OutOperandList = (outs ACC64DSPOpnd:$ac);439 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);440 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");441 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,442 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];443 string Constraints = "$acin = $ac";444 string BaseOpcode = instr_asm;445}446 447class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,448 InstrItinClass itin> {449 dag OutOperandList = (outs GPR32Opnd:$rd);450 dag InOperandList = (ins uimm10:$mask);451 string AsmString = !strconcat(instr_asm, "\t$rd, $mask");452 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode timmZExt10:$mask))];453 InstrItinClass Itinerary = itin;454 string BaseOpcode = instr_asm;455}456 457class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,458 InstrItinClass itin> {459 dag OutOperandList = (outs);460 dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);461 string AsmString = !strconcat(instr_asm, "\t$rs, $mask");462 list<dag> Pattern = [(OpNode GPR32Opnd:$rs, timmZExt10:$mask)];463 InstrItinClass Itinerary = itin;464 string BaseOpcode = instr_asm;465}466 467class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {468 dag OutOperandList = (outs ACC64DSPOpnd:$ac);469 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);470 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");471 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,472 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];473 string Constraints = "$acin = $ac";474 string BaseOpcode = instr_asm;475}476 477class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,478 InstrItinClass itin> {479 dag OutOperandList = (outs ACC64DSPOpnd:$ac);480 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);481 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");482 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];483 InstrItinClass Itinerary = itin;484 bit isCommutable = 1;485 string BaseOpcode = instr_asm;486}487 488class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,489 InstrItinClass itin> {490 dag OutOperandList = (outs ACC64DSPOpnd:$ac);491 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);492 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");493 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,494 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];495 InstrItinClass Itinerary = itin;496 string Constraints = "$acin = $ac";497 string BaseOpcode = instr_asm;498}499 500class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,501 InstrItinClass itin> {502 dag OutOperandList = (outs GPR32Opnd:$rd);503 dag InOperandList = (ins RO:$ac);504 string AsmString = !strconcat(instr_asm, "\t$rd, $ac");505 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];506 InstrItinClass Itinerary = itin;507 string BaseOpcode = instr_asm;508 bit isMoveReg = 1;509}510 511class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,512 InstrItinClass itin> {513 dag OutOperandList = (outs RO:$ac);514 dag InOperandList = (ins GPR32Opnd:$rs);515 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");516 InstrItinClass Itinerary = itin;517 string BaseOpcode = instr_asm;518 bit isMoveReg = 1;519}520 521class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode> :522 MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {523 bit hasNoSchedulingInfo = 1;524 bit usesCustomInserter = 1;525}526 527class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,528 InstrItinClass itin> {529 dag OutOperandList = (outs);530 dag InOperandList = (ins opnd:$offset);531 string AsmString = !strconcat(instr_asm, "\t$offset");532 InstrItinClass Itinerary = itin;533 bit isBranch = 1;534 bit isTerminator = 1;535 bit hasDelaySlot = 1;536 string BaseOpcode = instr_asm;537}538 539class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,540 InstrItinClass itin> {541 dag OutOperandList = (outs GPR32Opnd:$rt);542 dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);543 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");544 list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];545 InstrItinClass Itinerary = itin;546 string Constraints = "$src = $rt";547 string BaseOpcode = instr_asm;548}549 550//===----------------------------------------------------------------------===//551// MIPS DSP Rev 1552//===----------------------------------------------------------------------===//553 554// Addition/subtraction555class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,556 DSPROpnd, DSPROpnd>, IsCommutable,557 Defs<[DSPOutFlag20]>;558 559class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,560 NoItinerary, DSPROpnd, DSPROpnd>,561 IsCommutable, Defs<[DSPOutFlag20]>;562 563class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,564 DSPROpnd, DSPROpnd>,565 Defs<[DSPOutFlag20]>;566 567class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,568 NoItinerary, DSPROpnd, DSPROpnd>,569 Defs<[DSPOutFlag20]>;570 571class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,572 DSPROpnd, DSPROpnd>, IsCommutable,573 Defs<[DSPOutFlag20]>;574 575class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,576 NoItinerary, DSPROpnd, DSPROpnd>,577 IsCommutable, Defs<[DSPOutFlag20]>;578 579class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,580 DSPROpnd, DSPROpnd>,581 Defs<[DSPOutFlag20]>;582 583class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,584 NoItinerary, DSPROpnd, DSPROpnd>,585 Defs<[DSPOutFlag20]>;586 587class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,588 NoItinerary, GPR32Opnd, GPR32Opnd>,589 IsCommutable, Defs<[DSPOutFlag20]>;590 591class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,592 NoItinerary, GPR32Opnd, GPR32Opnd>,593 Defs<[DSPOutFlag20]>;594 595class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,596 GPR32Opnd, GPR32Opnd>, IsCommutable,597 Defs<[DSPCarry]>;598 599class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,600 GPR32Opnd, GPR32Opnd>,601 IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;602 603class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,604 GPR32Opnd, GPR32Opnd>;605 606class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,607 NoItinerary, GPR32Opnd, DSPROpnd>;608 609// Absolute value610class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,611 NoItinerary, DSPROpnd>,612 Defs<[DSPOutFlag20]>;613 614class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,615 NoItinerary, GPR32Opnd>,616 Defs<[DSPOutFlag20]>;617 618// Precision reduce/expand619class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",620 int_mips_precrq_qb_ph,621 NoItinerary, DSPROpnd, DSPROpnd>;622 623class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",624 int_mips_precrq_ph_w,625 NoItinerary, DSPROpnd, GPR32Opnd>;626 627class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",628 int_mips_precrq_rs_ph_w,629 NoItinerary, DSPROpnd,630 GPR32Opnd>,631 Defs<[DSPOutFlag22]>;632 633class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",634 int_mips_precrqu_s_qb_ph,635 NoItinerary, DSPROpnd,636 DSPROpnd>,637 Defs<[DSPOutFlag22]>;638 639class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",640 int_mips_preceq_w_phl,641 NoItinerary, GPR32Opnd, DSPROpnd>;642 643class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",644 int_mips_preceq_w_phr,645 NoItinerary, GPR32Opnd, DSPROpnd>;646 647class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",648 int_mips_precequ_ph_qbl,649 NoItinerary, DSPROpnd>;650 651class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",652 int_mips_precequ_ph_qbr,653 NoItinerary, DSPROpnd>;654 655class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",656 int_mips_precequ_ph_qbla,657 NoItinerary, DSPROpnd>;658 659class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",660 int_mips_precequ_ph_qbra,661 NoItinerary, DSPROpnd>;662 663class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",664 int_mips_preceu_ph_qbl,665 NoItinerary, DSPROpnd>;666 667class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",668 int_mips_preceu_ph_qbr,669 NoItinerary, DSPROpnd>;670 671class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",672 int_mips_preceu_ph_qbla,673 NoItinerary, DSPROpnd>;674 675class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",676 int_mips_preceu_ph_qbra,677 NoItinerary, DSPROpnd>;678 679// Shift680class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,681 NoItinerary, DSPROpnd, uimm3>,682 Defs<[DSPOutFlag22]>;683 684class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,685 NoItinerary, DSPROpnd>,686 Defs<[DSPOutFlag22]>;687 688class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,689 NoItinerary, DSPROpnd, uimm3>;690 691class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,692 NoItinerary, DSPROpnd>;693 694class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,695 NoItinerary, DSPROpnd, uimm4>,696 Defs<[DSPOutFlag22]>;697 698class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,699 NoItinerary, DSPROpnd>,700 Defs<[DSPOutFlag22]>;701 702class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,703 immZExt4, NoItinerary, DSPROpnd,704 uimm4>,705 Defs<[DSPOutFlag22]>;706 707class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,708 NoItinerary, DSPROpnd>,709 Defs<[DSPOutFlag22]>;710 711class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,712 NoItinerary, DSPROpnd, uimm4>;713 714class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,715 NoItinerary, DSPROpnd>;716 717class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,718 immZExt4, NoItinerary, DSPROpnd,719 uimm4>;720 721class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,722 NoItinerary, DSPROpnd>;723 724class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,725 immZExt5, NoItinerary, GPR32Opnd,726 uimm5>,727 Defs<[DSPOutFlag22]>;728 729class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,730 NoItinerary, GPR32Opnd>,731 Defs<[DSPOutFlag22]>;732 733class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,734 immZExt5, NoItinerary, GPR32Opnd,735 uimm5>;736 737class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,738 NoItinerary, GPR32Opnd>;739 740// Multiplication741class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",742 int_mips_muleu_s_ph_qbl,743 NoItinerary, DSPROpnd, DSPROpnd>,744 Defs<[DSPOutFlag21]>;745 746class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",747 int_mips_muleu_s_ph_qbr,748 NoItinerary, DSPROpnd, DSPROpnd>,749 Defs<[DSPOutFlag21]>;750 751class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",752 int_mips_muleq_s_w_phl,753 NoItinerary, GPR32Opnd, DSPROpnd>,754 IsCommutable, Defs<[DSPOutFlag21]>;755 756class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",757 int_mips_muleq_s_w_phr,758 NoItinerary, GPR32Opnd, DSPROpnd>,759 IsCommutable, Defs<[DSPOutFlag21]>;760 761class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,762 NoItinerary, DSPROpnd, DSPROpnd>,763 IsCommutable, Defs<[DSPOutFlag21]>;764 765class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",766 MipsMULSAQ_S_W_PH>,767 Defs<[DSPOutFlag16_19]>;768 769class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,770 Defs<[DSPOutFlag16_19]>;771 772class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,773 Defs<[DSPOutFlag16_19]>;774 775class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,776 Defs<[DSPOutFlag16_19]>;777 778class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,779 Defs<[DSPOutFlag16_19]>;780 781// Move from/to hi/lo.782class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;783class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;784class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;785class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;786 787// Dot product with accumulate/subtract788class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;789 790class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;791 792class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;793 794class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;795 796class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,797 Defs<[DSPOutFlag16_19]>;798 799class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,800 Defs<[DSPOutFlag16_19]>;801 802class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,803 Defs<[DSPOutFlag16_19]>;804 805class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,806 Defs<[DSPOutFlag16_19]>;807 808class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;809class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;810class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;811class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;812class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;813class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;814 815// Comparison816class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",817 int_mips_cmpu_eq_qb, NoItinerary,818 DSPROpnd>,819 IsCommutable, Defs<[DSPCCond]>;820 821class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",822 int_mips_cmpu_lt_qb, NoItinerary,823 DSPROpnd>, Defs<[DSPCCond]>;824 825class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",826 int_mips_cmpu_le_qb, NoItinerary,827 DSPROpnd>, Defs<[DSPCCond]>;828 829class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",830 int_mips_cmpgu_eq_qb,831 NoItinerary, GPR32Opnd, DSPROpnd>,832 IsCommutable;833 834class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",835 int_mips_cmpgu_lt_qb,836 NoItinerary, GPR32Opnd, DSPROpnd>;837 838class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",839 int_mips_cmpgu_le_qb,840 NoItinerary, GPR32Opnd, DSPROpnd>;841 842class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,843 NoItinerary, DSPROpnd>,844 IsCommutable, Defs<[DSPCCond]>;845 846class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,847 NoItinerary, DSPROpnd>,848 Defs<[DSPCCond]>;849 850class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,851 NoItinerary, DSPROpnd>,852 Defs<[DSPCCond]>;853 854// Misc855class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,856 NoItinerary, GPR32Opnd>;857 858class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,859 NoItinerary, DSPROpnd, DSPROpnd>;860 861class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,862 immZExt8, NoItinerary, DSPROpnd>;863 864class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,865 immSExt10, NoItinerary, DSPROpnd>;866 867class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,868 NoItinerary, DSPROpnd, GPR32Opnd>;869 870class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,871 NoItinerary, DSPROpnd, GPR32Opnd>;872 873class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,874 NoItinerary, DSPROpnd, DSPROpnd>,875 Uses<[DSPCCond]>;876 877class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,878 NoItinerary, DSPROpnd, DSPROpnd>,879 Uses<[DSPCCond]>;880 881class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;882 883class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;884 885class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;886 887class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;888 889// Extr890class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", NoItinerary>,891 Uses<[DSPPos]>, Defs<[DSPEFI]>;892 893class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", NoItinerary>,894 Uses<[DSPPos]>, Defs<[DSPEFI]>;895 896class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", NoItinerary>,897 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;898 899class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", NoItinerary>,900 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;901 902class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", NoItinerary>,903 Defs<[DSPOutFlag23]>;904 905class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", NoItinerary>,906 Defs<[DSPOutFlag23]>;907 908class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", NoItinerary>,909 Defs<[DSPOutFlag23]>;910 911class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", NoItinerary>,912 Defs<[DSPOutFlag23]>;913 914class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", NoItinerary>,915 Defs<[DSPOutFlag23]>;916 917class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", NoItinerary>,918 Defs<[DSPOutFlag23]>;919 920class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", NoItinerary>,921 Defs<[DSPOutFlag23]>;922 923class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", NoItinerary>,924 Defs<[DSPOutFlag23]>;925 926class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;927 928class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;929 930class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;931 932class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;933 934class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;935 936class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,937 Uses<[DSPPos, DSPSCount]>;938 939//===----------------------------------------------------------------------===//940// MIPS DSP Rev 2941// Addition/subtraction942class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,943 DSPROpnd, DSPROpnd>, IsCommutable,944 Defs<[DSPOutFlag20]>;945 946class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,947 NoItinerary, DSPROpnd, DSPROpnd>,948 IsCommutable, Defs<[DSPOutFlag20]>;949 950class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,951 DSPROpnd, DSPROpnd>,952 Defs<[DSPOutFlag20]>;953 954class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,955 NoItinerary, DSPROpnd, DSPROpnd>,956 Defs<[DSPOutFlag20]>;957 958class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,959 NoItinerary, DSPROpnd>, IsCommutable;960 961class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,962 NoItinerary, DSPROpnd>, IsCommutable;963 964class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,965 NoItinerary, DSPROpnd>;966 967class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,968 NoItinerary, DSPROpnd>;969 970class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,971 NoItinerary, DSPROpnd>, IsCommutable;972 973class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,974 NoItinerary, DSPROpnd>, IsCommutable;975 976class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,977 NoItinerary, DSPROpnd>;978 979class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,980 NoItinerary, DSPROpnd>;981 982class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,983 NoItinerary, GPR32Opnd>, IsCommutable;984 985class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,986 NoItinerary, GPR32Opnd>, IsCommutable;987 988class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,989 NoItinerary, GPR32Opnd>;990 991class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,992 NoItinerary, GPR32Opnd>;993 994// Comparison995class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",996 int_mips_cmpgdu_eq_qb,997 NoItinerary, GPR32Opnd, DSPROpnd>,998 IsCommutable, Defs<[DSPCCond]>;999 1000class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",1001 int_mips_cmpgdu_lt_qb,1002 NoItinerary, GPR32Opnd, DSPROpnd>,1003 Defs<[DSPCCond]>;1004 1005class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",1006 int_mips_cmpgdu_le_qb,1007 NoItinerary, GPR32Opnd, DSPROpnd>,1008 Defs<[DSPCCond]>;1009 1010// Absolute1011class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,1012 NoItinerary, DSPROpnd>,1013 Defs<[DSPOutFlag20]>;1014 1015// Multiplication1016class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,1017 DSPROpnd>, IsCommutable,1018 Defs<[DSPOutFlag21]>;1019 1020class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,1021 NoItinerary, DSPROpnd>, IsCommutable,1022 Defs<[DSPOutFlag21]>;1023 1024class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,1025 NoItinerary, GPR32Opnd>, IsCommutable,1026 Defs<[DSPOutFlag21]>;1027 1028class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,1029 NoItinerary, GPR32Opnd>, IsCommutable,1030 Defs<[DSPOutFlag21]>;1031 1032class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,1033 NoItinerary, DSPROpnd, DSPROpnd>,1034 IsCommutable, Defs<[DSPOutFlag21]>;1035 1036// Dot product with accumulate/subtract1037class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;1038 1039class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;1040 1041class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,1042 Defs<[DSPOutFlag16_19]>;1043 1044class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",1045 MipsDPAQX_SA_W_PH>,1046 Defs<[DSPOutFlag16_19]>;1047 1048class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;1049 1050class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;1051 1052class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,1053 Defs<[DSPOutFlag16_19]>;1054 1055class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",1056 MipsDPSQX_SA_W_PH>,1057 Defs<[DSPOutFlag16_19]>;1058 1059class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;1060 1061// Precision reduce/expand1062class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",1063 int_mips_precr_qb_ph,1064 NoItinerary, DSPROpnd, DSPROpnd>;1065 1066class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",1067 int_mips_precr_sra_ph_w,1068 NoItinerary, DSPROpnd,1069 GPR32Opnd>;1070 1071class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",1072 int_mips_precr_sra_r_ph_w,1073 NoItinerary, DSPROpnd,1074 GPR32Opnd>;1075 1076// Shift1077class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,1078 NoItinerary, DSPROpnd, uimm3>;1079 1080class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,1081 NoItinerary, DSPROpnd>;1082 1083class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,1084 immZExt3, NoItinerary, DSPROpnd,1085 uimm3>;1086 1087class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,1088 NoItinerary, DSPROpnd>;1089 1090class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,1091 NoItinerary, DSPROpnd, uimm4>;1092 1093class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,1094 NoItinerary, DSPROpnd>;1095 1096// Misc1097class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5,1098 NoItinerary>;1099 1100class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, timmZExt2,1101 NoItinerary>;1102 1103class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,1104 timmZExt5, NoItinerary>;1105 1106// Pseudos.1107def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32>,1108 Uses<[DSPPos]>;1109 1110// Instruction defs.1111// MIPS DSP Rev 11112def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;1113def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;1114def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;1115def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;1116def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;1117def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;1118def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;1119def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;1120def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;1121def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;1122def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;1123def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;1124def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;1125def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;1126def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;1127def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;1128def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;1129def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;1130def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;1131def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;1132def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;1133def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;1134def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;1135def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;1136def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;1137def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;1138def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;1139def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;1140def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;1141def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;1142def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;1143def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;1144def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;1145def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;1146def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;1147def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;1148def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;1149def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;1150def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;1151def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;1152def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;1153def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;1154def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;1155def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;1156def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;1157def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;1158def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;1159def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;1160def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;1161def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;1162def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;1163def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;1164def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;1165def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;1166def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;1167def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;1168def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;1169def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;1170def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;1171def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;1172def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;1173def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;1174def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;1175def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;1176def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;1177def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;1178def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;1179def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;1180def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;1181def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;1182def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;1183def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;1184def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;1185def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;1186def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;1187def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;1188def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;1189def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;1190def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;1191def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;1192def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;1193def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;1194def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;1195def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;1196def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;1197def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;1198def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;1199def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;1200def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;1201def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;1202def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;1203def LWX : DspMMRel, LWX_ENC, LWX_DESC;1204def LHX : DspMMRel, LHX_ENC, LHX_DESC;1205def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;1206let AdditionalPredicates = [NotInMicroMips] in {1207 def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;1208}1209def INSV : DspMMRel, INSV_ENC, INSV_DESC;1210def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;1211def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;1212def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;1213def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;1214def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;1215def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;1216def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;1217def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;1218def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;1219def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;1220def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;1221def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;1222def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;1223def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;1224def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;1225def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;1226let AdditionalPredicates = [NotInMicroMips] in {1227 def WRDSP : WRDSP_ENC, WRDSP_DESC;1228}1229 1230// MIPS DSP Rev 21231def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;1232def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;1233def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;1234def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;1235def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;1236def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;1237def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;1238def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;1239def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;1240def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;1241def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;1242def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;1243def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;1244def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;1245def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;1246def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;1247def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;1248def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;1249def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;1250def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;1251def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;1252def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;1253def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;1254def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;1255def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;1256def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;1257def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;1258def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;1259def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;1260def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;1261def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;1262def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;1263def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;1264def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;1265def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;1266def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;1267def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;1268def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;1269def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;1270def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;1271def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;1272def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;1273def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;1274def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;1275def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;1276def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;1277 1278// Pseudos.1279let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {1280 // Pseudo instructions for loading and storing accumulator registers.1281 def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>;1282 def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;1283 1284 // Pseudos for loading and storing ccond field of DSP control register.1285 def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>;1286 def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;1287}1288 1289let DecoderNamespace = "MipsDSP", Arch = "dsp",1290 ASEPredicate = [HasDSP] in {1291 def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;1292 def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;1293}1294 1295// Pseudo CMP and PICK instructions.1296class PseudoCMP<Instruction RealInst> :1297 PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,1298 PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>,1299 NeverHasSideEffects;1300 1301class PseudoPICK<Instruction RealInst> :1302 PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,1303 PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,1304 NeverHasSideEffects;1305 1306def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;1307def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;1308def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;1309def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;1310def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;1311def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;1312 1313def PseudoPICK_PH : PseudoPICK<PICK_PH>;1314def PseudoPICK_QB : PseudoPICK<PICK_QB>;1315 1316let AdditionalPredicates = [HasDSP] in {1317 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;1318}1319 1320// Patterns.1321class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :1322 Pat<pattern, result>, Requires<[pred]>;1323 1324class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,1325 RegisterClass SrcRC> :1326 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),1327 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;1328 1329def : BitconvertPat<i32, v2i16, GPR32, DSPR>;1330def : BitconvertPat<i32, v4i8, GPR32, DSPR>;1331def : BitconvertPat<v2i16, i32, DSPR, GPR32>;1332def : BitconvertPat<v4i8, i32, DSPR, GPR32>;1333def : BitconvertPat<f32, v2i16, FGR32, DSPR>;1334def : BitconvertPat<f32, v4i8, FGR32, DSPR>;1335def : BitconvertPat<v2i16, f32, DSPR, FGR32>;1336def : BitconvertPat<v4i8, f32, DSPR, FGR32>;1337 1338def : DSPPat<(v2i16 (load addr:$a)),1339 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;1340def : DSPPat<(v4i8 (load addr:$a)),1341 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;1342def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),1343 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;1344def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),1345 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;1346 1347// Binary operations.1348class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,1349 Predicate Pred = HasDSP> :1350 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;1351 1352def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;1353def : DSPBinPat<ADDQ_PH, v2i16, add>;1354def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;1355def : DSPBinPat<SUBQ_PH, v2i16, sub>;1356def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;1357def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;1358def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;1359def : DSPBinPat<ADDU_QB, v4i8, add>;1360def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;1361def : DSPBinPat<SUBU_QB, v4i8, sub>;1362def : DSPBinPat<ADDSC, i32, int_mips_addsc>;1363def : DSPBinPat<ADDSC, i32, addc>;1364def : DSPBinPat<ADDWC, i32, int_mips_addwc>;1365def : DSPBinPat<ADDWC, i32, adde>;1366 1367// Shift immediate patterns.1368class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,1369 SDPatternOperator Imm, Predicate Pred = HasDSP> :1370 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;1371 1372def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;1373def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;1374def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;1375def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;1376def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;1377def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;1378def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;1379def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;1380def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;1381def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;1382def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;1383def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;1384 1385// SETCC/SELECT_CC patterns.1386class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,1387 CondCode CC> :1388 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),1389 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),1390 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),1391 (ValTy ZERO)))>;1392 1393class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,1394 CondCode CC> :1395 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),1396 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),1397 (ValTy ZERO),1398 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;1399 1400class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,1401 CondCode CC> :1402 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),1403 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;1404 1405class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,1406 CondCode CC> :1407 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),1408 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;1409 1410def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;1411def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;1412def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;1413def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;1414def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;1415def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;1416def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;1417def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;1418def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;1419def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;1420def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;1421def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;1422 1423def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;1424def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;1425def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;1426def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;1427def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;1428def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;1429def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;1430def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;1431def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;1432def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;1433def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;1434def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;1435 1436// Extr patterns.1437class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :1438 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),1439 (Instr ACC64DSP:$ac, GPR32:$rs)>;1440 1441class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :1442 DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),1443 (Instr ACC64DSP:$ac, immZExt5:$shift)>;1444 1445def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;1446def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;1447def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;1448def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;1449def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;1450def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;1451def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;1452def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;1453def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;1454def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;1455def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;1456def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;1457 1458// Indexed load patterns.1459class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :1460 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),1461 (Instr i32:$base, i32:$index)>;1462 1463let AddedComplexity = 20 in {1464 def : IndexedLoadPat<zextloadi8, LBUX>;1465 def : IndexedLoadPat<sextloadi16, LHX>;1466 def : IndexedLoadPat<load, LWX>;1467}1468 1469// Instruction alias.1470let AdditionalPredicates = [NotInMicroMips] in {1471 def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;1472}1473