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1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Mips FPU instruction set.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Floating Point Instructions15// ------------------------16// * 64bit fp:17// - 32 64-bit registers (default mode)18// - 16 even 32-bit registers (32-bit compatible mode) for19// single and double access.20// * 32bit fp:21// - 16 even 32-bit registers - single and double (aliased)22// - 32 32-bit registers (within single-only mode)23//===----------------------------------------------------------------------===//24 25// Floating Point Compare and Branch26def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,27 SDTCisVT<1, i32>,28 SDTCisVT<2, OtherVT>]>;29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,30 SDTCisVT<2, i32>]>;31def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,32 SDTCisSameAs<1, 3>]>;33def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;34def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,35 SDTCisVT<1, i32>,36 SDTCisSameAs<1, 2>]>;37def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,38 SDTCisVT<1, f64>,39 SDTCisVT<2, i32>]>;40 41def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>,42 SDTCisVT<1, i32>]>;43 44def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;45def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;46def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;47def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,48 [SDNPHasChain, SDNPOptInGlue]>;49def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;50def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;51def : GINodeEquiv<G_MERGE_VALUES, MipsBuildPairF64>;52def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",53 SDT_MipsExtractElementF64>;54 55def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;56 57// Operand for printing out a condition code.58let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in59 def condcode : Operand<i32>;60 61//===----------------------------------------------------------------------===//62// Feature predicates.63//===----------------------------------------------------------------------===//64 65def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,66 AssemblerPredicate<(all_of FeatureFP64Bit)>;67def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,68 AssemblerPredicate<(all_of (not FeatureFP64Bit))>;69def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,70 AssemblerPredicate<(all_of FeatureSingleFloat)>;71def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,72 AssemblerPredicate<(all_of (not FeatureSingleFloat))>;73def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,74 AssemblerPredicate<(all_of (not FeatureSoftFloat))>;75def HasMips3D : Predicate<"Subtarget->has3D()">,76 AssemblerPredicate<(all_of FeatureMips3D)>;77 78//===----------------------------------------------------------------------===//79// Mips FGR size adjectives.80// They are mutually exclusive.81//===----------------------------------------------------------------------===//82 83class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }84class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }85class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }86 87//===----------------------------------------------------------------------===//88 89// FP immediate patterns.90def fpimm0 : PatLeaf<(fpimm), [{91 return N->isExactlyValue(+0.0);92}]>;93 94def fpimm0neg : PatLeaf<(fpimm), [{95 return N->isExactlyValue(-0.0);96}]>;97 98//===----------------------------------------------------------------------===//99// Instruction Class Templates100//101// A set of multiclasses is used to address the register usage.102//103// S32 - single precision in 16 32bit even fp registers104// single precision in 32 32bit fp registers in SingleOnly mode105// S64 - single precision in 32 64bit fp registers (In64BitMode)106// D32 - double precision in 16 32bit even fp registers107// D64 - double precision in 32 64bit fp registers (In64BitMode)108//109// Only S32 and D32 are supported right now.110//===----------------------------------------------------------------------===//111class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,112 SDPatternOperator OpNode= null_frag> :113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),114 !strconcat(opstr, "\t$fd, $fs, $ft"),115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,116 HARDFLOAT {117 let isCommutable = IsComm;118}119 120multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,121 SDPatternOperator OpNode = null_frag> {122 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;123 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {124 string DecoderNamespace = "MipsFP64";125 }126}127 128class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,129 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,132 HARDFLOAT,133 NeverHasSideEffects;134 135class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,136 InstrItinClass Itin, bit IsComm,137 SDPatternOperator OpNode = null_frag> :138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),139 !strconcat(opstr, "\t$fd, $fs, $ft"),140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,141 HARDFLOAT {142 let isCommutable = IsComm;143}144 145multiclass ABSS_M<string opstr, InstrItinClass Itin,146 SDPatternOperator OpNode= null_frag> {147 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,148 FGR_32;149 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,150 FGR_64 {151 string DecoderNamespace = "MipsFP64";152 }153}154 155multiclass ROUND_M<string opstr, InstrItinClass Itin> {156 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;157 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {158 let DecoderNamespace = "MipsFP64";159 }160}161 162class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,163 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {166 let isMoveReg = 1;167}168 169class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,170 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),172 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {173 let isMoveReg = 1;174}175 176class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,177 InstrItinClass Itin> :178 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),179 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {180 // $fs_in is part of a white lie to work around a widespread bug in the FPU181 // implementation. See expandBuildPairF64 for details.182 let Constraints = "$fs = $fs_in";183}184 185class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,186 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :187 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),188 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,189 HARDFLOAT {190 let DecoderMethod = "DecodeFMem";191 let mayLoad = 1;192}193 194class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,195 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :196 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),197 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {198 let DecoderMethod = "DecodeFMem";199 let mayStore = 1;200}201 202class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,203 SDPatternOperator OpNode = null_frag> :204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),205 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),206 [(set RC:$fd, (OpNode (any_fmul RC:$fs, RC:$ft), RC:$fr))], Itin,207 FrmFR, opstr>, HARDFLOAT;208 209class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,210 SDPatternOperator OpNode = null_frag> :211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),212 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),213 [(set RC:$fd, (any_fsub fpimm0, (OpNode (any_fmul RC:$fs, RC:$ft), RC:$fr)))],214 Itin, FrmFR, opstr>, HARDFLOAT;215 216class LWXC1_FT<string opstr, RegisterOperand DRC,217 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),219 !strconcat(opstr, "\t$fd, ${index}(${base})"),220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,221 FrmFI, opstr>, HARDFLOAT {222 let AddedComplexity = 20;223}224 225class SWXC1_FT<string opstr, RegisterOperand DRC,226 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),228 !strconcat(opstr, "\t$fs, ${index}(${base})"),229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,230 FrmFI, opstr>, HARDFLOAT {231 let AddedComplexity = 20;232}233 234class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,235 SDPatternOperator Op = null_frag> :236 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),237 !strconcat(opstr, "\t$fcc, $offset"),238 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,239 FrmFI, opstr>, HARDFLOAT {240 let isBranch = 1;241 let isTerminator = 1;242 let hasDelaySlot = 1;243 let Defs = [AT];244 let hasFCCRegOperand = 1;245}246 247class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :248 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),249 !strconcat(opstr, "\t$fcc, $offset"), [], Itin,250 FrmFI, opstr>, HARDFLOAT {251 let isBranch = 1;252 let isTerminator = 1;253 let hasDelaySlot = 1;254 let Defs = [AT];255 let hasFCCRegOperand = 1;256}257 258class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,259 SDPatternOperator OpNode = null_frag> :260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),261 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),262 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,263 !strconcat("c.$cond.", typestr)>, HARDFLOAT {264 let Defs = [FCC0];265 let isCodeGenOnly = 1;266 let hasFCCRegOperand = 1;267}268 269 270// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather271// duplicating the instruction definition for MIPS1 - MIPS3, we expand272// c.cond.ft if necessary, and reject it after constructing the273// instruction if the ISA doesn't support it.274class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,275 InstrItinClass itin> :276 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),277 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,278 FrmFR>, HARDFLOAT {279 let isCompare = 1;280 let hasFCCRegOperand = 1;281}282 283multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,284 InstrItinClass itin> {285 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,286 C_COND_FM<fmt, 0> {287 let BaseOpcode = "c.f."#NAME;288 let isCommutable = 1;289 }290 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,291 C_COND_FM<fmt, 1> {292 let BaseOpcode = "c.un."#NAME;293 let isCommutable = 1;294 }295 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,296 C_COND_FM<fmt, 2> {297 let BaseOpcode = "c.eq."#NAME;298 let isCommutable = 1;299 }300 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,301 C_COND_FM<fmt, 3> {302 let BaseOpcode = "c.ueq."#NAME;303 let isCommutable = 1;304 }305 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,306 C_COND_FM<fmt, 4> {307 let BaseOpcode = "c.olt."#NAME;308 }309 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,310 C_COND_FM<fmt, 5> {311 let BaseOpcode = "c.ult."#NAME;312 }313 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,314 C_COND_FM<fmt, 6> {315 let BaseOpcode = "c.ole."#NAME;316 }317 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,318 C_COND_FM<fmt, 7> {319 let BaseOpcode = "c.ule."#NAME;320 }321 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,322 C_COND_FM<fmt, 8> {323 let BaseOpcode = "c.sf."#NAME;324 let isCommutable = 1;325 }326 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,327 C_COND_FM<fmt, 9> {328 let BaseOpcode = "c.ngle."#NAME;329 }330 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,331 C_COND_FM<fmt, 10> {332 let BaseOpcode = "c.seq."#NAME;333 let isCommutable = 1;334 }335 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,336 C_COND_FM<fmt, 11> {337 let BaseOpcode = "c.ngl."#NAME;338 }339 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,340 C_COND_FM<fmt, 12> {341 let BaseOpcode = "c.lt."#NAME;342 }343 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,344 C_COND_FM<fmt, 13> {345 let BaseOpcode = "c.nge."#NAME;346 }347 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,348 C_COND_FM<fmt, 14> {349 let BaseOpcode = "c.le."#NAME;350 }351 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,352 C_COND_FM<fmt, 15> {353 let BaseOpcode = "c.ngt."#NAME;354 }355}356 357let AdditionalPredicates = [NotInMicroMips] in {358defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;359defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,360 FGR_32;361let DecoderNamespace = "MipsFP64" in362defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,363 FGR_64;364}365//===----------------------------------------------------------------------===//366// Floating Point Instructions367//===----------------------------------------------------------------------===//368let AdditionalPredicates = [NotInMicroMips] in {369 def ROUND_W_S : MMRel, StdMMR6Rel,370 ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,371 ABSS_FM<0xc, 16>, ISA_MIPS2;372 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;373 def TRUNC_W_S : MMRel, StdMMR6Rel,374 ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,375 ABSS_FM<0xd, 16>, ISA_MIPS2;376 def CEIL_W_S : MMRel, StdMMR6Rel,377 ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,378 ABSS_FM<0xe, 16>, ISA_MIPS2;379 def FLOOR_W_S : MMRel, StdMMR6Rel,380 ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,381 ABSS_FM<0xf, 16>, ISA_MIPS2;382 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,383 ABSS_FM<0x24, 16>, ISA_MIPS1;384 385 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;386 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;387 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;388 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;389}390 391let AdditionalPredicates = [NotInMicroMips] in {392 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,393 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;394 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,395 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {396 let BaseOpcode = "RECIP_D32";397 }398 let DecoderNamespace = "MipsFP64" in399 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,400 II_RECIP_D>, ABSS_FM<0b010101, 0x11>,401 INSN_MIPS4_32R2, FGR_64;402 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,403 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;404 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,405 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {406 let BaseOpcode = "RSQRT_D32";407 }408 let DecoderNamespace = "MipsFP64" in409 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,410 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,411 INSN_MIPS4_32R2, FGR_64;412}413let DecoderNamespace = "MipsFP64" in {414 let AdditionalPredicates = [NotInMicroMips] in {415 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,416 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64;417 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,418 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64;419 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,420 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64;421 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,422 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64;423 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,424 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64;425 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,426 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64;427 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,428 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64;429 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,430 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64;431 }432}433 434let AdditionalPredicates = [NotInMicroMips] in{435 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,436 ABSS_FM<0x20, 20>, ISA_MIPS1;437 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,438 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;439 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,440 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;441}442 443let AdditionalPredicates = [NotInMicroMips] in {444 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,445 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;446 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,447 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;448 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,449 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;450}451 452let DecoderNamespace = "MipsFP64" in {453 let AdditionalPredicates = [NotInMicroMips] in {454 def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>,455 ADDS_FM<0x0, 22>,456 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;457 def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>,458 ADDS_FM<0x2, 22>,459 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;460 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,461 ADDS_FM<0x2C, 22>,462 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;463 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,464 ADDS_FM<0x2D, 22>,465 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;466 def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,467 ADDS_FM<0x2E, 22>,468 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;469 def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,470 ADDS_FM<0x2F, 22>,471 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;472 def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>,473 ADDS_FM<0x1, 22>,474 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;475 476 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,477 ABSS_FM<0x20, 22>,478 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;479 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,480 ABSS_FM<0x28, 22>,481 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;482 483 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,484 ADDS_FM<0x26, 16>,485 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;486 }487}488 489let DecoderNamespace = "MipsFP64" in {490 let AdditionalPredicates = [HasMips3D] in {491 def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>,492 ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;493 def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>,494 ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;495 def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>,496 ABSS_FM<0x26, 20>,497 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;498 def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>,499 ABSS_FM<0x24, 22>,500 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;501 }502}503 504let DecoderNamespace = "MipsFP64" in {505 let AdditionalPredicates = [NotInMicroMips] in {506 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,507 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;508 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,509 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;510 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,511 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;512 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,513 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;514 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,515 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;516 }517}518 519let isPseudo = 1, isCodeGenOnly = 1 in {520 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;521 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;522 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;523 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;524 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;525}526 527let AdditionalPredicates = [NotInMicroMips, UseAbs] in {528 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,529 ABSS_FM<0x5, 16>, ISA_MIPS1;530 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;531}532 533def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,534 ABSS_FM<0x7, 16>, ISA_MIPS1;535let AdditionalPredicates = [NotInMicroMips] in {536 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;537}538 539let AdditionalPredicates = [NotInMicroMips] in {540 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,541 II_SQRT_S, any_fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;542 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, any_fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;543}544 545// The odd-numbered registers are only referenced when doing loads,546// stores, and moves between floating-point and integer registers.547// When defining instructions, we reference all 32-bit registers,548// regardless of register aliasing.549 550/// Move Control Registers From/To CPU Registers551let AdditionalPredicates = [NotInMicroMips] in {552 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>,553 ISA_MIPS1;554 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,555 ISA_MIPS1;556 557 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,558 bitconvert>, MFC1_FM<0>, ISA_MIPS1;559 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,560 ISA_MIPS1, FGR_64 {561 let DecoderNamespace = "MipsFP64";562 }563 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,564 bitconvert>, MFC1_FM<4>, ISA_MIPS1;565 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,566 ISA_MIPS1, FGR_64 {567 let DecoderNamespace = "MipsFP64";568 }569 570 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,571 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;572 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,573 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {574 let DecoderNamespace = "MipsFP64";575 }576 577 def MTHC1_D32 : MMRel, StdMMR6Rel,578 MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,579 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;580 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,581 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {582 let DecoderNamespace = "MipsFP64";583 }584 585 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,586 bitconvert>, MFC1_FM<5>, ISA_MIPS3;587 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,588 bitconvert>, MFC1_FM<1>, ISA_MIPS3;589 let isMoveReg = 1 in {590 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,591 ABSS_FM<0x6, 16>, ISA_MIPS1;592 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;593 } // isMoveReg594}595 596/// Floating Point Memory Instructions597let AdditionalPredicates = [NotInMicroMips] in {598 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,599 LW_FM<0x31>, ISA_MIPS1;600 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,601 LW_FM<0x39>, ISA_MIPS1;602}603 604let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {605 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,606 LW_FM<0x35>, ISA_MIPS2, FGR_64 {607 let BaseOpcode = "LDC164";608 }609 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,610 LW_FM<0x3d>, ISA_MIPS2, FGR_64;611}612 613let AdditionalPredicates = [NotInMicroMips] in {614 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,615 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {616 let BaseOpcode = "LDC132";617 }618 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,619 LW_FM<0x3d>, ISA_MIPS2, FGR_32;620}621 622// Indexed loads and stores.623// Base register + offset register addressing mode (indicated by "x" in the624// instruction mnemonic).625def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,626 INSN_MIPS4_32R2_NOT_32R6_64R6;627def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,628 INSN_MIPS4_32R2_NOT_32R6_64R6;629 630let AdditionalPredicates = [NotInMicroMips] in {631 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,632 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;633 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,634 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;635}636 637let DecoderNamespace="MipsFP64" in {638 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,639 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;640 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,641 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;642}643 644// Load/store doubleword indexed unaligned.645// FIXME: This instruction should not be defined for FGR_32.646let AdditionalPredicates = [NotInMicroMips] in {647 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,648 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;649 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,650 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;651}652 653let AdditionalPredicates = [NotInMicroMips],654 DecoderNamespace="MipsFP64" in {655 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,656 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;657 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,658 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;659}660 661/// Floating-point Arithmetic662let AdditionalPredicates = [NotInMicroMips] in {663 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, any_fadd>,664 ADDS_FM<0x00, 16>, ISA_MIPS1;665 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, any_fadd>, ADDS_FM<0x00, 17>,666 ISA_MIPS1;667 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, any_fdiv>,668 ADDS_FM<0x03, 16>, ISA_MIPS1;669 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, any_fdiv>, ADDS_FM<0x03, 17>,670 ISA_MIPS1;671 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, any_fmul>,672 ADDS_FM<0x02, 16>, ISA_MIPS1;673 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, any_fmul>, ADDS_FM<0x02, 17>,674 ISA_MIPS1;675 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, any_fsub>,676 ADDS_FM<0x01, 16>, ISA_MIPS1;677 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, any_fsub>, ADDS_FM<0x01, 17>,678 ISA_MIPS1;679}680 681let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {682 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, any_fadd>,683 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;684 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, any_fsub>,685 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;686 687 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, any_fadd>,688 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;689 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, any_fsub>,690 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;691 692 let DecoderNamespace = "MipsFP64" in {693 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, any_fadd>,694 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;695 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, any_fsub>,696 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;697 }698}699 700let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {701 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, any_fadd>,702 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;703 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, any_fsub>,704 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;705 706 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, any_fadd>,707 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;708 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, any_fsub>,709 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;710 711 let DecoderNamespace = "MipsFP64" in {712 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, any_fadd>,713 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;714 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, any_fsub>,715 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;716 }717}718//===----------------------------------------------------------------------===//719// Floating Point Branch Codes720//===----------------------------------------------------------------------===//721// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.722// They must be kept in synch.723def MIPS_BRANCH_F : PatLeaf<(i32 0)>;724def MIPS_BRANCH_T : PatLeaf<(i32 1)>;725 726let AdditionalPredicates = [NotInMicroMips] in {727 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,728 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;729 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,730 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;731 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,732 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;733 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,734 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;735 736/// Floating Point Compare737 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,738 ISA_MIPS1_NOT_32R6_64R6 {739 740 // FIXME: This is a required to work around the fact that these instructions741 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the742 // fcc register set is used directly.743 bits<3> fcc = 0;744 }745 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,746 ISA_MIPS1_NOT_32R6_64R6, FGR_32 {747 // FIXME: This is a required to work around the fact that these instructions748 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the749 // fcc register set is used directly.750 bits<3> fcc = 0;751 }752}753let DecoderNamespace = "MipsFP64" in754def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,755 ISA_MIPS1_NOT_32R6_64R6, FGR_64 {756 // FIXME: This is a required to work around the fact that thiese instructions757 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the758 // fcc register set is used directly.759 bits<3> fcc = 0;760}761 762//===----------------------------------------------------------------------===//763// Floating Point Pseudo-Instructions764//===----------------------------------------------------------------------===//765 766// This pseudo instr gets expanded into 2 mtc1 instrs after register767// allocation.768class BuildPairF64Base<RegisterOperand RO> :769 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),770 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],771 II_MTC1>;772 773def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;774def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;775 776// This pseudo instr gets expanded into 2 mfc1 instrs after register777// allocation.778// if n is 0, lower part of src is extracted.779// if n is 1, higher part of src is extracted.780// This node has associated scheduling information as the pre RA scheduler781// asserts otherwise.782class ExtractElementF64Base<RegisterOperand RO> :783 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),784 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],785 II_MFC1>;786 787def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;788def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;789 790def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),791 (ins FGR32Opnd:$fs, GPR32Opnd:$rs),792 "trunc.w.s\t$fd, $fs, $rs">;793 794def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),795 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),796 "trunc.w.d\t$fd, $fs, $rs">,797 FGR_32, HARDFLOAT;798 799def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),800 (ins FGR64Opnd:$fs, GPR32Opnd:$rs),801 "trunc.w.d\t$fd, $fs, $rs">,802 FGR_64, HARDFLOAT;803 804def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),805 (ins imm64:$fpimm),806 "li.s\t$rd, $fpimm">;807 808def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd),809 (ins imm64:$fpimm),810 "li.s\t$rd, $fpimm">,811 HARDFLOAT;812 813def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),814 (ins imm64:$fpimm),815 "li.d\t$rd, $fpimm">;816 817def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd),818 (ins imm64:$fpimm),819 "li.d\t$rd, $fpimm">,820 FGR_32, HARDFLOAT;821 822def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),823 (ins imm64:$fpimm),824 "li.d\t$rd, $fpimm">,825 FGR_64, HARDFLOAT;826 827def SDC1_M1 : MipsAsmPseudoInst<(outs AFGR64Opnd:$fd),828 (ins mem_simm16:$addr),829 "s.d\t$fd, $addr">,830 FGR_32, ISA_MIPS1, HARDFLOAT;831 832//===----------------------------------------------------------------------===//833// InstAliases.834//===----------------------------------------------------------------------===//835def : MipsInstAlias836 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,837 ISA_MIPS2, HARDFLOAT;838def : MipsInstAlias839 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,840 FGR_32, ISA_MIPS2, HARDFLOAT;841def : MipsInstAlias842 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,843 FGR_64, ISA_MIPS2, HARDFLOAT;844def : MipsInstAlias845 <"s.d $fd, $addr", (SDC1_M1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,846 FGR_32, ISA_MIPS1, HARDFLOAT;847 848def : MipsInstAlias849 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,850 ISA_MIPS2, HARDFLOAT;851def : MipsInstAlias852 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,853 FGR_32, ISA_MIPS2, HARDFLOAT;854def : MipsInstAlias855 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,856 FGR_64, ISA_MIPS2, HARDFLOAT;857 858multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> {859 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"),860 (!cast<Instruction>("C_F_"#NAME) FCC0,861 RC:$fs, RC:$ft), 1>;862 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"),863 (!cast<Instruction>("C_UN_"#NAME) FCC0,864 RC:$fs, RC:$ft), 1>;865 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"),866 (!cast<Instruction>("C_EQ_"#NAME) FCC0,867 RC:$fs, RC:$ft), 1>;868 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"),869 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,870 RC:$fs, RC:$ft), 1>;871 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"),872 (!cast<Instruction>("C_OLT_"#NAME) FCC0,873 RC:$fs, RC:$ft), 1>;874 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"),875 (!cast<Instruction>("C_ULT_"#NAME) FCC0,876 RC:$fs, RC:$ft), 1>;877 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"),878 (!cast<Instruction>("C_OLE_"#NAME) FCC0,879 RC:$fs, RC:$ft), 1>;880 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"),881 (!cast<Instruction>("C_ULE_"#NAME) FCC0,882 RC:$fs, RC:$ft), 1>;883 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"),884 (!cast<Instruction>("C_SF_"#NAME) FCC0,885 RC:$fs, RC:$ft), 1>;886 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"),887 (!cast<Instruction>("C_NGLE_"#NAME) FCC0,888 RC:$fs, RC:$ft), 1>;889 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"),890 (!cast<Instruction>("C_SEQ_"#NAME) FCC0,891 RC:$fs, RC:$ft), 1>;892 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"),893 (!cast<Instruction>("C_NGL_"#NAME) FCC0,894 RC:$fs, RC:$ft), 1>;895 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"),896 (!cast<Instruction>("C_LT_"#NAME) FCC0,897 RC:$fs, RC:$ft), 1>;898 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"),899 (!cast<Instruction>("C_NGE_"#NAME) FCC0,900 RC:$fs, RC:$ft), 1>;901 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"),902 (!cast<Instruction>("C_LE_"#NAME) FCC0,903 RC:$fs, RC:$ft), 1>;904 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"),905 (!cast<Instruction>("C_NGT_"#NAME) FCC0,906 RC:$fs, RC:$ft), 1>;907}908 909multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString,910 Instruction BCFalse, string BCFalseString> {911 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"),912 (BCTrue FCC0, brtarget:$offset), 1>;913 914 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"),915 (BCFalse FCC0, brtarget:$offset), 1>;916}917 918let AdditionalPredicates = [NotInMicroMips] in {919 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,920 ISA_MIPS1_NOT_32R6_64R6;921 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,922 ISA_MIPS1_NOT_32R6_64R6, FGR_32;923 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,924 ISA_MIPS1_NOT_32R6_64R6, FGR_64;925 926 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,927 HARDFLOAT;928 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,929 HARDFLOAT;930}931//===----------------------------------------------------------------------===//932// Floating Point Patterns933//===----------------------------------------------------------------------===//934def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;935def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;936 937def : MipsPat<(f32 (any_sint_to_fp GPR32Opnd:$src)),938 (PseudoCVT_S_W GPR32Opnd:$src)>;939def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),940 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1;941 942def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),943 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;944 945def : MipsPat<(f64 (any_sint_to_fp GPR32Opnd:$src)),946 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;947let AdditionalPredicates = [NotInMicroMips] in {948 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),949 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32;950 def : MipsPat<(f32 (any_fpround AFGR64Opnd:$src)),951 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32;952 def : MipsPat<(f64 (any_fpextend FGR32Opnd:$src)),953 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32;954}955 956def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;957def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,958 FGR_64;959 960def : MipsPat<(f64 (any_sint_to_fp GPR32Opnd:$src)), 961 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;962def : MipsPat<(f32 (any_sint_to_fp GPR64Opnd:$src)),963 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;964def : MipsPat<(f64 (any_sint_to_fp GPR64Opnd:$src)),965 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;966 967def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),968 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;969def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),970 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64;971def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),972 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;973 974let AdditionalPredicates = [NotInMicroMips] in {975 def : MipsPat<(f32 (any_fpround FGR64Opnd:$src)),976 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64;977 def : MipsPat<(f64 (any_fpextend FGR32Opnd:$src)),978 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64;979}980 981// To generate NMADD and NMSUB instructions when fneg node is present982multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> {983 def : MipsPat<(fneg (any_fadd (any_fmul RC:$fs, RC:$ft), RC:$fr)),984 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;985 def : MipsPat<(fneg (any_fsub (any_fmul RC:$fs, RC:$ft), RC:$fr)),986 (Nmsub RC:$fr, RC:$fs, RC:$ft)>;987}988 989let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {990 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>,991 INSN_MIPS4_32R2_NOT_32R6_64R6;992 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>,993 FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;994 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>,995 FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;996}997 998// Patterns for loads/stores with a reg+imm operand.999let AdditionalPredicates = [NotInMicroMips] in {1000 let AddedComplexity = 40 in {1001 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1;1002 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1;1003 1004 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64;1005 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64;1006 1007 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32;1008 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32;1009 }1010}1011