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1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Describe MIPS instructions format11//12// CPU INSTRUCTION FORMATS13//14// opcode - operation code.15// rs - src reg.16// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).17// rd - dst reg, only used on 3 regs instr.18// shamt - only used on shift instructions, contains the shift amount.19// funct - combined with opcode field give us an operation code.20//21//===----------------------------------------------------------------------===//22 23// Format specifies the encoding used by the instruction. This is part of the24// ad-hoc solution used to emit machine instruction encodings by our machine25// code emitter.26class Format<bits<4> val> {27 bits<4> Value = val;28}29 30def Pseudo : Format<0>;31def FrmR : Format<1>;32def FrmI : Format<2>;33def FrmJ : Format<3>;34def FrmFR : Format<4>;35def FrmFI : Format<5>;36def FrmOther : Format<6>; // Instruction w/ a custom format37 38class MMRel;39 40def Std2MicroMips : InstrMapping {41 let FilterClass = "MMRel";42 // Instructions with the same BaseOpcode and isNVStore values form a row.43 let RowFields = ["BaseOpcode"];44 // Instructions with the same predicate sense form a column.45 let ColFields = ["Arch"];46 // The key column is the unpredicated instructions.47 let KeyCol = ["se"];48 // Value columns are PredSense=true and PredSense=false49 let ValueCols = [["se"], ["micromips"]];50}51 52class StdMMR6Rel;53 54def Std2MicroMipsR6 : InstrMapping {55 let FilterClass = "StdMMR6Rel";56 // Instructions with the same BaseOpcode and isNVStore values form a row.57 let RowFields = ["BaseOpcode"];58 // Instructions with the same predicate sense form a column.59 let ColFields = ["Arch"];60 // The key column is the unpredicated instructions.61 let KeyCol = ["se"];62 // Value columns are PredSense=true and PredSense=false63 let ValueCols = [["se"], ["micromipsr6"]];64}65 66class StdArch {67 string Arch = "se";68}69 70// Generic Mips Format71class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,72 InstrItinClass itin, Format f>: Instruction, PredicateControl73{74 field bits<32> Inst;75 Format Form = f;76 77 let Namespace = "Mips";78 79 let Size = 4;80 81 bits<6> Opcode = 0;82 83 // Top 6 bits are the 'opcode' field84 let Inst{31-26} = Opcode;85 86 let OutOperandList = outs;87 let InOperandList = ins;88 89 let AsmString = asmstr;90 let Pattern = pattern;91 let Itinerary = itin;92 93 //94 // Attributes specific to Mips instructions...95 //96 bits<4> FormBits = Form.Value;97 bit isCTI = 0; // Any form of Control Transfer Instruction.98 // Required for MIPSR699 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.100 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is101 // present in MIPS-I to MIPS-III.102 103 // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.104 let TSFlags{3-0} = FormBits;105 let TSFlags{4} = isCTI;106 let TSFlags{5} = hasForbiddenSlot;107 let TSFlags{6} = hasFCCRegOperand;108 109 let DecoderNamespace = "Mips";110}111 112// Mips32/64 Instruction Format113class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,114 InstrItinClass itin, Format f, string opstr = ""> :115 MipsInst<outs, ins, asmstr, pattern, itin, f> {116 let EncodingPredicates = [NotInMips16Mode];117 string BaseOpcode = opstr;118 string Arch;119}120 121// Mips Pseudo Instructions Format122class MipsPseudo<dag outs, dag ins, list<dag> pattern,123 InstrItinClass itin = IIPseudo> :124 MipsInst<outs, ins, "", pattern, itin, Pseudo> {125 let isCodeGenOnly = 1;126 let isPseudo = 1;127}128 129// Mips32/64 Pseudo Instruction Format130class PseudoSE<dag outs, dag ins, list<dag> pattern,131 InstrItinClass itin = IIPseudo> :132 MipsPseudo<outs, ins, pattern, itin> {133 let EncodingPredicates = [NotInMips16Mode];134}135 136// Pseudo-instructions for alternate assembly syntax (never used by codegen).137// These are aliases that require C++ handling to convert to the target138// instruction, while InstAliases can be handled directly by tblgen.139class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:140 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {141 let isPseudo = 1;142 let hasNoSchedulingInfo = 1;143 let Pattern = [];144}145//===----------------------------------------------------------------------===//146// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>147//===----------------------------------------------------------------------===//148 149class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,150 list<dag> pattern, InstrItinClass itin>:151 InstSE<outs, ins, asmstr, pattern, itin, FrmR>152{153 bits<5> rd;154 bits<5> rs;155 bits<5> rt;156 bits<5> shamt;157 bits<6> funct;158 159 let Opcode = op;160 let funct = _funct;161 162 let Inst{25-21} = rs;163 let Inst{20-16} = rt;164 let Inst{15-11} = rd;165 let Inst{10-6} = shamt;166 let Inst{5-0} = funct;167}168 169//===----------------------------------------------------------------------===//170// Format J instruction class in Mips : <|opcode|address|>171//===----------------------------------------------------------------------===//172 173class FJ<bits<6> op> : StdArch174{175 bits<26> target;176 177 bits<32> Inst;178 179 let Inst{31-26} = op;180 let Inst{25-0} = target;181}182 183//===----------------------------------------------------------------------===//184// MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>185//===----------------------------------------------------------------------===//186class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {187 bits<5> rt;188 bits<5> rd;189 bits<3> sel;190 191 bits<32> Inst;192 193 let Inst{31-26} = op;194 let Inst{25-21} = mfmt;195 let Inst{20-16} = rt;196 let Inst{15-11} = rd;197 let Inst{10-8} = guest;198 let Inst{7-3} = 0;199 let Inst{2-0} = sel;200}201 202class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {203 bits<5> rt;204 bits<16> imm16;205 206 bits<32> Inst;207 208 let Inst{31-26} = op;209 let Inst{25-21} = mfmt;210 let Inst{20-16} = rt;211 let Inst{15-0} = imm16;212}213 214class ADD_FM<bits<6> op, bits<6> funct> : StdArch {215 bits<5> rd;216 bits<5> rs;217 bits<5> rt;218 219 bits<32> Inst;220 221 let Inst{31-26} = op;222 let Inst{25-21} = rs;223 let Inst{20-16} = rt;224 let Inst{15-11} = rd;225 let Inst{10-6} = 0;226 let Inst{5-0} = funct;227}228 229class ADDI_FM<bits<6> op> : StdArch {230 bits<5> rs;231 bits<5> rt;232 bits<16> imm16;233 234 bits<32> Inst;235 236 let Inst{31-26} = op;237 let Inst{25-21} = rs;238 let Inst{20-16} = rt;239 let Inst{15-0} = imm16;240}241 242class SRA_FM<bits<6> funct, bit rotate> : StdArch {243 bits<5> rd;244 bits<5> rt;245 bits<5> shamt;246 247 bits<32> Inst;248 249 let Inst{31-26} = 0;250 let Inst{25-22} = 0;251 let Inst{21} = rotate;252 let Inst{20-16} = rt;253 let Inst{15-11} = rd;254 let Inst{10-6} = shamt;255 let Inst{5-0} = funct;256}257 258class SRLV_FM<bits<6> funct, bit rotate> : StdArch {259 bits<5> rd;260 bits<5> rt;261 bits<5> rs;262 263 bits<32> Inst;264 265 let Inst{31-26} = 0;266 let Inst{25-21} = rs;267 let Inst{20-16} = rt;268 let Inst{15-11} = rd;269 let Inst{10-7} = 0;270 let Inst{6} = rotate;271 let Inst{5-0} = funct;272}273 274class BEQ_FM<bits<6> op> : StdArch {275 bits<5> rs;276 bits<5> rt;277 bits<16> offset;278 279 bits<32> Inst;280 281 let Inst{31-26} = op;282 let Inst{25-21} = rs;283 let Inst{20-16} = rt;284 let Inst{15-0} = offset;285}286 287class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {288 bits<5> rs;289 bits<16> offset;290 291 bits<32> Inst;292 293 let Inst{31-26} = op;294 let Inst{25-21} = rs;295 let Inst{20-16} = funct;296 let Inst{15-0} = offset;297}298 299class BBIT_FM<bits<6> op> : StdArch {300 bits<5> rs;301 bits<5> p;302 bits<16> offset;303 304 bits<32> Inst;305 306 let Inst{31-26} = op;307 let Inst{25-21} = rs;308 let Inst{20-16} = p;309 let Inst{15-0} = offset;310}311 312class SLTI_FM<bits<6> op> : StdArch {313 bits<5> rt;314 bits<5> rs;315 bits<16> imm16;316 317 bits<32> Inst;318 319 let Inst{31-26} = op;320 let Inst{25-21} = rs;321 let Inst{20-16} = rt;322 let Inst{15-0} = imm16;323}324 325class MFLO_FM<bits<6> funct> : StdArch {326 bits<5> rd;327 328 bits<32> Inst;329 330 let Inst{31-26} = 0;331 let Inst{25-16} = 0;332 let Inst{15-11} = rd;333 let Inst{10-6} = 0;334 let Inst{5-0} = funct;335}336 337class MTLO_FM<bits<6> funct> : StdArch {338 bits<5> rs;339 340 bits<32> Inst;341 342 let Inst{31-26} = 0;343 let Inst{25-21} = rs;344 let Inst{20-6} = 0;345 let Inst{5-0} = funct;346}347 348class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {349 bits<5> rd;350 bits<5> rt;351 352 bits<32> Inst;353 354 let Inst{31-26} = 0x1f;355 let Inst{25-21} = 0;356 let Inst{20-16} = rt;357 let Inst{15-11} = rd;358 let Inst{10-6} = funct;359 let Inst{5-0} = funct2;360}361 362class CLO_FM<bits<6> funct> : StdArch {363 bits<5> rd;364 bits<5> rs;365 bits<5> rt;366 367 bits<32> Inst;368 369 let Inst{31-26} = 0x1c;370 let Inst{25-21} = rs;371 let Inst{20-16} = rt;372 let Inst{15-11} = rd;373 let Inst{10-6} = 0;374 let Inst{5-0} = funct;375 let rt = rd;376}377 378class LUI_FM : StdArch {379 bits<5> rt;380 bits<16> imm16;381 382 bits<32> Inst;383 384 let Inst{31-26} = 0xf;385 let Inst{25-21} = 0;386 let Inst{20-16} = rt;387 let Inst{15-0} = imm16;388}389 390class JALR_FM {391 bits<5> rd;392 bits<5> rs;393 394 bits<32> Inst;395 396 let Inst{31-26} = 0;397 let Inst{25-21} = rs;398 let Inst{20-16} = 0;399 let Inst{15-11} = rd;400 let Inst{10-6} = 0;401 let Inst{5-0} = 9;402}403 404class BGEZAL_FM<bits<5> funct> : StdArch {405 bits<5> rs;406 bits<16> offset;407 408 bits<32> Inst;409 410 let Inst{31-26} = 1;411 let Inst{25-21} = rs;412 let Inst{20-16} = funct;413 let Inst{15-0} = offset;414}415 416class SYNC_FM : StdArch {417 bits<5> stype;418 419 bits<32> Inst;420 421 let Inst{31-26} = 0;422 let Inst{10-6} = stype;423 let Inst{5-0} = 0xf;424}425 426class SYNCI_FM : StdArch {427 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).428 bits<21> addr;429 bits<5> rs = addr{20-16};430 bits<16> offset = addr{15-0};431 432 bits<32> Inst;433 434 let Inst{31-26} = 0b000001;435 let Inst{25-21} = rs;436 let Inst{20-16} = 0b11111;437 let Inst{15-0} = offset;438}439 440class MULT_FM<bits<6> op, bits<6> funct> : StdArch {441 bits<5> rs;442 bits<5> rt;443 444 bits<32> Inst;445 446 let Inst{31-26} = op;447 let Inst{25-21} = rs;448 let Inst{20-16} = rt;449 let Inst{15-6} = 0;450 let Inst{5-0} = funct;451}452 453class EXT_FM<bits<6> funct> : StdArch {454 bits<5> rt;455 bits<5> rs;456 bits<5> pos;457 bits<5> size;458 459 bits<32> Inst;460 461 let Inst{31-26} = 0x1f;462 let Inst{25-21} = rs;463 let Inst{20-16} = rt;464 let Inst{15-11} = size;465 let Inst{10-6} = pos;466 let Inst{5-0} = funct;467}468 469class RDHWR_FM : StdArch {470 bits<5> rt;471 bits<5> rd;472 bits<3> sel;473 474 bits<32> Inst;475 476 let Inst{31-26} = 0x1f;477 let Inst{25-21} = 0;478 let Inst{20-16} = rt;479 let Inst{15-11} = rd;480 let Inst{10-9} = 0b00;481 let Inst{8-6} = sel;482 let Inst{5-0} = 0x3b;483}484 485class TEQ_FM<bits<6> funct> : StdArch {486 bits<5> rs;487 bits<5> rt;488 bits<10> code_;489 490 bits<32> Inst;491 492 let Inst{31-26} = 0;493 let Inst{25-21} = rs;494 let Inst{20-16} = rt;495 let Inst{15-6} = code_;496 let Inst{5-0} = funct;497}498 499class TEQI_FM<bits<5> funct> : StdArch {500 bits<5> rs;501 bits<16> imm16;502 503 bits<32> Inst;504 505 let Inst{31-26} = 1;506 let Inst{25-21} = rs;507 let Inst{20-16} = funct;508 let Inst{15-0} = imm16;509}510 511class WAIT_FM : StdArch {512 bits<32> Inst;513 514 let Inst{31-26} = 0x10;515 let Inst{25} = 1;516 let Inst{24-6} = 0;517 let Inst{5-0} = 0x20;518}519 520class EXTS_FM<bits<6> funct> : StdArch {521 bits<5> rt;522 bits<5> rs;523 bits<5> pos;524 bits<5> lenm1;525 526 bits<32> Inst;527 528 let Inst{31-26} = 0x1c;529 let Inst{25-21} = rs;530 let Inst{20-16} = rt;531 let Inst{15-11} = lenm1;532 let Inst{10-6} = pos;533 let Inst{5-0} = funct;534}535 536class MTMR_FM<bits<6> funct> : StdArch {537 bits<5> rs;538 539 bits<32> Inst;540 541 let Inst{31-26} = 0x1c;542 let Inst{25-21} = rs;543 let Inst{20-6} = 0;544 let Inst{5-0} = funct;545}546 547class POP_FM<bits<6> funct> : StdArch {548 bits<5> rd;549 bits<5> rs;550 551 bits<32> Inst;552 553 let Inst{31-26} = 0x1c;554 let Inst{25-21} = rs;555 let Inst{20-16} = 0;556 let Inst{15-11} = rd;557 let Inst{10-6} = 0;558 let Inst{5-0} = funct;559}560 561class SEQ_FM<bits<6> funct> : StdArch {562 bits<5> rd;563 bits<5> rs;564 bits<5> rt;565 566 bits<32> Inst;567 568 let Inst{31-26} = 0x1c;569 let Inst{25-21} = rs;570 let Inst{20-16} = rt;571 let Inst{15-11} = rd;572 let Inst{10-6} = 0;573 let Inst{5-0} = funct;574}575 576class SEQI_FM<bits<6> funct> : StdArch {577 bits<5> rs;578 bits<5> rt;579 bits<10> imm10;580 581 bits<32> Inst;582 583 let Inst{31-26} = 0x1c;584 let Inst{25-21} = rs;585 let Inst{20-16} = rt;586 let Inst{15-6} = imm10;587 let Inst{5-0} = funct;588}589 590class SAA_FM<bits<6> funct> : StdArch {591 bits<5> rt;592 bits<5> rs;593 594 bits<32> Inst;595 596 let Inst{31-26} = 0x1c;597 let Inst{25-21} = rs;598 let Inst{20-16} = rt;599 let Inst{15-6} = 0;600 let Inst{5-0} = funct;601}602 603//===----------------------------------------------------------------------===//604// System calls format <op|code_|funct>605//===----------------------------------------------------------------------===//606 607class SYS_FM<bits<6> funct> : StdArch608{609 bits<20> code_;610 bits<32> Inst;611 let Inst{31-26} = 0x0;612 let Inst{25-6} = code_;613 let Inst{5-0} = funct;614}615 616//===----------------------------------------------------------------------===//617// Break instruction format <op|code_1|funct>618//===----------------------------------------------------------------------===//619 620class BRK_FM<bits<6> funct> : StdArch621{622 bits<10> code_1;623 bits<10> code_2;624 bits<32> Inst;625 let Inst{31-26} = 0x0;626 let Inst{25-16} = code_1;627 let Inst{15-6} = code_2;628 let Inst{5-0} = funct;629}630 631//===----------------------------------------------------------------------===//632// Exception return format <Cop0|1|0|funct>633//===----------------------------------------------------------------------===//634 635class ER_FM<bits<6> funct, bit LLBit> : StdArch636{637 bits<32> Inst;638 let Inst{31-26} = 0x10;639 let Inst{25} = 1;640 let Inst{24-7} = 0;641 let Inst{6} = LLBit;642 let Inst{5-0} = funct;643}644 645//===----------------------------------------------------------------------===//646// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>647//===----------------------------------------------------------------------===//648 649class EI_FM<bits<1> sc> : StdArch650{651 bits<32> Inst;652 bits<5> rt;653 let Inst{31-26} = 0x10;654 let Inst{25-21} = 0xb;655 let Inst{20-16} = rt;656 let Inst{15-11} = 0xc;657 let Inst{10-6} = 0;658 let Inst{5} = sc;659 let Inst{4-0} = 0;660}661 662//===----------------------------------------------------------------------===//663//664// FLOATING POINT INSTRUCTION FORMATS665//666// opcode - operation code.667// fs - src reg.668// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).669// fd - dst reg, only used on 3 regs instr.670// fmt - double or single precision.671// funct - combined with opcode field give us an operation code.672//673//===----------------------------------------------------------------------===//674 675//===----------------------------------------------------------------------===//676// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>677//===----------------------------------------------------------------------===//678 679class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {680 bits<5> fd;681 bits<5> fs;682 bits<5> ft;683 684 bits<32> Inst;685 686 let Inst{31-26} = 0x11;687 let Inst{25-21} = fmt;688 let Inst{20-16} = ft;689 let Inst{15-11} = fs;690 let Inst{10-6} = fd;691 let Inst{5-0} = funct;692}693 694class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {695 bits<5> fd;696 bits<5> fs;697 698 bits<32> Inst;699 700 let Inst{31-26} = 0x11;701 let Inst{25-21} = fmt;702 let Inst{20-16} = 0;703 let Inst{15-11} = fs;704 let Inst{10-6} = fd;705 let Inst{5-0} = funct;706}707 708class MFC1_FM<bits<5> funct> : StdArch {709 bits<5> rt;710 bits<5> fs;711 712 bits<32> Inst;713 714 let Inst{31-26} = 0x11;715 let Inst{25-21} = funct;716 let Inst{20-16} = rt;717 let Inst{15-11} = fs;718 let Inst{10-0} = 0;719}720 721class LW_FM<bits<6> op> : StdArch {722 bits<5> rt;723 bits<21> addr;724 725 bits<32> Inst;726 727 let Inst{31-26} = op;728 let Inst{25-21} = addr{20-16};729 let Inst{20-16} = rt;730 let Inst{15-0} = addr{15-0};731}732 733class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {734 bits<5> fd;735 bits<5> fr;736 bits<5> fs;737 bits<5> ft;738 739 bits<32> Inst;740 741 let Inst{31-26} = 0x13;742 let Inst{25-21} = fr;743 let Inst{20-16} = ft;744 let Inst{15-11} = fs;745 let Inst{10-6} = fd;746 let Inst{5-3} = funct;747 let Inst{2-0} = fmt;748}749 750class LWXC1_FM<bits<6> funct> : StdArch {751 bits<5> fd;752 bits<5> base;753 bits<5> index;754 755 bits<32> Inst;756 757 let Inst{31-26} = 0x13;758 let Inst{25-21} = base;759 let Inst{20-16} = index;760 let Inst{15-11} = 0;761 let Inst{10-6} = fd;762 let Inst{5-0} = funct;763}764 765class SWXC1_FM<bits<6> funct> : StdArch {766 bits<5> fs;767 bits<5> base;768 bits<5> index;769 770 bits<32> Inst;771 772 let Inst{31-26} = 0x13;773 let Inst{25-21} = base;774 let Inst{20-16} = index;775 let Inst{15-11} = fs;776 let Inst{10-6} = 0;777 let Inst{5-0} = funct;778}779 780class BC1F_FM<bit nd, bit tf> : StdArch {781 bits<3> fcc;782 bits<16> offset;783 784 bits<32> Inst;785 786 let Inst{31-26} = 0x11;787 let Inst{25-21} = 0x8;788 let Inst{20-18} = fcc;789 let Inst{17} = nd;790 let Inst{16} = tf;791 let Inst{15-0} = offset;792}793 794class CEQS_FM<bits<5> fmt> : StdArch {795 bits<5> fs;796 bits<5> ft;797 bits<3> fcc;798 bits<4> cond;799 800 bits<32> Inst;801 802 let Inst{31-26} = 0x11;803 let Inst{25-21} = fmt;804 let Inst{20-16} = ft;805 let Inst{15-11} = fs;806 let Inst{10-8} = fcc;807 let Inst{7-4} = 0x3;808 let Inst{3-0} = cond;809}810 811class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {812 let cond = c;813}814 815class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {816 bits<5> fd;817 bits<5> fs;818 bits<5> rt;819 820 bits<32> Inst;821 822 let Inst{31-26} = 0x11;823 let Inst{25-21} = fmt;824 let Inst{20-16} = rt;825 let Inst{15-11} = fs;826 let Inst{10-6} = fd;827 let Inst{5-0} = funct;828}829 830class CMov_F_I_FM<bit tf> : StdArch {831 bits<5> rd;832 bits<5> rs;833 bits<3> fcc;834 835 bits<32> Inst;836 837 let Inst{31-26} = 0;838 let Inst{25-21} = rs;839 let Inst{20-18} = fcc;840 let Inst{17} = 0;841 let Inst{16} = tf;842 let Inst{15-11} = rd;843 let Inst{10-6} = 0;844 let Inst{5-0} = 1;845}846 847class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {848 bits<5> fd;849 bits<5> fs;850 bits<3> fcc;851 852 bits<32> Inst;853 854 let Inst{31-26} = 0x11;855 let Inst{25-21} = fmt;856 let Inst{20-18} = fcc;857 let Inst{17} = 0;858 let Inst{16} = tf;859 let Inst{15-11} = fs;860 let Inst{10-6} = fd;861 let Inst{5-0} = 0x11;862}863 864class BARRIER_FM<bits<5> op> : StdArch {865 bits<32> Inst;866 867 let Inst{31-26} = 0; // SPECIAL868 let Inst{25-21} = 0;869 let Inst{20-16} = 0; // rt = 0870 let Inst{15-11} = 0; // rd = 0871 let Inst{10-6} = op; // Operation872 let Inst{5-0} = 0; // SLL873}874 875class SDBBP_FM : StdArch {876 bits<20> code_;877 878 bits<32> Inst;879 880 let Inst{31-26} = 0b011100; // SPECIAL2881 let Inst{25-6} = code_;882 let Inst{5-0} = 0b111111; // SDBBP883}884 885class JR_HB_FM<bits<6> op> : StdArch{886 bits<5> rs;887 888 bits<32> Inst;889 890 let Inst{31-26} = 0; // SPECIAL891 let Inst{25-21} = rs;892 let Inst{20-11} = 0;893 let Inst{10} = 1;894 let Inst{9-6} = 0;895 let Inst{5-0} = op;896}897 898class JALR_HB_FM<bits<6> op> : StdArch {899 bits<5> rd;900 bits<5> rs;901 902 bits<32> Inst;903 904 let Inst{31-26} = 0; // SPECIAL905 let Inst{25-21} = rs;906 let Inst{20-16} = 0;907 let Inst{15-11} = rd;908 let Inst{10} = 1;909 let Inst{9-6} = 0;910 let Inst{5-0} = op;911}912 913class COP0_TLB_FM<bits<6> op> : StdArch {914 bits<32> Inst;915 916 let Inst{31-26} = 0x10; // COP0917 let Inst{25} = 1; // CO918 let Inst{24-6} = 0;919 let Inst{5-0} = op; // Operation920}921 922class CACHEOP_FM<bits<6> op> : StdArch {923 bits<21> addr;924 bits<5> hint;925 bits<5> base = addr{20-16};926 bits<16> offset = addr{15-0};927 928 bits<32> Inst;929 930 let Inst{31-26} = op;931 let Inst{25-21} = base;932 let Inst{20-16} = hint;933 let Inst{15-0} = offset;934}935 936class HYPCALL_FM<bits<6> op> : StdArch {937 bits<10> code_;938 939 bits<32> Inst;940 941 let Inst{31-26} = 0b010000;942 let Inst{25} = 1;943 let Inst{20-11} = code_;944 let Inst{5-0} = op;945}946