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1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the Mips implementation of the TargetInstrInfo class.10//11// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in12// order for MipsLongBranch pass to work correctly when the code has inline13// assembly. The returned value doesn't have to be the asm instruction's exact14// size in bytes; MipsLongBranch only expects it to be the correct upper bound.15//===----------------------------------------------------------------------===//16 17#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H18#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H19 20#include "MCTargetDesc/MipsMCTargetDesc.h"21#include "Mips.h"22#include "MipsRegisterInfo.h"23#include "llvm/ADT/ArrayRef.h"24#include "llvm/CodeGen/MachineBasicBlock.h"25#include "llvm/CodeGen/MachineInstrBuilder.h"26#include "llvm/CodeGen/MachineMemOperand.h"27#include "llvm/CodeGen/TargetInstrInfo.h"28#include <cstdint>29 30#define GET_INSTRINFO_HEADER31#include "MipsGenInstrInfo.inc"32 33namespace llvm {34 35class MachineInstr;36class MachineOperand;37class MipsSubtarget;38class TargetRegisterClass;39class TargetRegisterInfo;40 41class MipsInstrInfo : public MipsGenInstrInfo {42 virtual void anchor();43 44protected:45 const MipsSubtarget &Subtarget;46 unsigned UncondBrOpc;47 48public:49 enum BranchType {50 BT_None, // Couldn't analyze branch.51 BT_NoBranch, // No branches found.52 BT_Uncond, // One unconditional branch.53 BT_Cond, // One conditional branch.54 BT_CondUncond, // A conditional branch followed by an unconditional branch.55 BT_Indirect // One indirct branch.56 };57 58 explicit MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI,59 unsigned UncondBrOpc);60 61 MCInst getNop() const override;62 63 static const MipsInstrInfo *create(MipsSubtarget &STI);64 65 /// Branch Analysis66 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,67 MachineBasicBlock *&FBB,68 SmallVectorImpl<MachineOperand> &Cond,69 bool AllowModify) const override;70 71 unsigned removeBranch(MachineBasicBlock &MBB,72 int *BytesRemoved = nullptr) const override;73 74 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,75 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,76 const DebugLoc &DL,77 int *BytesAdded = nullptr) const override;78 79 bool80 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;81 82 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,83 MachineBasicBlock *&FBB,84 SmallVectorImpl<MachineOperand> &Cond,85 bool AllowModify,86 SmallVectorImpl<MachineInstr *> &BranchInstrs) const;87 88 /// Determine the opcode of a non-delay slot form for a branch if one exists.89 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;90 91 /// Determine if the branch target is in range.92 bool isBranchOffsetInRange(unsigned BranchOpc,93 int64_t BrOffset) const override;94 95 bool SafeAfterMflo(const MachineInstr &MI) const;96 97 /// Predicate to determine if an instruction can go in a forbidden slot.98 bool SafeInForbiddenSlot(const MachineInstr &MI) const;99 100 /// Predicate to determine if an instruction can go in an FPU delay slot.101 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,102 const MachineInstr &FPUMI) const;103 104 /// Predicate to determine if an instruction can go in a load delay slot.105 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,106 const MachineInstr &LoadMI) const;107 108 bool IsMfloOrMfhi(const MachineInstr &MI) const;109 110 /// Predicate to determine if an instruction has a forbidden slot.111 bool HasForbiddenSlot(const MachineInstr &MI) const;112 113 /// Predicate to determine if an instruction has an FPU delay slot.114 bool HasFPUDelaySlot(const MachineInstr &MI) const;115 116 /// Predicate to determine if an instruction has a load delay slot.117 bool HasLoadDelaySlot(const MachineInstr &MI) const;118 119 bool isAsCheapAsAMove(const MachineInstr &MI) const override;120 121 /// Insert nop instruction when hazard condition is found122 void insertNoop(MachineBasicBlock &MBB,123 MachineBasicBlock::iterator MI) const override;124 125 /// Insert an ISA appropriate `nop`.126 // FIXME: Add support for MIPS16e.127 MachineInstrBuilder insertNop(MachineBasicBlock &MBB,128 MachineBasicBlock::iterator MI,129 DebugLoc DL) const;130 131 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As132 /// such, whenever a client has an instance of instruction info, it should133 /// always be able to get register info as well (through this method).134 const MipsRegisterInfo &getRegisterInfo() const {135 return static_cast<const MipsRegisterInfo &>(136 TargetInstrInfo::getRegisterInfo());137 }138 139 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;140 141 virtual bool isBranchWithImm(unsigned Opc) const {142 return false;143 }144 145 /// Return the number of bytes of code the specified instruction may be.146 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;147 148 void storeRegToStackSlot(149 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,150 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,151 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {152 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, 0, Flags);153 }154 155 void loadRegFromStackSlot(156 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,157 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,158 Register VReg,159 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {160 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, 0, Flags);161 }162 163 virtual void164 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,165 Register SrcReg, bool isKill, int FrameIndex,166 const TargetRegisterClass *RC, int64_t Offset,167 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;168 169 virtual void loadRegFromStack(170 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,171 int FrameIndex, const TargetRegisterClass *RC, int64_t Offset,172 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;173 174 virtual void adjustStackPtr(unsigned SP, int64_t Amount,175 MachineBasicBlock &MBB,176 MachineBasicBlock::iterator I) const = 0;177 178 /// Create an instruction which has the same operands and memory operands179 /// as MI but has a new opcode.180 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,181 MachineBasicBlock::iterator I) const;182 183 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,184 unsigned &SrcOpIdx2) const override;185 186 /// Perform target specific instruction verification.187 bool verifyInstruction(const MachineInstr &MI,188 StringRef &ErrInfo) const override;189 190 std::pair<unsigned, unsigned>191 decomposeMachineOperandsTargetFlags(unsigned TF) const override;192 193 ArrayRef<std::pair<unsigned, const char *>>194 getSerializableDirectMachineOperandTargetFlags() const override;195 196 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,197 Register Reg) const override;198 199 std::optional<ParamLoadedValue>200 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;201 202protected:203 bool isZeroImm(const MachineOperand &op) const;204 205 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,206 MachineMemOperand::Flags Flags) const;207 208private:209 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;210 211 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,212 MachineBasicBlock *&BB,213 SmallVectorImpl<MachineOperand> &Cond) const;214 215 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,216 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;217};218 219/// Create MipsInstrInfo objects.220const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);221const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);222 223namespace Mips {224// Mask assignments for floating-point.225enum FClassMask {226 FClassMaskSignalingNaN = 1 << 0,227 FClassMaskQuietNaN = 1 << 1,228 FClassMaskNegativeInfinity = 1 << 2,229 FClassMaskNegativeNormal = 1 << 3,230 FClassMaskNegativeSubnormal = 1 << 4,231 FClassMaskNegativeZero = 1 << 5,232 FClassMaskPositiveInfinity = 1 << 6,233 FClassMaskPositiveNormal = 1 << 7,234 FClassMaskPositiveSubnormal = 1 << 8,235 FClassMaskPositiveZero = 1 << 9236};237 238} // namespace Mips239 240} // end namespace llvm241 242#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H243