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1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the Mips implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13 14//===----------------------------------------------------------------------===//15// Mips profiles and nodes16//===----------------------------------------------------------------------===//17include "MipsInstrCompiler.td"18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,21 SDTCisSameAs<1, 2>,22 SDTCisSameAs<3, 4>,23 SDTCisInt<4>]>;24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,30 SDTCisSameAs<1, 2>]>;31def SDT_MipsMAddMSub : SDTypeProfile<1, 3,32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,44 SDTCisSameAs<0, 4>]>;45 46def SDTMipsLoadLR : SDTypeProfile<1, 2,47 [SDTCisInt<0>, SDTCisPtrTy<1>,48 SDTCisSameAs<0, 2>]>;49 50// Call51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,53 SDNPVariadic]>;54 55// Tail call56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;58 59// Hi and Lo nodes are used to handle global addresses. Used on60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol61// static model. (nothing to do with Mips Registers Hi and Lo)62 63// Hi is the odd node out, on MIPS64 it can expand to either daddiu when64// using static relocations with 64 bit symbols, or lui when using 32 bit65// symbols.66def MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>;67def MipsHighest : SDNode<"MipsISD::Highest", SDTIntUnaryOp>;68def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;69def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;70 71def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;72 73// Hi node for accessing the GOT.74def MipsGotHi : SDNode<"MipsISD::GotHi", SDTIntUnaryOp>;75 76// Hi node for handling TLS offsets77def MipsTlsHi : SDNode<"MipsISD::TlsHi", SDTIntUnaryOp>;78 79// Thread pointer80def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;81 82// Return83def MipsRet : SDNode<"MipsISD::Ret", SDTNone,84 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;85 86def MipsERet : SDNode<"MipsISD::ERet", SDTNone,87 [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;88 89// These are target-independent nodes, but have target-specific formats.90def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,91 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;92def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,93 [SDNPHasChain, SDNPSideEffect,94 SDNPOptInGlue, SDNPOutGlue]>;95 96// Nodes used to extract LO/HI registers.97def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;98def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;99 100// Node used to insert 32-bit integers to LOHI register pair.101def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;102 103// Mult nodes.104def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;105def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;106 107// MAdd*/MSub* nodes108def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;109def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;110def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;111def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;112 113// DivRem(u) nodes114def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;115def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;116def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,117 [SDNPOutGlue]>;118def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,119 [SDNPOutGlue]>;120 121// Target constant nodes that are not part of any isel patterns and remain122// unchanged can cause instructions with illegal operands to be emitted.123// Wrapper node patterns give the instruction selector a chance to replace124// target constant nodes that would otherwise remain unchanged with ADDiu125// nodes. Without these wrapper node patterns, the following conditional move126// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is127// compiled:128// movn %got(d)($gp), %got(c)($gp), $4129// This instruction is illegal since movn can take only register operands.130 131def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;132 133def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;134 135def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;136def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;137def MipsCIns : SDNode<"MipsISD::CIns", SDT_Ext>;138 139def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;141def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,142 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;143def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;145def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,146 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;147def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,148 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;149def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,150 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;151def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,152 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;153def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,154 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;155 156//===----------------------------------------------------------------------===//157// Mips Instruction Predicate Definitions.158//===----------------------------------------------------------------------===//159// FIXME: Move to Mips.td160 161def HasMips2 : Predicate<"Subtarget->hasMips2()">,162 AssemblerPredicate<(all_of FeatureMips2)>;163def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,164 AssemblerPredicate<(all_of FeatureMips3_32)>;165def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,166 AssemblerPredicate<(all_of FeatureMips3_32r2)>;167def HasMips3 : Predicate<"Subtarget->hasMips3()">,168 AssemblerPredicate<(all_of FeatureMips3)>;169def NotMips3 : Predicate<"!Subtarget->hasMips3()">,170 AssemblerPredicate<(all_of (not FeatureMips3))>;171def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,172 AssemblerPredicate<(all_of FeatureMips4_32)>;173def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,174 AssemblerPredicate<(all_of (not FeatureMips4_32))>;175def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,176 AssemblerPredicate<(all_of FeatureMips4_32r2)>;177def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,178 AssemblerPredicate<(all_of FeatureMips5_32r2)>;179def HasMips32 : Predicate<"Subtarget->hasMips32()">,180 AssemblerPredicate<(all_of FeatureMips32)>;181def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,182 AssemblerPredicate<(all_of FeatureMips32r2)>;183def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,184 AssemblerPredicate<(all_of FeatureMips32r5)>;185def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,186 AssemblerPredicate<(all_of FeatureMips32r6)>;187def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,188 AssemblerPredicate<(all_of (not FeatureMips32r6))>;189def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,190 AssemblerPredicate<(all_of FeatureGP64Bit)>;191def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,192 AssemblerPredicate<(all_of (not FeatureGP64Bit))>;193def HasMips64 : Predicate<"Subtarget->hasMips64()">,194 AssemblerPredicate<(all_of FeatureMips64)>;195def NotMips64 : Predicate<"!Subtarget->hasMips64()">,196 AssemblerPredicate<(all_of (not FeatureMips64))>;197def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,198 AssemblerPredicate<(all_of FeatureMips64r2)>;199def HasMips64r5 : Predicate<"Subtarget->hasMips64r5()">,200 AssemblerPredicate<(all_of FeatureMips64r5)>;201def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,202 AssemblerPredicate<(all_of FeatureMips64r6)>;203def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,204 AssemblerPredicate<(all_of (not FeatureMips64r6))>;205def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,206 AssemblerPredicate<(all_of FeatureMips16)>;207def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,208 AssemblerPredicate<(all_of (not FeatureMips16))>;209def HasCnMips : Predicate<"Subtarget->hasCnMips()">,210 AssemblerPredicate<(all_of FeatureCnMips)>;211def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,212 AssemblerPredicate<(all_of (not FeatureCnMips))>;213def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">,214 AssemblerPredicate<(all_of FeatureCnMipsP)>;215def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">,216 AssemblerPredicate<(all_of (not FeatureCnMipsP))>;217def IsSym32 : Predicate<"Subtarget->hasSym32()">,218 AssemblerPredicate<(all_of FeatureSym32)>;219def IsSym64 : Predicate<"!Subtarget->hasSym32()">,220 AssemblerPredicate<(all_of (not FeatureSym32))>;221def IsN64 : Predicate<"Subtarget->isABI_N64()">;222def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">;223def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;224def RelocPIC : Predicate<"TM.isPositionIndependent()">;225def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;226def UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||"227 "TM.Options.NoNaNsFPMath">;228def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,229 AssemblerPredicate<(all_of (not FeatureMips16))>;230def NotDSP : Predicate<"!Subtarget->hasDSP()">;231def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,232 AssemblerPredicate<(all_of FeatureMicroMips)>;233def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,234 AssemblerPredicate<(all_of (not FeatureMicroMips))>;235def IsLE : Predicate<"Subtarget->isLittle()">;236def IsBE : Predicate<"!Subtarget->isLittle()">;237def UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>;238def HasEVA : Predicate<"Subtarget->hasEVA()">,239 AssemblerPredicate<(all_of FeatureEVA)>;240def HasMSA : Predicate<"Subtarget->hasMSA()">,241 AssemblerPredicate<(all_of FeatureMSA)>;242def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,243 AssemblerPredicate<(all_of (not FeatureNoMadd4))>;244def HasMT : Predicate<"Subtarget->hasMT()">,245 AssemblerPredicate<(all_of FeatureMT)>;246def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,247 AssemblerPredicate<(all_of FeatureUseIndirectJumpsHazard)>;248def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">,249 AssemblerPredicate<(all_of (not FeatureUseIndirectJumpsHazard))>;250def HasCRC : Predicate<"Subtarget->hasCRC()">,251 AssemblerPredicate<(all_of FeatureCRC)>;252def HasVirt : Predicate<"Subtarget->hasVirt()">,253 AssemblerPredicate<(all_of FeatureVirt)>;254def HasGINV : Predicate<"Subtarget->hasGINV()">,255 AssemblerPredicate<(all_of FeatureGINV)>;256// TODO: Add support for FPOpFusion::Standard257def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion =="258 " FPOpFusion::Fast">;259//===----------------------------------------------------------------------===//260// Mips GPR size adjectives.261// They are mutually exclusive.262//===----------------------------------------------------------------------===//263 264class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }265class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }266 267class PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; }268class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; }269 270//===----------------------------------------------------------------------===//271// Mips Symbol size adjectives.272// They are mutally exculsive.273//===----------------------------------------------------------------------===//274 275class SYM_32 { list<Predicate> SYMPredicates = [IsSym32]; }276class SYM_64 { list<Predicate> SYMPredicates = [IsSym64]; }277 278//===----------------------------------------------------------------------===//279// Mips ISA/ASE membership and instruction group membership adjectives.280// They are mutually exclusive.281//===----------------------------------------------------------------------===//282 283// FIXME: I'd prefer to use additive predicates to build the instruction sets284// but we are short on assembler feature bits at the moment. Using a285// subtractive predicate will hopefully keep us under the 32 predicate286// limit long enough to develop an alternative way to handle P1||P2287// predicates.288class ISA_MIPS1 {289 list<Predicate> EncodingPredicates = [HasStdEnc];290}291class ISA_MIPS1_NOT_MIPS3 {292 list<Predicate> InsnPredicates = [NotMips3];293 list<Predicate> EncodingPredicates = [HasStdEnc];294}295class ISA_MIPS1_NOT_4_32 {296 list<Predicate> InsnPredicates = [NotMips4_32];297 list<Predicate> EncodingPredicates = [HasStdEnc];298}299class ISA_MIPS1_NOT_32R6_64R6 {300 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];301 list<Predicate> EncodingPredicates = [HasStdEnc];302}303class ISA_MIPS2 {304 list<Predicate> InsnPredicates = [HasMips2];305 list<Predicate> EncodingPredicates = [HasStdEnc];306}307class ISA_MIPS2_NOT_32R6_64R6 {308 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];309 list<Predicate> EncodingPredicates = [HasStdEnc];310}311class ISA_MIPS3 {312 list<Predicate> InsnPredicates = [HasMips3];313 list<Predicate> EncodingPredicates = [HasStdEnc];314}315class ISA_MIPS3_NOT_32R6_64R6 {316 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];317 list<Predicate> EncodingPredicates = [HasStdEnc];318}319class ISA_MIPS32 {320 list<Predicate> InsnPredicates = [HasMips32];321 list<Predicate> EncodingPredicates = [HasStdEnc];322}323class ISA_MIPS32_NOT_32R6_64R6 {324 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];325 list<Predicate> EncodingPredicates = [HasStdEnc];326}327class ISA_MIPS32R2 {328 list<Predicate> InsnPredicates = [HasMips32r2];329 list<Predicate> EncodingPredicates = [HasStdEnc];330}331class ISA_MIPS32R2_NOT_32R6_64R6 {332 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];333 list<Predicate> EncodingPredicates = [HasStdEnc];334}335class ISA_MIPS32R5 {336 list<Predicate> InsnPredicates = [HasMips32r5];337 list<Predicate> EncodingPredicates = [HasStdEnc];338}339class ISA_MIPS64 {340 list<Predicate> InsnPredicates = [HasMips64];341 list<Predicate> EncodingPredicates = [HasStdEnc];342}343class ISA_MIPS64_NOT_64R6 {344 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];345 list<Predicate> EncodingPredicates = [HasStdEnc];346}347class ISA_MIPS64R2 {348 list<Predicate> InsnPredicates = [HasMips64r2];349 list<Predicate> EncodingPredicates = [HasStdEnc];350}351class ISA_MIPS64R5 {352 list<Predicate> InsnPredicates = [HasMips64r5];353 list<Predicate> EncodingPredicates = [HasStdEnc];354}355class ISA_MIPS32R6 {356 list<Predicate> InsnPredicates = [HasMips32r6];357 list<Predicate> EncodingPredicates = [HasStdEnc];358}359class ISA_MIPS64R6 {360 list<Predicate> InsnPredicates = [HasMips64r6];361 list<Predicate> EncodingPredicates = [HasStdEnc];362}363class ISA_MICROMIPS {364 list<Predicate> EncodingPredicates = [InMicroMips];365}366class ISA_MICROMIPS32R5 {367 list<Predicate> InsnPredicates = [HasMips32r5];368 list<Predicate> EncodingPredicates = [InMicroMips];369}370class ISA_MICROMIPS32R6 {371 list<Predicate> InsnPredicates = [HasMips32r6];372 list<Predicate> EncodingPredicates = [InMicroMips];373}374class ISA_MICROMIPS64R6 {375 list<Predicate> InsnPredicates = [HasMips64r6];376 list<Predicate> EncodingPredicates = [InMicroMips];377}378class ISA_MICROMIPS32_NOT_MIPS32R6 {379 list<Predicate> InsnPredicates = [NotMips32r6];380 list<Predicate> EncodingPredicates = [InMicroMips];381}382class ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; }383 384// The portions of MIPS-III that were also added to MIPS32385class INSN_MIPS3_32 {386 list<Predicate> InsnPredicates = [HasMips3_32];387 list<Predicate> EncodingPredicates = [HasStdEnc];388}389 390// The portions of MIPS-III that were also added to MIPS32 but were removed in391// MIPS32r6 and MIPS64r6.392class INSN_MIPS3_32_NOT_32R6_64R6 {393 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];394 list<Predicate> EncodingPredicates = [HasStdEnc];395}396 397// The portions of MIPS-III that were also added to MIPS32398class INSN_MIPS3_32R2 {399 list<Predicate> InsnPredicates = [HasMips3_32r2];400 list<Predicate> EncodingPredicates = [HasStdEnc];401}402 403// The portions of MIPS-IV that were also added to MIPS32.404class INSN_MIPS4_32 {405 list <Predicate> InsnPredicates = [HasMips4_32];406 list<Predicate> EncodingPredicates = [HasStdEnc];407}408 409// The portions of MIPS-IV that were also added to MIPS32 but were removed in410// MIPS32r6 and MIPS64r6.411class INSN_MIPS4_32_NOT_32R6_64R6 {412 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];413 list<Predicate> EncodingPredicates = [HasStdEnc];414}415 416// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in417// MIPS32r6 and MIPS64r6.418class INSN_MIPS4_32R2_NOT_32R6_64R6 {419 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];420 list<Predicate> EncodingPredicates = [HasStdEnc];421}422 423// The portions of MIPS-IV that were also added to MIPS32r2.424class INSN_MIPS4_32R2 {425 list<Predicate> InsnPredicates = [HasMips4_32r2];426 list<Predicate> EncodingPredicates = [HasStdEnc];427}428 429// The portions of MIPS-V that were also added to MIPS32r2 but were removed in430// MIPS32r6 and MIPS64r6.431class INSN_MIPS5_32R2_NOT_32R6_64R6 {432 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];433 list<Predicate> EncodingPredicates = [HasStdEnc];434}435 436class ASE_CNMIPS {437 list<Predicate> ASEPredicate = [HasCnMips];438}439 440class NOT_ASE_CNMIPS {441 list<Predicate> ASEPredicate = [NotCnMips];442}443 444class ASE_CNMIPSP {445 list<Predicate> ASEPredicate = [HasCnMipsP];446}447 448class NOT_ASE_CNMIPSP {449 list<Predicate> ASEPredicate = [NotCnMipsP];450}451 452class ASE_MIPS64_CNMIPS {453 list<Predicate> ASEPredicate = [HasMips64, HasCnMips];454}455 456class ASE_MSA {457 list<Predicate> ASEPredicate = [HasMSA];458}459 460class ASE_MSA_NOT_MSA64 {461 list<Predicate> ASEPredicate = [HasMSA, NotMips64];462}463 464class ASE_MSA64 {465 list<Predicate> ASEPredicate = [HasMSA, HasMips64];466}467 468class ASE_MT {469 list <Predicate> ASEPredicate = [HasMT];470}471 472class ASE_CRC {473 list <Predicate> ASEPredicate = [HasCRC];474}475 476class ASE_VIRT {477 list <Predicate> ASEPredicate = [HasVirt];478}479 480class ASE_GINV {481 list <Predicate> ASEPredicate = [HasGINV];482}483 484// Class used for separating microMIPSr6 and microMIPS (r3) instruction.485// It can be used only on instructions that doesn't inherit PredicateControl.486class ISA_MICROMIPS_NOT_32R6 : PredicateControl {487 let InsnPredicates = [NotMips32r6];488 let EncodingPredicates = [InMicroMips];489}490 491class ASE_NOT_DSP {492 list<Predicate> ASEPredicate = [NotDSP];493}494 495class MADD4 {496 list<Predicate> AdditionalPredicates = [HasMadd4];497}498 499// Classes used for separating expansions that differ based on the ABI in500// use.501class ABI_N64 {502 list<Predicate> AdditionalPredicates = [IsN64];503}504 505class ABI_NOT_N64 {506 list<Predicate> AdditionalPredicates = [IsNotN64];507}508 509class FPOP_FUSION_FAST {510 list <Predicate> AdditionalPredicates = [AllowFPOpFusion];511}512 513//===----------------------------------------------------------------------===//514 515class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl;516 517class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :518 InstAlias<Asm, Result, Emit>, PredicateControl;519 520class IsCommutable {521 bit isCommutable = 1;522}523 524class IsBranch {525 bit isBranch = 1;526 bit isCTI = 1;527}528 529class IsReturn {530 bit isReturn = 1;531 bit isCTI = 1;532}533 534class IsCall {535 bit isCall = 1;536 bit isCTI = 1;537}538 539class IsTailCall {540 bit isCall = 1;541 bit isTerminator = 1;542 bit isReturn = 1;543 bit isBarrier = 1;544 bit hasExtraSrcRegAllocReq = 1;545 bit isCodeGenOnly = 1;546 bit isCTI = 1;547}548 549class IsAsCheapAsAMove {550 bit isAsCheapAsAMove = 1;551}552 553class NeverHasSideEffects {554 bit hasSideEffects = 0;555}556 557//===----------------------------------------------------------------------===//558// Instruction format superclass559//===----------------------------------------------------------------------===//560 561include "MipsInstrFormats.td"562 563//===----------------------------------------------------------------------===//564// Mips Operand, Complex Patterns and Transformations Definitions.565//===----------------------------------------------------------------------===//566 567class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],568 int Offset = 0> : AsmOperandClass {569 let Name = "ConstantSImm" # Bits # "_" # Offset;570 let RenderMethod = "addConstantSImmOperands<" # Bits # ", " # Offset # ">";571 let PredicateMethod = "isConstantSImm<" # Bits # ", " # Offset # ">";572 let SuperClasses = Supers;573 let DiagnosticType = "SImm" # Bits # "_" # Offset;574}575 576class SimmLslAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],577 int Shift = 0> : AsmOperandClass {578 let Name = "Simm" # Bits # "_Lsl" # Shift;579 let RenderMethod = "addImmOperands";580 let PredicateMethod = "isScaledSImm<" # Bits # ", " # Shift # ">";581 let SuperClasses = Supers;582 let DiagnosticType = "SImm" # Bits # "_Lsl" # Shift;583}584 585class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],586 int Offset = 0> : AsmOperandClass {587 let Name = "ConstantUImm" # Bits # "_" # Offset;588 let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";589 let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";590 let SuperClasses = Supers;591 let DiagnosticType = "UImm" # Bits # "_" # Offset;592}593 594class ConstantUImmRangeAsmOperandClass<int Bottom, int Top,595 list<AsmOperandClass> Supers = []>596 : AsmOperandClass {597 let Name = "ConstantUImmRange" # Bottom # "_" # Top;598 let RenderMethod = "addImmOperands";599 let PredicateMethod = "isConstantUImmRange<" # Bottom # ", " # Top # ">";600 let SuperClasses = Supers;601 let DiagnosticType = "UImmRange" # Bottom # "_" # Top;602}603 604class SImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>605 : AsmOperandClass {606 let Name = "SImm" # Bits;607 let RenderMethod = "addSImmOperands<" # Bits # ">";608 let PredicateMethod = "isSImm<" # Bits # ">";609 let SuperClasses = Supers;610 let DiagnosticType = "SImm" # Bits;611}612 613class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>614 : AsmOperandClass {615 let Name = "UImm" # Bits;616 let RenderMethod = "addUImmOperands<" # Bits # ">";617 let PredicateMethod = "isUImm<" # Bits # ">";618 let SuperClasses = Supers;619 let DiagnosticType = "UImm" # Bits;620}621 622// Generic case - only to support certain assembly pseudo instructions.623class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>624 : AsmOperandClass {625 let Name = "ImmAny";626 let RenderMethod = "addConstantUImmOperands<32>";627 let PredicateMethod = "isSImm<" # Bits # ">";628 let SuperClasses = Supers;629 let DiagnosticType = "ImmAny";630}631 632// AsmOperandClasses require a strict ordering which is difficult to manage633// as a hierarchy. Instead, we use a linear ordering and impose an order that634// is in some places arbitrary.635//636// Here the rules that are in use:637// * Wider immediates are a superset of narrower immediates:638// uimm4 < uimm5 < uimm6639// * For the same bit-width, unsigned immediates are a superset of signed640// immediates::641// simm4 < uimm4 < simm5 < uimm5642// * For the same upper-bound, signed immediates are a superset of unsigned643// immediates:644// uimm3 < simm4 < uimm4 < simm4645// * Modified immediates are a superset of ordinary immediates:646// uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6647// The term 'superset' starts to break down here since the uimm5_plus* classes648// are not true supersets of uimm5 (but they are still subsets of uimm6).649// * 'Relaxed' immediates are supersets of the corresponding unsigned immediate.650// uimm16 < uimm16_relaxed651// * The codeGen pattern type is arbitrarily ordered.652// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5653// This is entirely arbitrary. We need an ordering and what we pick is654// unimportant since only one is possible for a given mnemonic.655 656def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {657 let Name = "UImm32_Coerced";658 let DiagnosticType = "UImm32_Coerced";659}660def SImm32RelaxedAsmOperandClass661 : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {662 let Name = "SImm32_Relaxed";663 let PredicateMethod = "isAnyImm<33>";664 let DiagnosticType = "SImm32_Relaxed";665}666def SImm32AsmOperandClass667 : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;668def ConstantUImm26AsmOperandClass669 : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;670def ConstantUImm20AsmOperandClass671 : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;672def ConstantSImm19Lsl2AsmOperandClass : AsmOperandClass {673 let Name = "SImm19Lsl2";674 let RenderMethod = "addImmOperands";675 let PredicateMethod = "isScaledSImm<19, 2>";676 let SuperClasses = [ConstantUImm20AsmOperandClass];677 let DiagnosticType = "SImm19_Lsl2";678}679def UImm16RelaxedAsmOperandClass680 : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {681 let Name = "UImm16_Relaxed";682 let PredicateMethod = "isAnyImm<16>";683 let DiagnosticType = "UImm16_Relaxed";684}685// Similar to the relaxed classes which take an SImm and render it as686// an UImm, this takes a UImm and renders it as an SImm.687def UImm16AltRelaxedAsmOperandClass688 : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {689 let Name = "UImm16_AltRelaxed";690 let PredicateMethod = "isUImm<16>";691 let DiagnosticType = "UImm16_AltRelaxed";692}693// FIXME: One of these should probably have UImm16AsmOperandClass as the694// superclass instead of UImm16RelaxedasmOPerandClass.695def UImm16AsmOperandClass696 : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;697def SImm16RelaxedAsmOperandClass698 : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {699 let Name = "SImm16_Relaxed";700 let PredicateMethod = "isAnyImm<16>";701 let DiagnosticType = "SImm16_Relaxed";702}703def SImm16AsmOperandClass704 : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>;705def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {706 let Name = "SImm10Lsl3";707 let RenderMethod = "addImmOperands";708 let PredicateMethod = "isScaledSImm<10, 3>";709 let SuperClasses = [SImm16AsmOperandClass];710 let DiagnosticType = "SImm10_Lsl3";711}712def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {713 let Name = "SImm10Lsl2";714 let RenderMethod = "addImmOperands";715 let PredicateMethod = "isScaledSImm<10, 2>";716 let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];717 let DiagnosticType = "SImm10_Lsl2";718}719def ConstantSImm11AsmOperandClass720 : ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>;721def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {722 let Name = "SImm10Lsl1";723 let RenderMethod = "addImmOperands";724 let PredicateMethod = "isScaledSImm<10, 1>";725 let SuperClasses = [ConstantSImm11AsmOperandClass];726 let DiagnosticType = "SImm10_Lsl1";727}728def ConstantUImm10AsmOperandClass729 : ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>;730def ConstantSImm10AsmOperandClass731 : ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>;732def ConstantSImm9AsmOperandClass733 : ConstantSImmAsmOperandClass<9, [ConstantSImm10AsmOperandClass]>;734def ConstantSImm7Lsl2AsmOperandClass : AsmOperandClass {735 let Name = "SImm7Lsl2";736 let RenderMethod = "addImmOperands";737 let PredicateMethod = "isScaledSImm<7, 2>";738 let SuperClasses = [ConstantSImm9AsmOperandClass];739 let DiagnosticType = "SImm7_Lsl2";740}741def ConstantUImm8AsmOperandClass742 : ConstantUImmAsmOperandClass<8, [ConstantSImm7Lsl2AsmOperandClass]>;743def ConstantUImm7Sub1AsmOperandClass744 : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass], -1> {745 // Specify the names since the -1 offset causes invalid identifiers otherwise.746 let Name = "UImm7_N1";747 let DiagnosticType = "UImm7_N1";748}749def ConstantUImm7AsmOperandClass750 : ConstantUImmAsmOperandClass<7, [ConstantUImm7Sub1AsmOperandClass]>;751def ConstantUImm6Lsl2AsmOperandClass : AsmOperandClass {752 let Name = "UImm6Lsl2";753 let RenderMethod = "addImmOperands";754 let PredicateMethod = "isScaledUImm<6, 2>";755 let SuperClasses = [ConstantUImm7AsmOperandClass];756 let DiagnosticType = "UImm6_Lsl2";757}758def ConstantUImm6AsmOperandClass759 : ConstantUImmAsmOperandClass<6, [ConstantUImm6Lsl2AsmOperandClass]>;760def ConstantSImm6AsmOperandClass761 : ConstantSImmAsmOperandClass<6, [ConstantUImm6AsmOperandClass]>;762def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass {763 let Name = "UImm5Lsl2";764 let RenderMethod = "addImmOperands";765 let PredicateMethod = "isScaledUImm<5, 2>";766 let SuperClasses = [ConstantSImm6AsmOperandClass];767 let DiagnosticType = "UImm5_Lsl2";768}769def ConstantUImm5_Range2_64AsmOperandClass770 : ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm5Lsl2AsmOperandClass]>;771def ConstantUImm5Plus33AsmOperandClass772 : ConstantUImmAsmOperandClass<5, [ConstantUImm5_Range2_64AsmOperandClass],773 33>;774def ConstantUImm5ReportUImm6AsmOperandClass775 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus33AsmOperandClass]> {776 let Name = "ConstantUImm5_0_Report_UImm6";777 let DiagnosticType = "UImm5_0_Report_UImm6";778}779def ConstantUImm5Plus32AsmOperandClass780 : ConstantUImmAsmOperandClass<781 5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>;782def ConstantUImm5Plus32NormalizeAsmOperandClass783 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> {784 let Name = "ConstantUImm5_32_Norm";785 // We must also subtract 32 when we render the operand.786 let RenderMethod = "addConstantUImmOperands<5, 32, -32>";787}788def ConstantUImm5Plus1ReportUImm6AsmOperandClass789 : ConstantUImmAsmOperandClass<790 5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>{791 let Name = "ConstantUImm5_Plus1_Report_UImm6";792}793def ConstantUImm5Plus1AsmOperandClass794 : ConstantUImmAsmOperandClass<795 5, [ConstantUImm5Plus1ReportUImm6AsmOperandClass], 1>;796def ConstantUImm5AsmOperandClass797 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;798def ConstantSImm5AsmOperandClass799 : ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>;800def ConstantUImm4AsmOperandClass801 : ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>;802def ConstantSImm4AsmOperandClass803 : ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>;804def ConstantUImm3AsmOperandClass805 : ConstantUImmAsmOperandClass<3, [ConstantSImm4AsmOperandClass]>;806def ConstantUImm2Plus1AsmOperandClass807 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;808def ConstantUImm2AsmOperandClass809 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;810def ConstantUImm1AsmOperandClass811 : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>;812def ConstantImmzAsmOperandClass : AsmOperandClass {813 let Name = "ConstantImmz";814 let RenderMethod = "addConstantUImmOperands<1>";815 let PredicateMethod = "isConstantImmz";816 let SuperClasses = [ConstantUImm1AsmOperandClass];817 let DiagnosticType = "Immz";818}819 820def Simm19Lsl2AsmOperand821 : SimmLslAsmOperandClass<19, [], 2>;822 823def MipsJumpTargetAsmOperand : AsmOperandClass {824 let Name = "JumpTarget";825 let ParserMethod = "parseJumpTarget";826 let PredicateMethod = "isImm";827 let RenderMethod = "addImmOperands";828}829 830// Instruction operand types831def jmptarget : Operand<OtherVT> {832 let EncoderMethod = "getJumpTargetOpValue";833 let ParserMatchClass = MipsJumpTargetAsmOperand;834 let PrintMethod = "printJumpOperand";835}836def brtarget : Operand<OtherVT> {837 let EncoderMethod = "getBranchTargetOpValue";838 let OperandType = "OPERAND_PCREL";839 let DecoderMethod = "DecodeBranchTarget";840 let ParserMatchClass = MipsJumpTargetAsmOperand;841 let PrintMethod = "printBranchOperand";842}843def brtarget1SImm16 : Operand<OtherVT> {844 let EncoderMethod = "getBranchTargetOpValue1SImm16";845 let OperandType = "OPERAND_PCREL";846 let DecoderMethod = "DecodeBranchTarget1SImm16";847 let ParserMatchClass = MipsJumpTargetAsmOperand;848 let PrintMethod = "printBranchOperand";849}850def calltarget : Operand<iPTR> {851 let EncoderMethod = "getJumpTargetOpValue";852 let ParserMatchClass = MipsJumpTargetAsmOperand;853 let PrintMethod = "printJumpOperand";854}855 856def imm64: Operand<i64>;857 858def ConstantImmAsmOperandClass : AsmOperandClass {859 let Name = "ConstantImm";860 let PredicateMethod = "isConstantImm";861 let RenderMethod = "addImmOperands";862}863 864def ConstantImm64: Operand<i64> {865 let ParserMatchClass = ConstantImmAsmOperandClass;866}867 868def simm19_lsl2 : Operand<i32> {869 let EncoderMethod = "getSimm19Lsl2Encoding";870 let DecoderMethod = "DecodeSimm19Lsl2";871 let ParserMatchClass = Simm19Lsl2AsmOperand;872}873 874def simm18_lsl3 : Operand<i32> {875 let EncoderMethod = "getSimm18Lsl3Encoding";876 let DecoderMethod = "DecodeSimm18Lsl3";877 let ParserMatchClass = MipsJumpTargetAsmOperand;878}879 880// Zero881def uimmz : Operand<i32> {882 let PrintMethod = "printUImm<0>";883 let ParserMatchClass = ConstantImmzAsmOperandClass;884}885 886// size operand of ins instruction887def uimm_range_2_64 : Operand<i32> {888 let PrintMethod = "printUImm<6, 2>";889 let EncoderMethod = "getSizeInsEncoding";890 let DecoderMethod = "DecodeInsSize";891 let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass;892}893 894// Unsigned Operands895foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in896 def uimm # I : Operand<i32> {897 let PrintMethod = "printUImm<" # I # ">";898 let ParserMatchClass =899 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");900 }901 902def uimm2_plus1 : Operand<i32> {903 let PrintMethod = "printUImm<2, 1>";904 let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";905 let DecoderMethod = "DecodeUImmWithOffset<2, 1>";906 let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;907}908 909def uimm5_plus1 : Operand<i32> {910 let PrintMethod = "printUImm<5, 1>";911 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";912 let DecoderMethod = "DecodeUImmWithOffset<5, 1>";913 let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;914}915 916def uimm5_plus1_report_uimm6 : Operand<i32> {917 let PrintMethod = "printUImm<6, 1>";918 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";919 let DecoderMethod = "DecodeUImmWithOffset<5, 1>";920 let ParserMatchClass = ConstantUImm5Plus1ReportUImm6AsmOperandClass;921}922 923def uimm5_plus32 : Operand<i32> {924 let PrintMethod = "printUImm<5, 32>";925 let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;926}927 928def uimm5_plus33 : Operand<i32> {929 let PrintMethod = "printUImm<5, 33>";930 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";931 let DecoderMethod = "DecodeUImmWithOffset<5, 1>";932 let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass;933}934 935def uimm5_inssize_plus1 : Operand<i32> {936 let PrintMethod = "printUImm<6>";937 let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;938 let EncoderMethod = "getSizeInsEncoding";939 let DecoderMethod = "DecodeInsSize";940}941 942def uimm5_plus32_normalize : Operand<i32> {943 let PrintMethod = "printUImm<5>";944 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;945}946 947def uimm5_lsl2 : Operand<OtherVT> {948 let EncoderMethod = "getUImm5Lsl2Encoding";949 let DecoderMethod = "DecodeUImmWithOffsetAndScale<5, 0, 4>";950 let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass;951}952 953def uimm5_plus32_normalize_64 : Operand<i64> {954 let PrintMethod = "printUImm<5>";955 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;956}957 958def uimm6_lsl2 : Operand<OtherVT> {959 let EncoderMethod = "getUImm6Lsl2Encoding";960 let DecoderMethod = "DecodeUImmWithOffsetAndScale<6, 0, 4>";961 let ParserMatchClass = ConstantUImm6Lsl2AsmOperandClass;962}963 964foreach I = {16} in965 def uimm # I : Operand<i32> {966 let PrintMethod = "printUImm<" # I # ">";967 let ParserMatchClass =968 !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");969 }970 971// Like uimm16_64 but coerces simm16 to uimm16.972def uimm16_relaxed : Operand<i32> {973 let PrintMethod = "printUImm<16>";974 let ParserMatchClass = UImm16RelaxedAsmOperandClass;975}976 977foreach I = {5} in978 def uimm # I # _64 : Operand<i64> {979 let PrintMethod = "printUImm<" # I # ">";980 let ParserMatchClass =981 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");982 }983 984foreach I = {16} in985 def uimm # I # _64 : Operand<i64> {986 let PrintMethod = "printUImm<" # I # ">";987 let ParserMatchClass =988 !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");989 }990 991// Like uimm16_64 but coerces simm16 to uimm16.992def uimm16_64_relaxed : Operand<i64> {993 let PrintMethod = "printUImm<16>";994 let ParserMatchClass = UImm16RelaxedAsmOperandClass;995}996 997def uimm16_altrelaxed : Operand<i32> {998 let PrintMethod = "printUImm<16>";999 let ParserMatchClass = UImm16AltRelaxedAsmOperandClass;1000}1001// Like uimm5 but reports a less confusing error for 32-63 when1002// an instruction alias permits that.1003def uimm5_report_uimm6 : Operand<i32> {1004 let PrintMethod = "printUImm<6>";1005 let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;1006}1007 1008// Like uimm5_64 but reports a less confusing error for 32-63 when1009// an instruction alias permits that.1010def uimm5_64_report_uimm6 : Operand<i64> {1011 let PrintMethod = "printUImm<5>";1012 let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;1013}1014 1015foreach I = {1, 2, 3, 4} in1016 def uimm # I # _ptr : Operand<iPTR> {1017 let PrintMethod = "printUImm<" # I # ">";1018 let ParserMatchClass =1019 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");1020 }1021 1022foreach I = {1, 2, 3, 4, 5, 6, 8} in1023 def vsplat_uimm # I : Operand<vAny> {1024 let PrintMethod = "printUImm<" # I # ">";1025 let ParserMatchClass =1026 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");1027 }1028 1029// Signed operands1030foreach I = {4, 5, 6, 9, 10, 11} in1031 def simm # I : Operand<i32> {1032 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";1033 let ParserMatchClass =1034 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");1035 }1036 1037foreach I = {1, 2, 3} in1038 def simm10_lsl # I : Operand<i32> {1039 let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">";1040 let ParserMatchClass =1041 !cast<AsmOperandClass>("ConstantSImm10Lsl" # I # "AsmOperandClass");1042 }1043 1044foreach I = {10} in1045 def simm # I # _64 : Operand<i64> {1046 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";1047 let ParserMatchClass =1048 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");1049 }1050 1051foreach I = {5, 10} in1052 def vsplat_simm # I : Operand<vAny> {1053 let ParserMatchClass =1054 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");1055 }1056 1057def simm7_lsl2 : Operand<OtherVT> {1058 let EncoderMethod = "getSImm7Lsl2Encoding";1059 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>";1060 let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;1061}1062 1063foreach I = {16, 32} in1064 def simm # I : Operand<i32> {1065 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";1066 let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass");1067 }1068 1069// Like simm16 but coerces uimm16 to simm16.1070def simm16_relaxed : Operand<i32> {1071 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";1072 let ParserMatchClass = SImm16RelaxedAsmOperandClass;1073}1074 1075def simm16_64 : Operand<i64> {1076 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";1077 let ParserMatchClass = SImm16AsmOperandClass;1078}1079 1080// like simm32 but coerces simm32 to uimm32.1081def uimm32_coerced : Operand<i32> {1082 let ParserMatchClass = UImm32CoercedAsmOperandClass;1083}1084// Like simm32 but coerces uimm32 to simm32.1085def simm32_relaxed : Operand<i32> {1086 let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";1087 let ParserMatchClass = SImm32RelaxedAsmOperandClass;1088}1089 1090// This is almost the same as a uimm7 but 0x7f is interpreted as -1.1091def li16_imm : Operand<i32> {1092 let DecoderMethod = "DecodeLi16Imm";1093 let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass;1094}1095 1096def MipsMemAsmOperand : AsmOperandClass {1097 let Name = "Mem";1098 let ParserMethod = "parseMemOperand";1099}1100 1101class MipsMemSimmAsmOperand<int Width, int Shift = 0> : AsmOperandClass {1102 let Name = "MemOffsetSimm" # Width # "_" # Shift;1103 let SuperClasses = [MipsMemAsmOperand];1104 let RenderMethod = "addMemOperands";1105 let ParserMethod = "parseMemOperand";1106 let PredicateMethod = "isMemWithSimmOffset<" # Width # ", " # Shift # ">";1107 let DiagnosticType = !if(!eq(Shift, 0), "MemSImm" # Width,1108 "MemSImm" # Width # "Lsl" # Shift);1109}1110 1111def MipsMemSimmPtrAsmOperand : AsmOperandClass {1112 let Name = "MemOffsetSimmPtr";1113 let SuperClasses = [MipsMemAsmOperand];1114 let RenderMethod = "addMemOperands";1115 let ParserMethod = "parseMemOperand";1116 let PredicateMethod = "isMemWithPtrSizeOffset";1117 let DiagnosticType = "MemSImmPtr";1118}1119 1120def MipsInvertedImmoperand : AsmOperandClass {1121 let Name = "InvNum";1122 let RenderMethod = "addImmOperands";1123 let ParserMethod = "parseInvNum";1124}1125 1126def InvertedImOperand : Operand<i32> {1127 let ParserMatchClass = MipsInvertedImmoperand;1128}1129 1130def InvertedImOperand64 : Operand<i64> {1131 let ParserMatchClass = MipsInvertedImmoperand;1132}1133 1134class mem_generic : Operand<iPTR> {1135 let PrintMethod = "printMemOperand";1136 let MIOperandInfo = (ops mips_ptr_rc, simm16);1137 let EncoderMethod = "getMemEncoding";1138 let ParserMatchClass = MipsMemAsmOperand;1139 let OperandType = "OPERAND_MEMORY";1140}1141 1142// Address operand1143def mem : mem_generic;1144 1145// MSA specific address operand1146def mem_msa : mem_generic {1147 let MIOperandInfo = (ops mips_ptr_rc, simm10);1148 let EncoderMethod = "getMSAMemEncoding";1149}1150 1151def simm12 : Operand<i32> {1152 let DecoderMethod = "DecodeSimm12";1153}1154 1155def mem_simm9_exp : mem_generic {1156 let MIOperandInfo = (ops mips_ptr_rc, simm9);1157 let ParserMatchClass = MipsMemSimmPtrAsmOperand;1158 let OperandNamespace = "MipsII";1159 let OperandType = "OPERAND_MEM_SIMM9";1160}1161 1162foreach I = {9, 10, 11, 12, 16} in1163 def mem_simm # I : mem_generic {1164 let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm" # I));1165 let ParserMatchClass = MipsMemSimmAsmOperand<I>;1166 }1167 1168foreach I = {1, 2, 3} in1169 def mem_simm10_lsl # I : mem_generic {1170 let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm10_lsl" # I));1171 let EncoderMethod = "getMemEncoding<" # I # ">";1172 let ParserMatchClass = MipsMemSimmAsmOperand<10, I>;1173 }1174 1175def mem_simmptr : mem_generic {1176 let ParserMatchClass = MipsMemSimmPtrAsmOperand;1177}1178 1179def mem_ea : Operand<iPTR> {1180 let PrintMethod = "printMemOperandEA";1181 let MIOperandInfo = (ops mips_ptr_rc, simm16);1182 let EncoderMethod = "getMemEncoding";1183 let OperandType = "OPERAND_MEMORY";1184}1185 1186def PtrRC : Operand<iPTR> {1187 let MIOperandInfo = (ops mips_ptr_rc);1188 let DecoderMethod = "DecodePtrRegisterClass";1189 let ParserMatchClass = GPR32AsmOperand;1190}1191 1192// size operand of ins instruction1193def size_ins : Operand<i32> {1194 let EncoderMethod = "getSizeInsEncoding";1195 let DecoderMethod = "DecodeInsSize";1196}1197 1198// Transformation Function - get the lower 16 bits.1199def LO16 : SDNodeXForm<imm, [{1200 return getImm(N, N->getZExtValue() & 0xFFFF);1201}]>;1202 1203// Transformation Function - get the higher 16 bits.1204def HI16 : SDNodeXForm<imm, [{1205 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);1206}]>;1207 1208// Plus 1.1209def Plus1 : SDNodeXForm<imm, [{1210 return getSignedImm(N, N->getSExtValue() + 1);1211}]>;1212 1213// Node immediate is zero (e.g. insve.d)1214def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;1215 1216// Node immediate fits as 16-bit sign extended on target immediate.1217// e.g. addi, andi1218def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;1219 1220// Node immediate fits as 16-bit sign extended on target immediate.1221// e.g. addi, andi1222def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;1223def imm32SExt16 : IntImmLeaf<i32, [{ return isInt<16>(Imm.getSExtValue()); }]>;1224 1225// Node immediate fits as 7-bit zero extended on target immediate.1226def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;1227def timmZExt7 : PatLeaf<(timm), [{ return isUInt<7>(N->getZExtValue()); }]>;1228 1229// Node immediate fits as 16-bit zero extended on target immediate.1230// The LO16 param means that only the lower 16 bits of the node1231// immediate are caught.1232// e.g. addiu, sltiu1233def immZExt16 : PatLeaf<(imm), [{1234 if (N->getValueType(0) == MVT::i32)1235 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();1236 else1237 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();1238}], LO16>;1239def imm32ZExt16 : IntImmLeaf<i32, [{1240 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();1241}]>;1242 1243// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).1244def immSExt32Low16Zero : PatLeaf<(imm), [{1245 int64_t Val = N->getSExtValue();1246 return isInt<32>(Val) && !(Val & 0xffff);1247}]>;1248 1249// Zero-extended 32-bit unsigned int with lower 16-bit cleared.1250def immZExt32Low16Zero : PatLeaf<(imm), [{1251 uint64_t Val = N->getZExtValue();1252 return isUInt<32>(Val) && !(Val & 0xffff);1253}]>;1254 1255// Note immediate fits as a 32 bit signed extended on target immediate.1256def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;1257 1258// Note immediate fits as a 32 bit zero extended on target immediate.1259def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;1260 1261// shamt field must fit in 5 bits.1262def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;1263def timmZExt5 : TImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;1264 1265def immZExt5Plus1 : PatLeaf<(imm), [{1266 return isUInt<5>(N->getZExtValue() - 1);1267}]>;1268def immZExt5Plus32 : PatLeaf<(imm), [{1269 return isUInt<5>(N->getZExtValue() - 32);1270}]>;1271def immZExt5Plus33 : PatLeaf<(imm), [{1272 return isUInt<5>(N->getZExtValue() - 33);1273}]>;1274 1275def immZExt5To31 : SDNodeXForm<imm, [{1276 return getImm(N, 31 - N->getZExtValue());1277}]>;1278 1279// True if (N + 1) fits in 16-bit field.1280def immSExt16Plus1 : PatLeaf<(imm), [{1281 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);1282}]>;1283 1284def immZExtRange2To64 : PatLeaf<(imm), [{1285 return isUInt<7>(N->getZExtValue()) && (N->getZExtValue() >= 2) &&1286 (N->getZExtValue() <= 64);1287}]>;1288 1289def ORiPred : PatLeaf<(imm), [{1290 return isUInt<16>(N->getZExtValue()) && !isInt<16>(N->getSExtValue());1291}], LO16>;1292 1293def LUiPred : PatLeaf<(imm), [{1294 int64_t Val = N->getSExtValue();1295 return !isInt<16>(Val) && isInt<32>(Val) && !(Val & 0xffff);1296}]>;1297 1298def LUiORiPred : PatLeaf<(imm), [{1299 int64_t SVal = N->getSExtValue();1300 return isInt<32>(SVal) && (SVal & 0xffff);1301}]>;1302 1303// Mips Address Mode! SDNode frameindex could possibly be a match1304// since load and store instructions from stack used it.1305def addr :1306 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;1307 1308def addrRegImm :1309 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;1310 1311def addrDefault :1312 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;1313 1314def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10", [frameindex]>;1315def addrimm10lsl1 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl1",1316 [frameindex]>;1317def addrimm10lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl2",1318 [frameindex]>;1319def addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3",1320 [frameindex]>;1321 1322//===----------------------------------------------------------------------===//1323// Instructions specific format1324//===----------------------------------------------------------------------===//1325 1326// Arithmetic and logical instructions with 3 register operands.1327class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,1328 InstrItinClass Itin = NoItinerary,1329 SDPatternOperator OpNode = null_frag>:1330 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),1331 !strconcat(opstr, "\t$rd, $rs, $rt"),1332 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {1333 let isCommutable = isComm;1334 let isReMaterializable = 1;1335 let TwoOperandAliasConstraint = "$rd = $rs";1336}1337 1338// Arithmetic and logical instructions with 2 register operands.1339class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,1340 InstrItinClass Itin = NoItinerary,1341 SDPatternOperator imm_type = null_frag,1342 SDPatternOperator OpNode = null_frag> :1343 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),1344 !strconcat(opstr, "\t$rt, $rs, $imm16"),1345 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],1346 Itin, FrmI, opstr> {1347 let isReMaterializable = 1;1348 let TwoOperandAliasConstraint = "$rs = $rt";1349}1350 1351// Arithmetic Multiply ADD/SUB1352class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :1353 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),1354 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {1355 let Defs = [HI0, LO0];1356 let Uses = [HI0, LO0];1357 let isCommutable = isComm;1358}1359 1360// Logical1361class LogicNOR<string opstr, RegisterOperand RO>:1362 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),1363 !strconcat(opstr, "\t$rd, $rs, $rt"),1364 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {1365 let isCommutable = 1;1366}1367 1368// Shifts1369class shift_rotate_imm<string opstr, Operand ImmOpnd,1370 RegisterOperand RO, InstrItinClass itin,1371 SDPatternOperator OpNode = null_frag,1372 SDPatternOperator PF = null_frag> :1373 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),1374 !strconcat(opstr, "\t$rd, $rt, $shamt"),1375 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {1376 let TwoOperandAliasConstraint = "$rt = $rd";1377}1378 1379class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,1380 SDPatternOperator OpNode = null_frag>:1381 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),1382 !strconcat(opstr, "\t$rd, $rt, $rs"),1383 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,1384 opstr>;1385 1386// Load Upper Immediate1387class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:1388 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),1389 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {1390 let hasSideEffects = 0;1391 let isReMaterializable = 1;1392}1393 1394// Memory Load/Store1395class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,1396 SDPatternOperator OpNode = null_frag,1397 InstrItinClass Itin = NoItinerary,1398 ComplexPattern Addr = addr> :1399 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),1400 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {1401 let DecoderMethod = "DecodeMem";1402 let canFoldAsLoad = 1;1403 string BaseOpcode = opstr;1404 let mayLoad = 1;1405}1406 1407class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,1408 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :1409 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;1410 1411class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,1412 SDPatternOperator OpNode = null_frag,1413 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :1414 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),1415 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {1416 let DecoderMethod = "DecodeMem";1417 string BaseOpcode = opstr;1418 let mayStore = 1;1419}1420 1421class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,1422 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr,1423 DAGOperand MO = mem> :1424 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;1425 1426// Load/Store Left/Right1427let canFoldAsLoad = 1 in1428class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,1429 InstrItinClass Itin> :1430 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),1431 !strconcat(opstr, "\t$rt, $addr"),1432 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {1433 let DecoderMethod = "DecodeMem";1434 string Constraints = "$src = $rt";1435 let BaseOpcode = opstr;1436}1437 1438class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,1439 InstrItinClass Itin> :1440 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),1441 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {1442 let DecoderMethod = "DecodeMem";1443 let BaseOpcode = opstr;1444}1445 1446// COP2 Load/Store1447class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,1448 SDPatternOperator OpNode= null_frag> :1449 InstSE<(outs RC:$rt), (ins mem_simm16:$addr),1450 !strconcat(opstr, "\t$rt, $addr"),1451 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {1452 let DecoderMethod = "DecodeFMem2";1453 let mayLoad = 1;1454}1455 1456class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,1457 SDPatternOperator OpNode= null_frag> :1458 InstSE<(outs), (ins RC:$rt, mem_simm16:$addr),1459 !strconcat(opstr, "\t$rt, $addr"),1460 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {1461 let DecoderMethod = "DecodeFMem2";1462 let mayStore = 1;1463}1464 1465// COP3 Load/Store1466class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,1467 SDPatternOperator OpNode= null_frag> :1468 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),1469 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {1470 let DecoderMethod = "DecodeFMem3";1471 let mayLoad = 1;1472}1473 1474class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,1475 SDPatternOperator OpNode= null_frag> :1476 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),1477 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {1478 let DecoderMethod = "DecodeFMem3";1479 let mayStore = 1;1480}1481 1482// Conditional Branch1483class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,1484 RegisterOperand RO> :1485 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),1486 !strconcat(opstr, "\t$rs, $rt, $offset"),1487 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,1488 FrmI, opstr> {1489 let isBranch = 1;1490 let isTerminator = 1;1491 let hasDelaySlot = 1;1492 let Defs = [AT];1493 bit isCTI = 1;1494}1495 1496class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :1497 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),1498 !strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> {1499 let isBranch = 1;1500 let isTerminator = 1;1501 let hasDelaySlot = 1;1502 let Defs = [AT];1503 bit isCTI = 1;1504}1505 1506class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,1507 RegisterOperand RO> :1508 InstSE<(outs), (ins RO:$rs, opnd:$offset),1509 !strconcat(opstr, "\t$rs, $offset"),1510 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,1511 FrmI, opstr> {1512 let isBranch = 1;1513 let isTerminator = 1;1514 let hasDelaySlot = 1;1515 let Defs = [AT];1516 bit isCTI = 1;1517}1518 1519class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :1520 InstSE<(outs), (ins RO:$rs, opnd:$offset),1521 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> {1522 let isBranch = 1;1523 let isTerminator = 1;1524 let hasDelaySlot = 1;1525 let Defs = [AT];1526 bit isCTI = 1;1527}1528 1529// SetCC1530class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :1531 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),1532 !strconcat(opstr, "\t$rd, $rs, $rt"),1533 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],1534 II_SLT_SLTU, FrmR, opstr>;1535 1536class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,1537 RegisterOperand RO>:1538 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),1539 !strconcat(opstr, "\t$rt, $rs, $imm16"),1540 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],1541 II_SLTI_SLTIU, FrmI, opstr>;1542 1543// Jump1544class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,1545 SDPatternOperator targetoperator, string bopstr> :1546 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),1547 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {1548 let isTerminator=1;1549 let isBarrier=1;1550 let hasDelaySlot = 1;1551 let DecoderMethod = "DecodeJumpTarget";1552 let Defs = [AT];1553 bit isCTI = 1;1554}1555 1556// Unconditional branch1557class UncondBranch<Instruction BEQInst, DAGOperand opnd> :1558 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,1559 PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> {1560 let isBranch = 1;1561 let isTerminator = 1;1562 let isBarrier = 1;1563 let hasDelaySlot = 1;1564 let AdditionalPredicates = [RelocPIC];1565 let Defs = [AT];1566 bit isCTI = 1;1567}1568 1569// Base class for indirect branch and return instruction classes.1570let isTerminator=1, isBarrier=1, hasDelaySlot = 1, isCTI = 1 in1571class JumpFR<string opstr, RegisterOperand RO,1572 SDPatternOperator operator = null_frag>:1573 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,1574 FrmR, opstr>;1575 1576// Indirect branch1577class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {1578 let isBranch = 1;1579 let isIndirectBranch = 1;1580}1581 1582// Jump and Link (Call)1583let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {1584 class JumpLink<string opstr, DAGOperand opnd> :1585 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),1586 [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> {1587 let DecoderMethod = "DecodeJumpTarget";1588 }1589 1590 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,1591 Register RetReg, RegisterOperand ResRO = RO>:1592 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,1593 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {1594 let hasPostISelHook = 1;1595 }1596 1597 class JumpLinkReg<string opstr, RegisterOperand RO>:1598 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),1599 [], II_JALR, FrmR, opstr> {1600 let hasPostISelHook = 1;1601 }1602 1603 class BGEZAL_FT<string opstr, DAGOperand opnd,1604 RegisterOperand RO> :1605 InstSE<(outs), (ins RO:$rs, opnd:$offset),1606 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {1607 let hasDelaySlot = 1;1608 }1609 1610}1611 1612let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,1613 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {1614 class TailCall<Instruction JumpInst, DAGOperand Opnd> :1615 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,1616 PseudoInstExpansion<(JumpInst Opnd:$target)>;1617 1618 class TailCallReg<Instruction JumpInst, RegisterOperand RO> :1619 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,1620 PseudoInstExpansion<(JumpInst RO:$rs)> {1621 let hasPostISelHook = 1;1622 }1623}1624 1625class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :1626 PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>,1627 PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> {1628 let isBranch = 1;1629 let isTerminator = 1;1630 let isBarrier = 1;1631 let hasDelaySlot = 1;1632 let Defs = [RA];1633 bit isCTI = 1;1634}1635 1636let isCTI = 1 in {1637// Syscall1638class SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> :1639 InstSE<(outs), (ins ImmOp:$code_),1640 !strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>;1641// Break1642class BRK_FT<string opstr> :1643 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),1644 !strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK,1645 FrmOther, opstr>;1646 1647// (D)Eret1648class ER_FT<string opstr, InstrItinClass itin = NoItinerary> :1649 InstSE<(outs), (ins),1650 opstr, [], itin, FrmOther, opstr>;1651 1652// Wait1653class WAIT_FT<string opstr> :1654 InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>;1655}1656 1657// Interrupts1658class DEI_FT<string opstr, RegisterOperand RO,1659 InstrItinClass itin = NoItinerary> :1660 InstSE<(outs RO:$rt), (ins),1661 !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;1662 1663// Sync1664let hasSideEffects = 1 in1665class SYNC_FT<string opstr> :1666 InstSE<(outs), (ins uimm5:$stype), "sync $stype",1667 [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;1668 1669class SYNCI_FT<string opstr, DAGOperand MO> :1670 InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [],1671 II_SYNCI, FrmOther, opstr> {1672 let hasSideEffects = 1;1673 let DecoderMethod = "DecodeSyncI";1674}1675 1676let hasSideEffects = 1, isCTI = 1 in {1677class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,1678 InstrItinClass itin = NoItinerary> :1679 InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),1680 !strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>;1681 1682class TEQI_FT<string opstr, RegisterOperand RO,1683 InstrItinClass itin = NoItinerary> :1684 InstSE<(outs), (ins RO:$rs, simm16:$imm16),1685 !strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>;1686}1687 1688// Mul, Div1689class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,1690 list<Register> DefRegs> :1691 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],1692 itin, FrmR, opstr> {1693 let isCommutable = 1;1694 let Defs = DefRegs;1695 let hasSideEffects = 0;1696}1697 1698// Pseudo multiply/divide instruction with explicit accumulator register1699// operands.1700class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,1701 SDPatternOperator OpNode, InstrItinClass Itin,1702 bit IsComm = 1, bit HasSideEffects = 0,1703 bit UsesCustomInserter = 0> :1704 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),1705 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,1706 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {1707 let isCommutable = IsComm;1708 let hasSideEffects = HasSideEffects;1709 let usesCustomInserter = UsesCustomInserter;1710}1711 1712// Pseudo multiply add/sub instruction with explicit accumulator register1713// operands.1714class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,1715 InstrItinClass itin>1716 : PseudoSE<(outs ACC64:$ac),1717 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),1718 [(set ACC64:$ac,1719 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],1720 itin>,1721 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {1722 string Constraints = "$acin = $ac";1723}1724 1725class Div<string opstr, InstrItinClass itin, RegisterOperand RO,1726 list<Register> DefRegs> :1727 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),1728 [], itin, FrmR, opstr> {1729 let Defs = DefRegs;1730}1731 1732// Move from Hi/Lo1733class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>1734 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),1735 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;1736 1737class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:1738 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,1739 FrmR, opstr> {1740 let Uses = [UseReg];1741 let hasSideEffects = 0;1742 let isMoveReg = 1;1743}1744 1745class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>1746 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),1747 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],1748 II_MTHI_MTLO>;1749 1750class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:1751 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,1752 FrmR, opstr> {1753 let Defs = DefRegs;1754 let hasSideEffects = 0;1755 let isMoveReg = 1;1756}1757 1758class EffectiveAddress<string opstr, RegisterOperand RO> :1759 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),1760 [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,1761 !strconcat(opstr, "_lea")> {1762 let isCodeGenOnly = 1;1763 let hasNoSchedulingInfo = 1;1764 let DecoderMethod = "DecodeMem";1765}1766 1767// Count Leading Ones/Zeros in Word1768class CountLeading0<string opstr, RegisterOperand RO,1769 InstrItinClass itin = NoItinerary>:1770 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),1771 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;1772 1773class CountLeading1<string opstr, RegisterOperand RO,1774 InstrItinClass itin = NoItinerary>:1775 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),1776 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;1777 1778// Sign Extend in Register.1779class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,1780 InstrItinClass itin> :1781 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),1782 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;1783 1784// Subword Swap1785class SubwordSwap<string opstr, RegisterOperand RO,1786 InstrItinClass itin = NoItinerary>:1787 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,1788 FrmR, opstr> {1789 let hasSideEffects = 0;1790}1791 1792// Read Hardware1793class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :1794 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),1795 "rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">;1796 1797// Ext and Ins1798class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,1799 Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm,1800 SDPatternOperator Op = null_frag> :1801 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),1802 !strconcat(opstr, "\t$rt, $rs, $pos, $size"),1803 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,1804 FrmR, opstr>;1805 1806// 'ins' and its' 64 bit variants are matched by C++ code.1807class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,1808 Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm>:1809 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),1810 !strconcat(opstr, "\t$rt, $rs, $pos, $size"),1811 [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size,1812 RO:$src))],1813 II_INS, FrmR, opstr> {1814 let Constraints = "$src = $rt";1815}1816 1817// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).1818class Atomic2Ops<PatFrag Op, RegisterClass DRC> :1819 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),1820 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {1821 let hasNoSchedulingInfo = 1;1822}1823 1824class Atomic2OpsPostRA<RegisterClass RC> :1825 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr), []> {1826 let mayLoad = 1;1827 let mayStore = 1;1828}1829 1830class Atomic2OpsSubwordPostRA<RegisterClass RC> :1831 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr, RC:$mask, RC:$mask2,1832 RC:$shiftamnt), []>;1833 1834// Atomic Compare & Swap.1835// Atomic compare and swap is lowered into two stages. The first stage happens1836// during ISelLowering, which produces the PostRA version of this instruction.1837class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :1838 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),1839 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {1840 let hasNoSchedulingInfo = 1;1841}1842 1843class AtomicCmpSwapPostRA<RegisterClass RC> :1844 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$cmp, RC:$swap), []> {1845 let mayLoad = 1;1846 let mayStore = 1;1847}1848 1849class AtomicCmpSwapSubwordPostRA<RegisterClass RC> :1850 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$mask, RC:$ShiftCmpVal,1851 RC:$mask2, RC:$ShiftNewVal, RC:$ShiftAmt), []> {1852 let mayLoad = 1;1853 let mayStore = 1;1854}1855 1856class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :1857 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),1858 [], II_LL, FrmI, opstr> {1859 let DecoderMethod = "DecodeMem";1860 let mayLoad = 1;1861}1862 1863class SCBase<string opstr, RegisterOperand RO> :1864 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),1865 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {1866 let DecoderMethod = "DecodeMem";1867 let mayStore = 1;1868 let Constraints = "$rt = $dst";1869}1870 1871class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,1872 InstrItinClass itin> :1873 InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),1874 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> {1875 let BaseOpcode = asmstr;1876}1877 1878class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,1879 InstrItinClass itin> :1880 InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),1881 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> {1882 let BaseOpcode = asmstr;1883}1884 1885class TrapBase<Instruction RealInst>1886 : PseudoSE<(outs), (ins), [(trap)], II_TRAP>,1887 PseudoInstExpansion<(RealInst 0, 0)> {1888 let mayStore = 0;1889 let mayLoad = 0;1890 let hasSideEffects = 1;1891 let isTrap = 1;1892 let isCodeGenOnly = 1;1893}1894 1895//===----------------------------------------------------------------------===//1896// Pseudo instructions1897//===----------------------------------------------------------------------===//1898 1899// Return RA.1900let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, isCTI=1 in {1901 let hasDelaySlot=1 in1902 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;1903 1904 let hasSideEffects=1 in1905 def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;1906}1907 1908let Defs = [SP], Uses = [SP], hasSideEffects = 1, hasNoSchedulingInfo = 1 in {1909def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),1910 [(callseq_start timm:$amt1, timm:$amt2)]>;1911def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),1912 [(callseq_end timm:$amt1, timm:$amt2)]>;1913}1914 1915let usesCustomInserter = 1 in {1916 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_i8, GPR32>;1917 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_i16, GPR32>;1918 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_i32, GPR32>;1919 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_i8, GPR32>;1920 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_i16, GPR32>;1921 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_i32, GPR32>;1922 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_i8, GPR32>;1923 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_i16, GPR32>;1924 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_i32, GPR32>;1925 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_i8, GPR32>;1926 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_i16, GPR32>;1927 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_i32, GPR32>;1928 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_i8, GPR32>;1929 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_i16, GPR32>;1930 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_i32, GPR32>;1931 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_i8, GPR32>;1932 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_i16, GPR32>;1933 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_i32, GPR32>;1934 1935 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_i8, GPR32>;1936 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_i16, GPR32>;1937 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_i32, GPR32>;1938 1939 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_i8, GPR32>;1940 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_i16, GPR32>;1941 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_i32, GPR32>;1942 1943 def ATOMIC_LOAD_MIN_I8 : Atomic2Ops<atomic_load_min_i8, GPR32>;1944 def ATOMIC_LOAD_MIN_I16 : Atomic2Ops<atomic_load_min_i16, GPR32>;1945 def ATOMIC_LOAD_MIN_I32 : Atomic2Ops<atomic_load_min_i32, GPR32>;1946 def ATOMIC_LOAD_MAX_I8 : Atomic2Ops<atomic_load_max_i8, GPR32>;1947 def ATOMIC_LOAD_MAX_I16 : Atomic2Ops<atomic_load_max_i16, GPR32>;1948 def ATOMIC_LOAD_MAX_I32 : Atomic2Ops<atomic_load_max_i32, GPR32>;1949 def ATOMIC_LOAD_UMIN_I8 : Atomic2Ops<atomic_load_umin_i8, GPR32>;1950 def ATOMIC_LOAD_UMIN_I16 : Atomic2Ops<atomic_load_umin_i16, GPR32>;1951 def ATOMIC_LOAD_UMIN_I32 : Atomic2Ops<atomic_load_umin_i32, GPR32>;1952 def ATOMIC_LOAD_UMAX_I8 : Atomic2Ops<atomic_load_umax_i8, GPR32>;1953 def ATOMIC_LOAD_UMAX_I16 : Atomic2Ops<atomic_load_umax_i16, GPR32>;1954 def ATOMIC_LOAD_UMAX_I32 : Atomic2Ops<atomic_load_umax_i32, GPR32>;1955}1956 1957def ATOMIC_LOAD_ADD_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1958def ATOMIC_LOAD_ADD_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1959def ATOMIC_LOAD_ADD_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1960def ATOMIC_LOAD_SUB_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1961def ATOMIC_LOAD_SUB_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1962def ATOMIC_LOAD_SUB_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1963def ATOMIC_LOAD_AND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1964def ATOMIC_LOAD_AND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1965def ATOMIC_LOAD_AND_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1966def ATOMIC_LOAD_OR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1967def ATOMIC_LOAD_OR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1968def ATOMIC_LOAD_OR_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1969def ATOMIC_LOAD_XOR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1970def ATOMIC_LOAD_XOR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1971def ATOMIC_LOAD_XOR_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1972def ATOMIC_LOAD_NAND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1973def ATOMIC_LOAD_NAND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1974def ATOMIC_LOAD_NAND_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1975 1976def ATOMIC_SWAP_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1977def ATOMIC_SWAP_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1978def ATOMIC_SWAP_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1979 1980def ATOMIC_CMP_SWAP_I8_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>;1981def ATOMIC_CMP_SWAP_I16_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>;1982def ATOMIC_CMP_SWAP_I32_POSTRA : AtomicCmpSwapPostRA<GPR32>;1983 1984def ATOMIC_LOAD_MIN_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1985def ATOMIC_LOAD_MIN_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1986def ATOMIC_LOAD_MIN_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1987def ATOMIC_LOAD_MAX_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1988def ATOMIC_LOAD_MAX_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1989def ATOMIC_LOAD_MAX_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1990def ATOMIC_LOAD_UMIN_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1991def ATOMIC_LOAD_UMIN_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1992def ATOMIC_LOAD_UMIN_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1993def ATOMIC_LOAD_UMAX_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1994def ATOMIC_LOAD_UMAX_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>;1995def ATOMIC_LOAD_UMAX_I32_POSTRA : Atomic2OpsPostRA<GPR32>;1996 1997/// Pseudo instructions for loading and storing accumulator registers.1998let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {1999 def LOAD_ACC64 : Load<"", ACC64>;2000 def STORE_ACC64 : Store<"", ACC64>;2001}2002 2003// We need these two pseudo instructions to avoid offset calculation for long2004// branches. See the comment in file MipsLongBranch.cpp for detailed2005// explanation.2006 2007// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt - $baltgt)2008def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),2009 (ins brtarget:$tgt, brtarget:$baltgt), []> {2010 bit hasNoSchedulingInfo = 1;2011}2012// Expands to: lui $dst, highest/%higher/%hi/%lo($tgt)2013def LONG_BRANCH_LUi2Op : PseudoSE<(outs GPR32Opnd:$dst),2014 (ins brtarget:$tgt), []> {2015 bit hasNoSchedulingInfo = 1;2016}2017 2018// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt - $baltgt)2019def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),2020 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {2021 bit hasNoSchedulingInfo = 1;2022}2023// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt)2024def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst),2025 (ins GPR32Opnd:$src, brtarget:$tgt), []> {2026 bit hasNoSchedulingInfo = 1;2027}2028 2029//===----------------------------------------------------------------------===//2030// Instruction definition2031//===----------------------------------------------------------------------===//2032//===----------------------------------------------------------------------===//2033// MipsI Instructions2034//===----------------------------------------------------------------------===//2035 2036/// Arithmetic Instructions (ALU Immediate)2037let AdditionalPredicates = [NotInMicroMips] in {2038 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,2039 II_ADDIU, imm32SExt16, add>,2040 ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;2041 2042 def ANDi : MMRel, StdMMR6Rel,2043 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, imm32ZExt16, and>,2044 ADDI_FM<0xc>, ISA_MIPS1;2045 def ORi : MMRel, StdMMR6Rel,2046 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, imm32ZExt16, or>,2047 ADDI_FM<0xd>, ISA_MIPS1;2048 def XORi : MMRel, StdMMR6Rel,2049 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, imm32ZExt16, xor>,2050 ADDI_FM<0xe>, ISA_MIPS1;2051 def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>,2052 ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6;2053 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,2054 SLTI_FM<0xa>, ISA_MIPS1;2055 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,2056 SLTI_FM<0xb>, ISA_MIPS1;2057 2058 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM,2059 ISA_MIPS1;2060 2061 /// Arithmetic Instructions (3-Operand, R-Type)2062 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,2063 ADD_FM<0, 0x21>, ISA_MIPS1;2064 def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,2065 ADD_FM<0, 0x23>, ISA_MIPS1;2066 2067 let Defs = [HI0, LO0] in2068 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,2069 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;2070 2071 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,2072 ADD_FM<0, 0x20>, ISA_MIPS1;2073 def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,2074 ADD_FM<0, 0x22>, ISA_MIPS1;2075 2076 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,2077 ISA_MIPS1;2078 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,2079 ISA_MIPS1;2080 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,2081 ADD_FM<0, 0x24>, ISA_MIPS1;2082 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,2083 ADD_FM<0, 0x25>, ISA_MIPS1;2084 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,2085 ADD_FM<0, 0x26>, ISA_MIPS1;2086 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>,2087 ISA_MIPS1;2088}2089 2090let AdditionalPredicates = [NotInMicroMips] in {2091 /// Shift Instructions2092 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, mshl_32,2093 immZExt5>, SRA_FM<0, 0>, ISA_MIPS1;2094 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, msrl_32,2095 immZExt5>, SRA_FM<2, 0>, ISA_MIPS1;2096 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, msra_32,2097 immZExt5>, SRA_FM<3, 0>, ISA_MIPS1;2098 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, mshl_32>,2099 SRLV_FM<4, 0>, ISA_MIPS1;2100 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, msrl_32>,2101 SRLV_FM<6, 0>, ISA_MIPS1;2102 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, msra_32>,2103 SRLV_FM<7, 0>, ISA_MIPS1;2104 2105 // Rotate Instructions2106 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,2107 immZExt5>,2108 SRA_FM<2, 1>, ISA_MIPS32R2;2109 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,2110 SRLV_FM<6, 1>, ISA_MIPS32R2;2111}2112 2113/// Load and Store Instructions2114/// aligned2115let AdditionalPredicates = [NotInMicroMips] in {2116 def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,2117 LW_FM<0x20>, ISA_MIPS1;2118 def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,2119 addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1;2120 def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,2121 addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1;2122 def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,2123 MMRel, LW_FM<0x25>, ISA_MIPS1;2124 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,2125 LW_FM<0x23>, ISA_MIPS1;2126 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,2127 LW_FM<0x28>, ISA_MIPS1;2128 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,2129 ISA_MIPS1;2130 def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>,2131 MMRel, LW_FM<0x2b>, ISA_MIPS1;2132}2133 2134/// load/store left/right2135let AdditionalPredicates = [NotInMicroMips] in {2136def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,2137 ISA_MIPS1_NOT_32R6_64R6;2138def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,2139 ISA_MIPS1_NOT_32R6_64R6;2140def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,2141 ISA_MIPS1_NOT_32R6_64R6;2142def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,2143 ISA_MIPS1_NOT_32R6_64R6;2144 2145// COP2 Memory Instructions2146def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>,2147 ISA_MIPS1_NOT_32R6_64R6;2148def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>,2149 LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6;2150def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>,2151 ISA_MIPS2_NOT_32R6_64R6;2152def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>,2153 LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6;2154 2155// COP3 Memory Instructions2156let DecoderNamespace = "COP3_" in {2157 def LWC3 : LW_FT3<"lwc3", COP3Opnd, II_LWC3, load>, LW_FM<0x33>,2158 ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS;2159 def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>,2160 ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS;2161 def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>,2162 ISA_MIPS2, NOT_ASE_CNMIPS;2163 def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,2164 ISA_MIPS2, NOT_ASE_CNMIPS;2165}2166 2167 def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;2168 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM,2169 ISA_MIPS32R2;2170}2171 2172let AdditionalPredicates = [NotInMicroMips] in {2173 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>,2174 ISA_MIPS2;2175 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>,2176 ISA_MIPS2;2177 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>,2178 ISA_MIPS2;2179 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>,2180 ISA_MIPS2;2181 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>,2182 ISA_MIPS2;2183 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>,2184 ISA_MIPS2;2185 2186 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>,2187 ISA_MIPS2_NOT_32R6_64R6;2188 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>,2189 ISA_MIPS2_NOT_32R6_64R6;2190 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>,2191 ISA_MIPS2_NOT_32R6_64R6;2192 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>,2193 ISA_MIPS2_NOT_32R6_64R6;2194 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>,2195 ISA_MIPS2_NOT_32R6_64R6;2196 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>,2197 ISA_MIPS2_NOT_32R6_64R6;2198}2199 2200let AdditionalPredicates = [NotInMicroMips] in {2201 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1;2202 def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>,2203 ISA_MIPS1;2204 def TRAP : TrapBase<BREAK>, ISA_MIPS1;2205 def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM,2206 ISA_MIPS32_NOT_32R6_64R6;2207 2208 def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32;2209 def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>,2210 ISA_MIPS32R5;2211 def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32;2212 2213 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>,2214 ISA_MIPS32R2;2215 def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>,2216 ISA_MIPS32R2;2217 2218 def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32;2219}2220 2221let AdditionalPredicates = [NotInMicroMips] in {2222/// Load-linked, Store-conditional2223def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;2224def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;2225}2226/// Jump and Branch Instructions2227let AdditionalPredicates = [NotInMicroMips, RelocNotPIC] in2228def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,2229 IsBranch, ISA_MIPS1;2230 2231let AdditionalPredicates = [NotInMicroMips] in {2232def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>,2233 ISA_MIPS1_NOT_32R6_64R6;2234def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,2235 ISA_MIPS1;2236def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,2237 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;2238def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,2239 ISA_MIPS1;2240def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,2241 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;2242def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,2243 BGEZ_FM<1, 1>, ISA_MIPS1;2244def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>,2245 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;2246def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,2247 BGEZ_FM<7, 0>, ISA_MIPS1;2248def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>,2249 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;2250def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,2251 BGEZ_FM<6, 0>, ISA_MIPS1;2252def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>,2253 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;2254def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,2255 BGEZ_FM<1, 0>, ISA_MIPS1;2256def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>,2257 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;2258def B : UncondBranch<BEQ, brtarget>, ISA_MIPS1;2259 2260def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1;2261 2262}2263 2264let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in {2265 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1;2266 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1;2267}2268 2269let AdditionalPredicates = [NotInMicroMips] in {2270 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,2271 ISA_MIPS32_NOT_32R6_64R6;2272 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,2273 ISA_MIPS1_NOT_32R6_64R6;2274 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,2275 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;2276 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,2277 ISA_MIPS1_NOT_32R6_64R6;2278 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,2279 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;2280 def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>, ISA_MIPS1;2281}2282let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {2283 def TAILCALL : TailCall<J, jmptarget>, ISA_MIPS1;2284}2285let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,2286 NoIndirectJumpGuards] in2287 def TAILCALLREG : TailCallReg<JR, GPR32Opnd>, ISA_MIPS1_NOT_32R6_64R6;2288 2289// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch642290// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.2291class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> :2292 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],2293 II_IndirectBranchPseudo>,2294 PseudoInstExpansion<(JumpInst RO:$rs)> {2295 let isTerminator=1;2296 let isBarrier=1;2297 let hasDelaySlot = 1;2298 let isBranch = 1;2299 let isIndirectBranch = 1;2300 bit isCTI = 1;2301}2302 2303let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,2304 NoIndirectJumpGuards] in2305 def PseudoIndirectBranch : PseudoIndirectBranchBase<JR, GPR32Opnd>,2306 ISA_MIPS1_NOT_32R6_64R6;2307 2308// Return instructions are matched as a RetRA instruction, then are expanded2309// into PseudoReturn/PseudoReturn64 after register allocation. Finally,2310// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the2311// ISA.2312class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),2313 [], II_ReturnPseudo> {2314 let isTerminator = 1;2315 let isBarrier = 1;2316 let hasDelaySlot = 1;2317 let isReturn = 1;2318 let isCodeGenOnly = 1;2319 let hasCtrlDep = 1;2320 let hasExtraSrcRegAllocReq = 1;2321 bit isCTI = 1;2322}2323 2324def PseudoReturn : PseudoReturnBase<GPR32Opnd>;2325 2326// Exception handling related node and instructions.2327// The conversion sequence is:2328// ISD::EH_RETURN -> MipsISD::EH_RETURN ->2329// MIPSeh_return -> (stack change + indirect branch)2330//2331// MIPSeh_return takes the place of regular return instruction2332// but takes two arguments (V1, V0) which are used for storing2333// the offset and return address respectively.2334def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;2335 2336def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,2337 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;2338 2339let Uses = [V0, V1], isTerminator = 1, isReturn = 1,2340 isBarrier = 1, isCTI = 1, hasNoSchedulingInfo = 1 in {2341 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),2342 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;2343 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, GPR64:$dst),2344 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;2345}2346 2347/// Multiply and Divide Instructions.2348let AdditionalPredicates = [NotInMicroMips] in {2349 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,2350 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;2351 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,2352 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;2353 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,2354 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;2355 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,2356 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;2357 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,2358 ISA_MIPS1_NOT_32R6_64R6;2359 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,2360 ISA_MIPS1_NOT_32R6_64R6;2361 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,2362 ISA_MIPS1_NOT_32R6_64R6;2363 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,2364 ISA_MIPS1_NOT_32R6_64R6;2365 2366 /// Sign Ext In Register Instructions.2367 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,2368 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;2369 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,2370 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;2371 2372 /// Count Leading2373 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,2374 ISA_MIPS32_NOT_32R6_64R6;2375 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,2376 ISA_MIPS32_NOT_32R6_64R6;2377 2378 /// Word Swap Bytes Within Halfwords2379 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,2380 ISA_MIPS32R2;2381 2382 /// No operation.2383 def NOP : PseudoSE<(outs), (ins), []>,2384 PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1;2385 2386 // FrameIndexes are legalized when they are operands from load/store2387 // instructions. The same not happens for stack address copies, so an2388 // add op with mem ComplexPattern is used and the stack address copy2389 // can be matched. It's similar to Sparc LEA_ADDRi2390 let AdditionalPredicates = [NotInMicroMips] in2391 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>,2392 ISA_MIPS1;2393 2394 // MADD*/MSUB*2395 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,2396 ISA_MIPS32_NOT_32R6_64R6;2397 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,2398 ISA_MIPS32_NOT_32R6_64R6;2399 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,2400 ISA_MIPS32_NOT_32R6_64R6;2401 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,2402 ISA_MIPS32_NOT_32R6_64R6;2403}2404 2405let AdditionalPredicates = [NotDSP] in {2406def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,2407 ISA_MIPS1_NOT_32R6_64R6;2408def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,2409 ISA_MIPS1_NOT_32R6_64R6;2410def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;2411def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;2412def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;2413def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,2414 ISA_MIPS32_NOT_32R6_64R6;2415def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,2416 ISA_MIPS32_NOT_32R6_64R6;2417def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,2418 ISA_MIPS32_NOT_32R6_64R6;2419def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,2420 ISA_MIPS32_NOT_32R6_64R6;2421}2422 2423let AdditionalPredicates = [NotInMicroMips] in {2424 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,2425 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;2426 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,2427 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;2428 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM, ISA_MIPS1;2429 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction2430 def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,2431 immZExt5, immZExt5Plus1, MipsExt>,2432 EXT_FM<0>, ISA_MIPS32R2;2433 def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,2434 uimm5_inssize_plus1, immZExt5,2435 immZExt5Plus1>,2436 EXT_FM<4>, ISA_MIPS32R2;2437}2438/// Move Control Registers From/To CPU Registers2439let AdditionalPredicates = [NotInMicroMips] in {2440 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>,2441 MFC3OP_FM<0x10, 4, 0>, ISA_MIPS1;2442 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>,2443 MFC3OP_FM<0x10, 0, 0>, ISA_MIPS1;2444 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>,2445 MFC3OP_FM<0x12, 0, 0>, ISA_MIPS1;2446 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>,2447 MFC3OP_FM<0x12, 4, 0>, ISA_MIPS1;2448}2449 2450class Barrier<string asmstr, InstrItinClass itin = NoItinerary> :2451 InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;2452let AdditionalPredicates = [NotInMicroMips] in {2453 def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>,2454 ISA_MIPS1;2455 def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1;2456 2457 let isCTI = 1 in2458 def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,2459 ISA_MIPS32R2;2460}2461 2462// JR_HB and JALR_HB are defined here using the new style naming2463// scheme because some of this code is shared with Mips32r6InstrInfo.td2464// and because of that it doesn't follow the naming convention of the2465// rest of the file. To avoid a mixture of old vs new style, the new2466// style was chosen.2467class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {2468 dag OutOperandList = (outs);2469 dag InOperandList = (ins GPROpnd:$rs);2470 string AsmString = !strconcat(instr_asm, "\t$rs");2471 list<dag> Pattern = [];2472}2473 2474class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {2475 dag OutOperandList = (outs GPROpnd:$rd);2476 dag InOperandList = (ins GPROpnd:$rs);2477 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");2478 list<dag> Pattern = [];2479}2480 2481class JR_HB_DESC<RegisterOperand RO> :2482 InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {2483 let isBranch=1;2484 let isIndirectBranch=1;2485 let hasDelaySlot=1;2486 let isTerminator=1;2487 let isBarrier=1;2488 bit isCTI = 1;2489}2490 2491class JALR_HB_DESC<RegisterOperand RO> :2492 InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>, JALR_HB_DESC_BASE<"jalr.hb",2493 RO> {2494 let isIndirectBranch=1;2495 let hasDelaySlot=1;2496 bit isCTI = 1;2497}2498 2499class JR_HB_ENC : JR_HB_FM<8>;2500class JALR_HB_ENC : JALR_HB_FM<9>;2501 2502def JR_HB : JR_HB_DESC<GPR32Opnd>, JR_HB_ENC, ISA_MIPS32R2_NOT_32R6_64R6;2503def JALR_HB : JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32;2504 2505let AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in2506 def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, RA>;2507 2508 2509let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,2510 UseIndirectJumpsHazard] in {2511 def TAILCALLREGHB : TailCallReg<JR_HB, GPR32Opnd>, ISA_MIPS32_NOT_32R6_64R6;2512 def PseudoIndirectHazardBranch : PseudoIndirectBranchBase<JR_HB, GPR32Opnd>,2513 ISA_MIPS32R2_NOT_32R6_64R6;2514}2515 2516class TLB<string asmstr, InstrItinClass itin = NoItinerary> :2517 InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;2518let AdditionalPredicates = [NotInMicroMips] in {2519 def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>, ISA_MIPS1;2520 def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>, ISA_MIPS1;2521 def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>, ISA_MIPS1;2522 def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>, ISA_MIPS1;2523}2524class CacheOp<string instr_asm, Operand MemOpnd,2525 InstrItinClass itin = NoItinerary> :2526 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),2527 !strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther,2528 instr_asm> {2529 let DecoderMethod = "DecodeCacheOp";2530}2531 2532let AdditionalPredicates = [NotInMicroMips] in {2533 def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,2534 INSN_MIPS3_32_NOT_32R6_64R6;2535 def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,2536 INSN_MIPS3_32_NOT_32R6_64R6;2537}2538// FIXME: We are missing the prefx instruction.2539def ROL : MipsAsmPseudoInst<(outs),2540 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),2541 "rol\t$rs, $rt, $rd">;2542def ROLImm : MipsAsmPseudoInst<(outs),2543 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),2544 "rol\t$rs, $rt, $imm">;2545def : MipsInstAlias<"rol $rd, $rs",2546 (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;2547def : MipsInstAlias<"rol $rd, $imm",2548 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;2549 2550def ROR : MipsAsmPseudoInst<(outs),2551 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),2552 "ror\t$rs, $rt, $rd">;2553def RORImm : MipsAsmPseudoInst<(outs),2554 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),2555 "ror\t$rs, $rt, $imm">;2556def : MipsInstAlias<"ror $rd, $rs",2557 (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;2558def : MipsInstAlias<"ror $rd, $imm",2559 (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;2560 2561def DROL : MipsAsmPseudoInst<(outs),2562 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),2563 "drol\t$rs, $rt, $rd">, ISA_MIPS64;2564def DROLImm : MipsAsmPseudoInst<(outs),2565 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),2566 "drol\t$rs, $rt, $imm">, ISA_MIPS64;2567def : MipsInstAlias<"drol $rd, $rs",2568 (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,2569 ISA_MIPS64;2570def : MipsInstAlias<"drol $rd, $imm",2571 (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,2572 ISA_MIPS64;2573 2574def DROR : MipsAsmPseudoInst<(outs),2575 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),2576 "dror\t$rs, $rt, $rd">, ISA_MIPS64;2577def DRORImm : MipsAsmPseudoInst<(outs),2578 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),2579 "dror\t$rs, $rt, $imm">, ISA_MIPS64;2580def : MipsInstAlias<"dror $rd, $rs",2581 (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,2582 ISA_MIPS64;2583def : MipsInstAlias<"dror $rd, $imm",2584 (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,2585 ISA_MIPS64;2586 2587def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),2588 "abs\t$rd, $rs">;2589 2590def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2591 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2592 "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS;2593 2594def : MipsInstAlias<"seq $rd, $rs",2595 (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,2596 NOT_ASE_CNMIPS;2597 2598def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2599 (ins GPR32Opnd:$rs, simm32_relaxed:$imm),2600 "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS;2601 2602def : MipsInstAlias<"seq $rd, $imm",2603 (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,2604 NOT_ASE_CNMIPS;2605 2606def SNEMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2607 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2608 "sne $rd, $rs, $rt">, NOT_ASE_CNMIPS;2609 2610def : MipsInstAlias<"sne $rd, $rs",2611 (SNEMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,2612 NOT_ASE_CNMIPS;2613 2614def SNEIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2615 (ins GPR32Opnd:$rs, simm32_relaxed:$imm),2616 "sne $rd, $rs, $imm">, NOT_ASE_CNMIPS;2617 2618def : MipsInstAlias<"sne $rd, $imm",2619 (SNEIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,2620 NOT_ASE_CNMIPS;2621 2622def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,2623 simm32_relaxed:$imm),2624 "mul\t$rd, $rs, $imm">,2625 ISA_MIPS1_NOT_32R6_64R6;2626def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,2627 GPR32Opnd:$rt),2628 "mulo\t$rd, $rs, $rt">,2629 ISA_MIPS1_NOT_32R6_64R6;2630def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,2631 GPR32Opnd:$rt),2632 "mulou\t$rd, $rs, $rt">,2633 ISA_MIPS1_NOT_32R6_64R6;2634 2635// Virtualization ASE2636class HYPCALL_FT<string opstr> :2637 InstSE<(outs), (ins uimm10:$code_),2638 !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther, opstr> {2639 let BaseOpcode = opstr;2640}2641 2642let AdditionalPredicates = [NotInMicroMips] in {2643 def MFGC0 : MMRel, MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,2644 MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32R5, ASE_VIRT;2645 def MTGC0 : MMRel, MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,2646 MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32R5, ASE_VIRT;2647 def MFHGC0 : MMRel, MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,2648 MFC3OP_FM<0x10, 3, 4>, ISA_MIPS32R5, ASE_VIRT;2649 def MTHGC0 : MMRel, MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,2650 MFC3OP_FM<0x10, 3, 6>, ISA_MIPS32R5, ASE_VIRT;2651 def TLBGINV : MMRel, TLB<"tlbginv", II_TLBGINV>, COP0_TLB_FM<0b001011>,2652 ISA_MIPS32R5, ASE_VIRT;2653 def TLBGINVF : MMRel, TLB<"tlbginvf", II_TLBGINVF>, COP0_TLB_FM<0b001100>,2654 ISA_MIPS32R5, ASE_VIRT;2655 def TLBGP : MMRel, TLB<"tlbgp", II_TLBGP>, COP0_TLB_FM<0b010000>,2656 ISA_MIPS32R5, ASE_VIRT;2657 def TLBGR : MMRel, TLB<"tlbgr", II_TLBGR>, COP0_TLB_FM<0b001001>,2658 ISA_MIPS32R5, ASE_VIRT;2659 def TLBGWI : MMRel, TLB<"tlbgwi", II_TLBGWI>, COP0_TLB_FM<0b001010>,2660 ISA_MIPS32R5, ASE_VIRT;2661 def TLBGWR : MMRel, TLB<"tlbgwr", II_TLBGWR>, COP0_TLB_FM<0b001110>,2662 ISA_MIPS32R5, ASE_VIRT;2663 def HYPCALL : MMRel, HYPCALL_FT<"hypcall">,2664 HYPCALL_FM<0b101000>, ISA_MIPS32R5, ASE_VIRT;2665}2666 2667//===----------------------------------------------------------------------===//2668// Instruction aliases2669//===----------------------------------------------------------------------===//2670 2671multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic,2672 Instruction Opcode,2673 RegisterOperand RO = GPR32Opnd,2674 Operand Imm = simm32_relaxed> {2675 def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"),2676 (Opcode RO:$rs,2677 RO:$rt,2678 Imm:$imm), 0>;2679 def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"),2680 (Opcode RO:$rs,2681 RO:$rs,2682 Imm:$imm), 0>;2683}2684 2685let AdditionalPredicates = [NotInMicroMips] in {2686 def : MipsInstAlias<"move $dst, $src",2687 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,2688 GPR_32, ISA_MIPS1;2689 def : MipsInstAlias<"move $dst, $src",2690 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,2691 GPR_32, ISA_MIPS1;2692 2693 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>,2694 ISA_MIPS1_NOT_32R6_64R6;2695 2696 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>, ISA_MIPS1;2697 2698 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;2699 2700 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>,2701 ISA_MIPS32;2702 2703 def : MipsInstAlias<"neg $rt, $rs",2704 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;2705 def : MipsInstAlias<"neg $rt",2706 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;2707 def : MipsInstAlias<"negu $rt, $rs",2708 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;2709 def : MipsInstAlias<"negu $rt",2710 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;2711 2712 def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2713 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2714 "sge\t$rd, $rs, $rt">, ISA_MIPS1;2715 def : MipsInstAlias<"sge $rs, $rt",2716 (SGE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2717 ISA_MIPS1;2718 def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2719 (ins GPR32Opnd:$rs, simm32:$imm),2720 "sge\t$rd, $rs, $imm">, GPR_32;2721 def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs,2722 GPR32Opnd:$rs,2723 simm32:$imm), 0>,2724 GPR_32;2725 2726 def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2727 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2728 "sgeu\t$rd, $rs, $rt">, ISA_MIPS1;2729 def : MipsInstAlias<"sgeu $rs, $rt",2730 (SGEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2731 ISA_MIPS1;2732 def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2733 (ins GPR32Opnd:$rs, uimm32_coerced:$imm),2734 "sgeu\t$rd, $rs, $imm">, GPR_32;2735 def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs,2736 GPR32Opnd:$rs,2737 uimm32_coerced:$imm), 0>,2738 GPR_32;2739 2740 def : MipsInstAlias<2741 "sgt $rd, $rs, $rt",2742 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;2743 def : MipsInstAlias<2744 "sgt $rs, $rt",2745 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;2746 2747 def SGTImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2748 (ins GPR32Opnd:$rs, simm32:$imm),2749 "sgt\t$rd, $rs, $imm">, GPR_32;2750 def : MipsInstAlias<"sgt $rs, $imm", (SGTImm GPR32Opnd:$rs,2751 GPR32Opnd:$rs,2752 simm32:$imm), 0>,2753 GPR_32;2754 def : MipsInstAlias<2755 "sgtu $rd, $rs, $rt",2756 (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;2757 def : MipsInstAlias<2758 "sgtu $$rs, $rt",2759 (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;2760 2761 def SGTUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2762 (ins GPR32Opnd:$rs, uimm32_coerced:$imm),2763 "sgtu\t$rd, $rs, $imm">, GPR_32;2764 def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm GPR32Opnd:$rs,2765 GPR32Opnd:$rs,2766 uimm32_coerced:$imm), 0>,2767 GPR_32;2768 2769 def SLE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2770 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2771 "sle\t$rd, $rs, $rt">, ISA_MIPS1;2772 def : MipsInstAlias<"sle $rs, $rt",2773 (SLE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2774 ISA_MIPS1;2775 def SLEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2776 (ins GPR32Opnd:$rs, simm32:$imm),2777 "sle\t$rd, $rs, $imm">, GPR_32;2778 def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs,2779 GPR32Opnd:$rs,2780 simm32:$imm), 0>,2781 GPR_32;2782 2783 def SLEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2784 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),2785 "sleu\t$rd, $rs, $rt">, ISA_MIPS1;2786 def : MipsInstAlias<"sleu $rs, $rt",2787 (SLEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2788 ISA_MIPS1;2789 def SLEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),2790 (ins GPR32Opnd:$rs, uimm32_coerced:$imm),2791 "sleu\t$rd, $rs, $imm">, GPR_32;2792 def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm GPR32Opnd:$rs,2793 GPR32Opnd:$rs,2794 uimm32_coerced:$imm), 0>,2795 GPR_32;2796 2797 def : MipsInstAlias<2798 "not $rt, $rs",2799 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;2800 def : MipsInstAlias<2801 "not $rt",2802 (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1;2803 2804 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;2805 2806 defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>,2807 ISA_MIPS1_NOT_32R6_64R6;2808 2809 defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1;2810 2811 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, ISA_MIPS1, GPR_32;2812 2813 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, ISA_MIPS1, GPR_32;2814 2815 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, ISA_MIPS1, GPR_32;2816 2817 defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, ISA_MIPS1, GPR_32;2818 2819 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32;2820 2821 def : MipsInstAlias<"mfgc0 $rt, $rd",2822 (MFGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,2823 ISA_MIPS32R5, ASE_VIRT;2824 def : MipsInstAlias<"mtgc0 $rt, $rd",2825 (MTGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,2826 ISA_MIPS32R5, ASE_VIRT;2827 def : MipsInstAlias<"mfhgc0 $rt, $rd",2828 (MFHGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,2829 ISA_MIPS32R5, ASE_VIRT;2830 def : MipsInstAlias<"mthgc0 $rt, $rd",2831 (MTHGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,2832 ISA_MIPS32R5, ASE_VIRT;2833 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,2834 ISA_MIPS1;2835 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,2836 ISA_MIPS1;2837 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>,2838 ISA_MIPS1;2839 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>,2840 ISA_MIPS1;2841 2842 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>,2843 ISA_MIPS1;2844 2845 def : MipsInstAlias<"bnez $rs,$offset",2846 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,2847 ISA_MIPS1;2848 def : MipsInstAlias<"bnezl $rs, $offset",2849 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>,2850 ISA_MIPS2;2851 def : MipsInstAlias<"beqz $rs,$offset",2852 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,2853 ISA_MIPS1;2854 def : MipsInstAlias<"beqzl $rs, $offset",2855 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>,2856 ISA_MIPS2;2857 2858 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1;2859 2860 def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1;2861 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1;2862 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;2863 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;2864 2865 def : MipsInstAlias<"teq $rs, $rt",2866 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2867 def : MipsInstAlias<"tge $rs, $rt",2868 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2869 def : MipsInstAlias<"tgeu $rs, $rt",2870 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2871 def : MipsInstAlias<"tlt $rs, $rt",2872 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2873 def : MipsInstAlias<"tltu $rs, $rt",2874 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2875 def : MipsInstAlias<"tne $rs, $rt",2876 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;2877 def : MipsInstAlias<"rdhwr $rt, $rs",2878 (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, ISA_MIPS1;2879 2880}2881def : MipsInstAlias<"sub, $rd, $rs, $imm",2882 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,2883 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;2884def : MipsInstAlias<"sub $rs, $imm",2885 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),2886 0>, ISA_MIPS1_NOT_32R6_64R6;2887def : MipsInstAlias<"subu, $rd, $rs, $imm",2888 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,2889 InvertedImOperand:$imm), 0>;2890def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,2891 InvertedImOperand:$imm), 0>;2892let AdditionalPredicates = [NotInMicroMips] in {2893 def : MipsInstAlias<"sll $rd, $rt, $rs",2894 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;2895 def : MipsInstAlias<"sra $rd, $rt, $rs",2896 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;2897 def : MipsInstAlias<"srl $rd, $rt, $rs",2898 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;2899 def : MipsInstAlias<"sll $rd, $rt",2900 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;2901 def : MipsInstAlias<"sra $rd, $rt",2902 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;2903 def : MipsInstAlias<"srl $rd, $rt",2904 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;2905 def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,2906 ISA_MIPS32R2;2907 def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,2908 ISA_MIPS32R2;2909}2910def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;2911let AdditionalPredicates = [NotInMicroMips] in2912 def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2;2913 2914def : MipsInstAlias<"mulo $rs, $rt",2915 (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2916 ISA_MIPS1_NOT_32R6_64R6;2917def : MipsInstAlias<"mulou $rs, $rt",2918 (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,2919 ISA_MIPS1_NOT_32R6_64R6;2920 2921let AdditionalPredicates = [NotInMicroMips] in2922 def : MipsInstAlias<"hypcall", (HYPCALL 0), 1>, ISA_MIPS32R5, ASE_VIRT;2923 2924//===----------------------------------------------------------------------===//2925// Assembler Pseudo Instructions2926//===----------------------------------------------------------------------===//2927 2928// We use uimm32_coerced to accept a 33 bit signed number that is rendered into2929// a 32 bit number.2930class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :2931 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),2932 !strconcat(instr_asm, "\t$rt, $imm32")> ;2933def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>;2934 2935class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,2936 RegisterOperand RO> :2937 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),2938 !strconcat(instr_asm, "\t$rt, $addr")> ;2939def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;2940 2941class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :2942 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),2943 !strconcat(instr_asm, "\t$rt, $imm32")> ;2944def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>;2945 2946def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),2947 "jal\t$rd, $rs"> ;2948def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),2949 "jal\t$rs"> ;2950 2951class NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> :2952 MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm),2953 "nor\t$rs, $rt, $imm">;2954def NORImm : NORIMM_DESC_BASE<GPR32Opnd, simm32_relaxed>, GPR_32;2955def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,2956 simm32_relaxed:$imm)>, GPR_32;2957 2958let hasDelaySlot = 1, isCTI = 1 in {2959def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),2960 (ins ConstantImm64:$imm64, brtarget:$offset),2961 "bne\t$rt, $imm64, $offset">;2962def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),2963 (ins ConstantImm64:$imm64, brtarget:$offset),2964 "beq\t$rt, $imm64, $offset">;2965 2966class CondBranchPseudo<string instr_asm> :2967 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,2968 brtarget:$offset),2969 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;2970}2971 2972def BLT : CondBranchPseudo<"blt">;2973def BLE : CondBranchPseudo<"ble">;2974def BGE : CondBranchPseudo<"bge">;2975def BGT : CondBranchPseudo<"bgt">;2976def BLTU : CondBranchPseudo<"bltu">;2977def BLEU : CondBranchPseudo<"bleu">;2978def BGEU : CondBranchPseudo<"bgeu">;2979def BGTU : CondBranchPseudo<"bgtu">;2980def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;2981def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;2982def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;2983def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;2984def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;2985def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;2986def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;2987def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;2988 2989let isCTI = 1 in2990class CondBranchImmPseudo<string instr_asm> :2991 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, ConstantImm64:$imm, brtarget:$offset),2992 !strconcat(instr_asm, "\t$rs, $imm, $offset")>;2993 2994def BEQLImmMacro : CondBranchImmPseudo<"beql">, ISA_MIPS2_NOT_32R6_64R6;2995def BNELImmMacro : CondBranchImmPseudo<"bnel">, ISA_MIPS2_NOT_32R6_64R6;2996 2997def BLTImmMacro : CondBranchImmPseudo<"blt">;2998def BLEImmMacro : CondBranchImmPseudo<"ble">;2999def BGEImmMacro : CondBranchImmPseudo<"bge">;3000def BGTImmMacro : CondBranchImmPseudo<"bgt">;3001def BLTUImmMacro : CondBranchImmPseudo<"bltu">;3002def BLEUImmMacro : CondBranchImmPseudo<"bleu">;3003def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;3004def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;3005def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;3006def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;3007def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;3008def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;3009def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;3010def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;3011def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;3012def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;3013 3014// FIXME: Predicates are removed because instructions are matched regardless of3015// predicates, because PredicateControl was not in the hierarchy. This was3016// done to emit more precise error message from expansion function.3017// Once the tablegen-erated errors are made better, this needs to be fixed and3018// predicates needs to be restored.3019 3020def SDivMacro : MipsAsmPseudoInst<(outs GPR32NonZeroOpnd:$rd),3021 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),3022 "div\t$rd, $rs, $rt">,3023 ISA_MIPS1_NOT_32R6_64R6;3024def SDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3025 (ins GPR32Opnd:$rs, simm32:$imm),3026 "div\t$rd, $rs, $imm">,3027 ISA_MIPS1_NOT_32R6_64R6;3028def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3029 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),3030 "divu\t$rd, $rs, $rt">,3031 ISA_MIPS1_NOT_32R6_64R6;3032def UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3033 (ins GPR32Opnd:$rs, simm32:$imm),3034 "divu\t$rd, $rs, $imm">,3035 ISA_MIPS1_NOT_32R6_64R6;3036 3037 3038def : MipsInstAlias<"div $rs, $rt", (SDIV GPR32ZeroOpnd:$rs,3039 GPR32Opnd:$rt), 0>,3040 ISA_MIPS1_NOT_32R6_64R6;3041def : MipsInstAlias<"div $rs, $rt", (SDivMacro GPR32NonZeroOpnd:$rs,3042 GPR32NonZeroOpnd:$rs,3043 GPR32Opnd:$rt), 0>,3044 ISA_MIPS1_NOT_32R6_64R6;3045def : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,3046 simm32:$imm), 0>,3047 ISA_MIPS1_NOT_32R6_64R6;3048 3049def : MipsInstAlias<"divu $rt, $rs", (UDIV GPR32ZeroOpnd:$rt,3050 GPR32Opnd:$rs), 0>,3051 ISA_MIPS1_NOT_32R6_64R6;3052def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32NonZeroOpnd:$rt,3053 GPR32NonZeroOpnd:$rt,3054 GPR32Opnd:$rs), 0>,3055 ISA_MIPS1_NOT_32R6_64R6;3056 3057def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,3058 simm32:$imm), 0>,3059 ISA_MIPS1_NOT_32R6_64R6;3060 3061 3062def : MipsInstAlias<"nal", (BLTZAL ZERO, 0), 1>, ISA_MIPS1_NOT_32R6_64R6;3063 3064def SRemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3065 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),3066 "rem\t$rd, $rs, $rt">,3067 ISA_MIPS1_NOT_32R6_64R6;3068def SRemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3069 (ins GPR32Opnd:$rs, simm32_relaxed:$imm),3070 "rem\t$rd, $rs, $imm">,3071 ISA_MIPS1_NOT_32R6_64R6;3072def URemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3073 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),3074 "remu\t$rd, $rs, $rt">,3075 ISA_MIPS1_NOT_32R6_64R6;3076def URemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),3077 (ins GPR32Opnd:$rs, simm32_relaxed:$imm),3078 "remu\t$rd, $rs, $imm">,3079 ISA_MIPS1_NOT_32R6_64R6;3080 3081def : MipsInstAlias<"rem $rt, $rs", (SRemMacro GPR32Opnd:$rt, GPR32Opnd:$rt,3082 GPR32Opnd:$rs), 0>,3083 ISA_MIPS1_NOT_32R6_64R6;3084def : MipsInstAlias<"rem $rd, $imm", (SRemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,3085 simm32_relaxed:$imm), 0>,3086 ISA_MIPS1_NOT_32R6_64R6;3087def : MipsInstAlias<"remu $rt, $rs", (URemMacro GPR32Opnd:$rt, GPR32Opnd:$rt,3088 GPR32Opnd:$rs), 0>,3089 ISA_MIPS1_NOT_32R6_64R6;3090def : MipsInstAlias<"remu $rd, $imm", (URemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,3091 simm32_relaxed:$imm), 0>,3092 ISA_MIPS1_NOT_32R6_64R6;3093 3094def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),3095 "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;3096 3097def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),3098 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;3099 3100def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),3101 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;3102 3103def Ush : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),3104 "ush\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;3105 3106def Usw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),3107 "usw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;3108 3109def LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),3110 (ins mem_simm16:$addr), "ld $rt, $addr">,3111 ISA_MIPS1_NOT_MIPS3;3112def SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),3113 (ins mem_simm16:$addr), "sd $rt, $addr">,3114 ISA_MIPS1_NOT_MIPS3;3115//===----------------------------------------------------------------------===//3116// Arbitrary patterns that map to one or more instructions3117//===----------------------------------------------------------------------===//3118 3119// Load/store pattern templates.3120class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :3121 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;3122 3123class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :3124 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;3125 3126// Materialize constants.3127multiclass MaterializeImms<ValueType VT, Register ZEROReg,3128 Instruction ADDiuOp, Instruction LUiOp,3129 Instruction ORiOp> {3130 3131// Constant synthesis previously relied on the ordering of the patterns below.3132// By making the predicates they use non-overlapping, the patterns were3133// reordered so that the effect of the newly introduced predicates can be3134// observed.3135 3136// Arbitrary immediates3137def : MipsPat<(VT LUiORiPred:$imm),3138 (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;3139 3140// Bits 32-16 set, sign/zero extended.3141def : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>;3142 3143// Small immediates3144def : MipsPat<(VT ORiPred:$imm), (ORiOp ZEROReg, imm:$imm)>;3145def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;3146}3147 3148let AdditionalPredicates = [NotInMicroMips] in3149 defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1;3150 3151// Carry MipsPatterns3152let AdditionalPredicates = [NotInMicroMips] in {3153 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),3154 (SUBu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1;3155}3156def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),3157 (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP;3158def : MipsPat<(addc GPR32:$src, immSExt16:$imm),3159 (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP;3160 3161// Support multiplication for pre-Mips32 targets that don't have3162// the MUL instruction.3163def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),3164 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,3165 ISA_MIPS1_NOT_32R6_64R6;3166 3167// SYNC3168def : MipsPat<(MipsSync (i32 immz)),3169 (SYNC 0)>, ISA_MIPS2;3170 3171// Call3172def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),3173 (JAL texternalsym:$dst)>, ISA_MIPS1;3174//def : MipsPat<(MipsJmpLink GPR32:$dst),3175// (JALR GPR32:$dst)>;3176 3177// Tail call3178let AdditionalPredicates = [NotInMicroMips] in {3179 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),3180 (TAILCALL tglobaladdr:$dst)>, ISA_MIPS1;3181 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),3182 (TAILCALL texternalsym:$dst)>, ISA_MIPS1;3183}3184// hi/lo relocs3185multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,3186 Register ZeroReg, RegisterOperand GPROpnd> {3187 def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>;3188 def : MipsPat<(MipsHi tblockaddress:$in), (Lui tblockaddress:$in)>;3189 def : MipsPat<(MipsHi tjumptable:$in), (Lui tjumptable:$in)>;3190 def : MipsPat<(MipsHi tconstpool:$in), (Lui tconstpool:$in)>;3191 def : MipsPat<(MipsHi texternalsym:$in), (Lui texternalsym:$in)>;3192 3193 def : MipsPat<(MipsLo tglobaladdr:$in),3194 (Addiu ZeroReg, tglobaladdr:$in)>;3195 def : MipsPat<(MipsLo tblockaddress:$in),3196 (Addiu ZeroReg, tblockaddress:$in)>;3197 def : MipsPat<(MipsLo tjumptable:$in),3198 (Addiu ZeroReg, tjumptable:$in)>;3199 def : MipsPat<(MipsLo tconstpool:$in),3200 (Addiu ZeroReg, tconstpool:$in)>;3201 def : MipsPat<(MipsLo tglobaltlsaddr:$in),3202 (Addiu ZeroReg, tglobaltlsaddr:$in)>;3203 def : MipsPat<(MipsLo texternalsym:$in),3204 (Addiu ZeroReg, texternalsym:$in)>;3205 3206 def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaladdr:$lo)),3207 (Addiu GPROpnd:$hi, tglobaladdr:$lo)>;3208 def : MipsPat<(add GPROpnd:$hi, (MipsLo tblockaddress:$lo)),3209 (Addiu GPROpnd:$hi, tblockaddress:$lo)>;3210 def : MipsPat<(add GPROpnd:$hi, (MipsLo tjumptable:$lo)),3211 (Addiu GPROpnd:$hi, tjumptable:$lo)>;3212 def : MipsPat<(add GPROpnd:$hi, (MipsLo tconstpool:$lo)),3213 (Addiu GPROpnd:$hi, tconstpool:$lo)>;3214 def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaltlsaddr:$lo)),3215 (Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>;3216 def : MipsPat<(add GPROpnd:$hi, (MipsLo texternalsym:$lo)),3217 (Addiu GPROpnd:$hi, texternalsym:$lo)>;3218}3219 3220// wrapper_pic3221class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:3222 MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>;3223 3224let AdditionalPredicates = [NotInMicroMips] in {3225 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;3226 3227 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>, ISA_MIPS1;3228 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>,3229 ISA_MIPS1;3230 3231 def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>,3232 ISA_MIPS1;3233 3234 // gp_rel relocs3235 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),3236 (ADDiu GPR32:$gp, tglobaladdr:$in)>, ISA_MIPS1, ABI_NOT_N64;3237 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),3238 (ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64;3239 3240 def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1;3241 def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1;3242 def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1;3243 def : WrapperPat<tblockaddress, ADDiu, GPR32>, ISA_MIPS1;3244 def : WrapperPat<tjumptable, ADDiu, GPR32>, ISA_MIPS1;3245 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>, ISA_MIPS1;3246 3247 // Mips does not have "not", so we expand our way3248 def : MipsPat<(not GPR32:$in),3249 (NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1;3250}3251 3252// extended loads3253let AdditionalPredicates = [NotInMicroMips] in {3254 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>, ISA_MIPS1;3255 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>, ISA_MIPS1;3256 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>, ISA_MIPS1;3257 3258 // peepholes3259 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, ISA_MIPS1;3260}3261 3262// brcond patterns3263multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1,3264 Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp,3265 Instruction SLTiOp, Instruction SLTiuOp,3266 Register ZEROReg> {3267def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),3268 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;3269def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),3270 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;3271 3272def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),3273 (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;3274def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),3275 (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;3276def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),3277 (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;3278def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),3279 (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;3280def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),3281 (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;3282def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),3283 (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;3284 3285def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),3286 (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;3287def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),3288 (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;3289 3290def : MipsPat<(brcond RC:$cond, bb:$dst),3291 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;3292}3293let AdditionalPredicates = [NotInMicroMips] in {3294 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,3295 ISA_MIPS1;3296 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),3297 (BLEZ i32:$lhs, bb:$dst)>, ISA_MIPS1;3298 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),3299 (BGEZ i32:$lhs, bb:$dst)>, ISA_MIPS1;3300}3301 3302// setcc patterns3303multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,3304 Instruction SLTuOp, Register ZEROReg> {3305 def : MipsPat<(seteq RC:$lhs, 0),3306 (SLTiuOp RC:$lhs, 1)>;3307 def : MipsPat<(setne RC:$lhs, 0),3308 (SLTuOp ZEROReg, RC:$lhs)>;3309 def : MipsPat<(seteq RC:$lhs, RC:$rhs),3310 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;3311 def : MipsPat<(setne RC:$lhs, RC:$rhs),3312 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;3313}3314 3315multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,3316 Instruction SLTuOp> {3317 def : MipsPat<(setle RC:$lhs, RC:$rhs),3318 (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;3319 def : MipsPat<(setule RC:$lhs, RC:$rhs),3320 (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;3321}3322 3323multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {3324 def : MipsPat<(setgt RC:$lhs, RC:$rhs),3325 (SLTOp RC:$rhs, RC:$lhs)>;3326 def : MipsPat<(setugt RC:$lhs, RC:$rhs),3327 (SLTuOp RC:$rhs, RC:$lhs)>;3328}3329 3330multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,3331 Instruction SLTuOp> {3332 def : MipsPat<(setge RC:$lhs, RC:$rhs),3333 (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;3334 def : MipsPat<(setuge RC:$lhs, RC:$rhs),3335 (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;3336}3337 3338multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp,3339 Instruction SLTiOp, Instruction SLTiuOp> {3340 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),3341 (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;3342 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),3343 (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;3344}3345 3346let AdditionalPredicates = [NotInMicroMips] in {3347 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1;3348 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;3349 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;3350 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;3351 defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>, ISA_MIPS1;3352 3353 // bswap pattern3354 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2;3355}3356 3357// Load halfword/word patterns.3358let AdditionalPredicates = [NotInMicroMips] in {3359 let AddedComplexity = 40 in {3360 def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1;3361 def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1;3362 def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1;3363 def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1;3364 def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1;3365 }3366 3367 // Atomic load patterns.3368 def : MipsPat<(atomic_load_asext_8 addr:$a), (LB addr:$a)>, ISA_MIPS1;3369 def : MipsPat<(atomic_load_asext_16 addr:$a), (LH addr:$a)>, ISA_MIPS1;3370 def : MipsPat<(atomic_load_nonext_32 addr:$a), (LW addr:$a)>, ISA_MIPS1;3371 3372 // Atomic store patterns.3373 def : MipsPat<(atomic_store_8 GPR32:$v, addr:$a), (SB GPR32:$v, addr:$a)>,3374 ISA_MIPS1;3375 def : MipsPat<(atomic_store_16 GPR32:$v, addr:$a), (SH GPR32:$v, addr:$a)>,3376 ISA_MIPS1;3377 def : MipsPat<(atomic_store_32 GPR32:$v, addr:$a), (SW GPR32:$v, addr:$a)>,3378 ISA_MIPS1;3379}3380 3381//===----------------------------------------------------------------------===//3382// Floating Point Support3383//===----------------------------------------------------------------------===//3384 3385include "MipsInstrFPU.td"3386include "Mips64InstrInfo.td"3387include "MipsCondMov.td"3388 3389include "Mips32r6InstrInfo.td"3390include "Mips64r6InstrInfo.td"3391 3392//3393// Mips163394 3395include "Mips16InstrFormats.td"3396include "Mips16InstrInfo.td"3397 3398// DSP3399include "MipsDSPInstrFormats.td"3400include "MipsDSPInstrInfo.td"3401 3402// MSA3403include "MipsMSAInstrFormats.td"3404include "MipsMSAInstrInfo.td"3405 3406// EVA3407include "MipsEVAInstrFormats.td"3408include "MipsEVAInstrInfo.td"3409 3410// MT3411include "MipsMTInstrFormats.td"3412include "MipsMTInstrInfo.td"3413 3414// Micromips3415include "MicroMipsInstrFormats.td"3416include "MicroMipsInstrInfo.td"3417include "MicroMipsInstrFPU.td"3418 3419// Micromips r63420include "MicroMips32r6InstrFormats.td"3421include "MicroMips32r6InstrInfo.td"3422 3423// Micromips DSP3424include "MicroMipsDSPInstrFormats.td"3425include "MicroMipsDSPInstrInfo.td"3426