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1//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,10 ASE_MSA {11 let EncodingPredicates = [HasStdEnc];12 let Inst{31-26} = 0b011110;13}14 15class MSACBranch : MSAInst {16 let Inst{31-26} = 0b010001;17}18 19class MSASpecial : MSAInst {20 let Inst{31-26} = 0b000000;21}22 23class MSAPseudo<dag outs, dag ins, list<dag> pattern,24 InstrItinClass itin = IIPseudo>:25 MipsPseudo<outs, ins, pattern, itin> {26 let EncodingPredicates = [HasStdEnc];27 let ASEPredicate = [HasMSA];28}29 30class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {31 bits<5> ws;32 bits<5> wd;33 bits<3> m;34 35 let Inst{25-23} = major;36 let Inst{22-19} = 0b1110;37 let Inst{18-16} = m;38 let Inst{15-11} = ws;39 let Inst{10-6} = wd;40 let Inst{5-0} = minor;41}42 43class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {44 bits<5> ws;45 bits<5> wd;46 bits<4> m;47 48 let Inst{25-23} = major;49 let Inst{22-20} = 0b110;50 let Inst{19-16} = m;51 let Inst{15-11} = ws;52 let Inst{10-6} = wd;53 let Inst{5-0} = minor;54}55 56class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {57 bits<5> ws;58 bits<5> wd;59 bits<5> m;60 61 let Inst{25-23} = major;62 let Inst{22-21} = 0b10;63 let Inst{20-16} = m;64 let Inst{15-11} = ws;65 let Inst{10-6} = wd;66 let Inst{5-0} = minor;67}68 69class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {70 bits<5> ws;71 bits<5> wd;72 bits<6> m;73 74 let Inst{25-23} = major;75 let Inst{22} = 0b0;76 let Inst{21-16} = m;77 let Inst{15-11} = ws;78 let Inst{10-6} = wd;79 let Inst{5-0} = minor;80}81 82class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {83 bits<5> rs;84 bits<5> wd;85 86 let Inst{25-18} = major;87 let Inst{17-16} = df;88 let Inst{15-11} = rs;89 let Inst{10-6} = wd;90 let Inst{5-0} = minor;91}92 93class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {94 bits<5> rs;95 bits<5> wd;96 97 let Inst{25-18} = major;98 let Inst{17-16} = df;99 let Inst{15-11} = rs;100 let Inst{10-6} = wd;101 let Inst{5-0} = minor;102}103 104class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {105 bits<5> ws;106 bits<5> wd;107 108 let Inst{25-18} = major;109 let Inst{17-16} = df;110 let Inst{15-11} = ws;111 let Inst{10-6} = wd;112 let Inst{5-0} = minor;113}114 115class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {116 bits<5> ws;117 bits<5> wd;118 119 let Inst{25-17} = major;120 let Inst{16} = df;121 let Inst{15-11} = ws;122 let Inst{10-6} = wd;123 let Inst{5-0} = minor;124}125 126class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {127 bits<5> wt;128 bits<5> ws;129 bits<5> wd;130 131 let Inst{25-23} = major;132 let Inst{22-21} = df;133 let Inst{20-16} = wt;134 let Inst{15-11} = ws;135 let Inst{10-6} = wd;136 let Inst{5-0} = minor;137}138 139class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {140 bits<5> wt;141 bits<5> ws;142 bits<5> wd;143 144 let Inst{25-22} = major;145 let Inst{21} = df;146 let Inst{20-16} = wt;147 let Inst{15-11} = ws;148 let Inst{10-6} = wd;149 let Inst{5-0} = minor;150}151 152class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {153 bits<5> rt;154 bits<5> ws;155 bits<5> wd;156 157 let Inst{25-23} = major;158 let Inst{22-21} = df;159 let Inst{20-16} = rt;160 let Inst{15-11} = ws;161 let Inst{10-6} = wd;162 let Inst{5-0} = minor;163}164 165class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {166 bits<5> ws;167 bits<5> wd;168 169 let Inst{25-16} = major;170 let Inst{15-11} = ws;171 let Inst{10-6} = wd;172 let Inst{5-0} = minor;173}174 175class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {176 bits<5> rd;177 bits<5> cs;178 179 let Inst{25-16} = major;180 let Inst{15-11} = cs;181 let Inst{10-6} = rd;182 let Inst{5-0} = minor;183}184 185class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {186 bits<5> rs;187 bits<5> cd;188 189 let Inst{25-16} = major;190 let Inst{15-11} = rs;191 let Inst{10-6} = cd;192 let Inst{5-0} = minor;193}194 195class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {196 bits<4> n;197 bits<5> ws;198 bits<5> wd;199 200 let Inst{25-22} = major;201 let Inst{21-20} = 0b00;202 let Inst{19-16} = n{3-0};203 let Inst{15-11} = ws;204 let Inst{10-6} = wd;205 let Inst{5-0} = minor;206}207 208class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {209 bits<4> n;210 bits<5> ws;211 bits<5> wd;212 213 let Inst{25-22} = major;214 let Inst{21-19} = 0b100;215 let Inst{18-16} = n{2-0};216 let Inst{15-11} = ws;217 let Inst{10-6} = wd;218 let Inst{5-0} = minor;219}220 221class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {222 bits<4> n;223 bits<5> ws;224 bits<5> wd;225 226 let Inst{25-22} = major;227 let Inst{21-18} = 0b1100;228 let Inst{17-16} = n{1-0};229 let Inst{15-11} = ws;230 let Inst{10-6} = wd;231 let Inst{5-0} = minor;232}233 234class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {235 bits<4> n;236 bits<5> ws;237 bits<5> wd;238 239 let Inst{25-22} = major;240 let Inst{21-17} = 0b11100;241 let Inst{16} = n{0};242 let Inst{15-11} = ws;243 let Inst{10-6} = wd;244 let Inst{5-0} = minor;245}246 247class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {248 bits<4> n;249 bits<5> ws;250 bits<5> rd;251 252 let Inst{25-22} = major;253 let Inst{21-20} = 0b00;254 let Inst{19-16} = n{3-0};255 let Inst{15-11} = ws;256 let Inst{10-6} = rd;257 let Inst{5-0} = minor;258}259 260class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {261 bits<4> n;262 bits<5> ws;263 bits<5> rd;264 265 let Inst{25-22} = major;266 let Inst{21-19} = 0b100;267 let Inst{18-16} = n{2-0};268 let Inst{15-11} = ws;269 let Inst{10-6} = rd;270 let Inst{5-0} = minor;271}272 273class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {274 bits<4> n;275 bits<5> ws;276 bits<5> rd;277 278 let Inst{25-22} = major;279 let Inst{21-18} = 0b1100;280 let Inst{17-16} = n{1-0};281 let Inst{15-11} = ws;282 let Inst{10-6} = rd;283 let Inst{5-0} = minor;284}285 286class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst {287 bits<4> n;288 bits<5> ws;289 bits<5> rd;290 291 let Inst{25-22} = major;292 let Inst{21-17} = 0b11100;293 let Inst{16} = n{0};294 let Inst{15-11} = ws;295 let Inst{10-6} = rd;296 let Inst{5-0} = minor;297}298 299class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {300 bits<6> n;301 bits<5> rs;302 bits<5> wd;303 304 let Inst{25-22} = major;305 let Inst{21-20} = 0b00;306 let Inst{19-16} = n{3-0};307 let Inst{15-11} = rs;308 let Inst{10-6} = wd;309 let Inst{5-0} = minor;310}311 312class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {313 bits<6> n;314 bits<5> rs;315 bits<5> wd;316 317 let Inst{25-22} = major;318 let Inst{21-19} = 0b100;319 let Inst{18-16} = n{2-0};320 let Inst{15-11} = rs;321 let Inst{10-6} = wd;322 let Inst{5-0} = minor;323}324 325class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {326 bits<6> n;327 bits<5> rs;328 bits<5> wd;329 330 let Inst{25-22} = major;331 let Inst{21-18} = 0b1100;332 let Inst{17-16} = n{1-0};333 let Inst{15-11} = rs;334 let Inst{10-6} = wd;335 let Inst{5-0} = minor;336}337 338class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst {339 bits<6> n;340 bits<5> rs;341 bits<5> wd;342 343 let Inst{25-22} = major;344 let Inst{21-17} = 0b11100;345 let Inst{16} = n{0};346 let Inst{15-11} = rs;347 let Inst{10-6} = wd;348 let Inst{5-0} = minor;349}350 351class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {352 bits<5> imm;353 bits<5> ws;354 bits<5> wd;355 356 let Inst{25-23} = major;357 let Inst{22-21} = df;358 let Inst{20-16} = imm;359 let Inst{15-11} = ws;360 let Inst{10-6} = wd;361 let Inst{5-0} = minor;362}363 364class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {365 bits<8> u8;366 bits<5> ws;367 bits<5> wd;368 369 let Inst{25-24} = major;370 let Inst{23-16} = u8;371 let Inst{15-11} = ws;372 let Inst{10-6} = wd;373 let Inst{5-0} = minor;374}375 376class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {377 bits<10> s10;378 bits<5> wd;379 380 let Inst{25-23} = major;381 let Inst{22-21} = df;382 let Inst{20-11} = s10;383 let Inst{10-6} = wd;384 let Inst{5-0} = minor;385}386 387class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {388 bits<21> addr;389 bits<5> wd;390 391 let Inst{25-16} = addr{9-0};392 let Inst{15-11} = addr{20-16};393 let Inst{10-6} = wd;394 let Inst{5-2} = minor;395 let Inst{1-0} = df;396}397 398class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {399 bits<5> wt;400 bits<5> ws;401 bits<5> wd;402 403 let Inst{25-21} = major;404 let Inst{20-16} = wt;405 let Inst{15-11} = ws;406 let Inst{10-6} = wd;407 let Inst{5-0} = minor;408}409 410class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {411 bits<16> offset;412 bits<5> wt;413 414 let Inst{25-23} = major;415 let Inst{22-21} = df;416 let Inst{20-16} = wt;417 let Inst{15-0} = offset;418}419 420class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {421 bits<16> offset;422 bits<5> wt;423 424 let Inst{25-21} = major;425 let Inst{20-16} = wt;426 let Inst{15-0} = offset;427}428 429class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {430 bits<5> rs;431 bits<5> rt;432 bits<5> rd;433 bits<2> sa;434 435 let Inst{25-21} = rs;436 let Inst{20-16} = rt;437 let Inst{15-11} = rd;438 let Inst{10-8} = 0b000;439 let Inst{7-6} = sa;440 let Inst{5-0} = minor;441}442 443class SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial {444 bits<5> rs;445 bits<5> rt;446 bits<5> rd;447 bits<2> sa;448 449 let Inst{25-21} = rs;450 let Inst{20-16} = rt;451 let Inst{15-11} = rd;452 let Inst{10-8} = 0b000;453 let Inst{7-6} = sa;454 let Inst{5-0} = minor;455}456