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1//===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the MIPS MT ASE as defined by MD00378 1.12.10//11// TODO: Add support for the microMIPS encodings for the MT ASE and add the12// instruction mappings.13//14//===----------------------------------------------------------------------===//15 16//===----------------------------------------------------------------------===//17// MIPS MT Instruction Encodings18//===----------------------------------------------------------------------===//19 20class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,21 OPCODE_SC_D>;22 23class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,24 OPCODE_SC_E>;25 26class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,27 OPCODE_SC_D>;28 29class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,30 OPCODE_SC_E>;31 32class FORK_ENC : SPECIAL3_MT_FORK;33 34class YIELD_ENC : SPECIAL3_MT_YIELD;35 36class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>;37 38class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;39 40//===----------------------------------------------------------------------===//41// MIPS MT Instruction Descriptions42//===----------------------------------------------------------------------===//43 44class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {45 dag OutOperandList = (outs GPR32Opnd:$rt);46 dag InOperandList = (ins);47 string AsmString = !strconcat(instr_asm, "\t$rt");48 list<dag> Pattern = [];49 InstrItinClass Itinerary = Itin;50}51 52class MFTR_DESC {53 dag OutOperandList = (outs GPR32Opnd:$rd);54 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);55 string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";56 list<dag> Pattern = [];57 InstrItinClass Itinerary = II_MFTR;58}59 60class MTTR_DESC {61 dag OutOperandList = (outs GPR32Opnd:$rd);62 dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);63 string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";64 list<dag> Pattern = [];65 InstrItinClass Itinerary = II_MTTR;66}67 68class FORK_DESC {69 dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);70 dag InOperandList = (ins GPR32Opnd:$rt);71 string AsmString = "fork\t$rd, $rs, $rt";72 list<dag> Pattern = [];73 InstrItinClass Itinerary = II_FORK;74}75 76class YIELD_DESC {77 dag OutOperandList = (outs GPR32Opnd:$rd);78 dag InOperandList = (ins GPR32Opnd:$rs);79 string AsmString = "yield\t$rd, $rs";80 list<dag> Pattern = [];81 InstrItinClass Itinerary = II_YIELD;82}83 84class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;85 86class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;87 88class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;89 90class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;91 92//===----------------------------------------------------------------------===//93// MIPS MT Instruction Definitions94//===----------------------------------------------------------------------===//95let hasSideEffects = 1, isNotDuplicable = 1,96 AdditionalPredicates = [NotInMicroMips] in {97 def DMT : DMT_ENC, DMT_DESC, ASE_MT;98 99 def EMT : EMT_ENC, EMT_DESC, ASE_MT;100 101 def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;102 103 def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;104 105 def FORK : FORK_ENC, FORK_DESC, ASE_MT;106 107 def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;108 109 def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;110 111 def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;112}113 114//===----------------------------------------------------------------------===//115// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.116//===----------------------------------------------------------------------===//117def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,118 uimm3:$sel),119 "mftc0 $rd, $rt, $sel">, ASE_MT;120 121def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,122 uimm3:$sel),123 "mftgpr $rd, $rt">, ASE_MT;124 125def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),126 "mftlo $rt, $ac">, ASE_MT;127 128def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),129 "mfthi $rt, $ac">, ASE_MT;130 131def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),132 "mftacx $rt, $ac">, ASE_MT;133 134def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),135 "mftdsp $rt">, ASE_MT;136 137def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),138 "mftc1 $rt, $ft">, ASE_MT;139 140def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),141 "mfthc1 $rt, $ft">, ASE_MT;142 143def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),144 "cftc1 $rt, $ft">, ASE_MT;145 146 147def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,148 uimm3:$sel),149 "mttc0 $rt, $rd, $sel">, ASE_MT;150 151def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),152 "mttgpr $rd, $rt">, ASE_MT;153 154def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),155 "mttlo $rt, $ac">, ASE_MT;156 157def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),158 "mtthi $rt, $ac">, ASE_MT;159 160def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),161 "mttacx $rt, $ac">, ASE_MT;162 163def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),164 "mttdsp $rt">, ASE_MT;165 166def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),167 "mttc1 $rt, $ft">, ASE_MT;168 169def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),170 "mtthc1 $rt, $ft">, ASE_MT;171 172def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),173 "cttc1 $rt, $ft">, ASE_MT;174 175//===----------------------------------------------------------------------===//176// MIPS MT Instruction Definitions177//===----------------------------------------------------------------------===//178 179let AdditionalPredicates = [NotInMicroMips] in {180 def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;181 182 def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;183 184 def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;185 186 def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;187 188 def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;189 190 def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),191 1>, ASE_MT;192 193 def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;194 195 def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;196 197 def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;198 199 def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),200 1>, ASE_MT;201 202 def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;203 204 def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;205 206 def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;207}208