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1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Declarations that describe the MIPS register file11//===----------------------------------------------------------------------===//12let Namespace = "Mips" in {13def sub_32 : SubRegIndex<32>;14def sub_64 : SubRegIndex<64>;15def sub_lo : SubRegIndex<32>;16def sub_hi : SubRegIndex<32, 32>;17def sub_dsp16_19 : SubRegIndex<4, 16>;18def sub_dsp20 : SubRegIndex<1, 20>;19def sub_dsp21 : SubRegIndex<1, 21>;20def sub_dsp22 : SubRegIndex<1, 22>;21def sub_dsp23 : SubRegIndex<1, 23>;22}23 24class Unallocatable {25 bit isAllocatable = 0;26}27 28// We have banks of 32 registers each.29class MipsReg<bits<16> Enc, string n> : Register<n> {30 let HWEncoding = Enc;31 let Namespace = "Mips";32}33 34class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>35 : RegisterWithSubRegs<n, subregs> {36 let HWEncoding = Enc;37 let Namespace = "Mips";38}39 40// Mips CPU Registers.41class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;42 43// Mips 64-bit CPU Registers44class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>45 : MipsRegWithSubRegs<Enc, n, subregs> {46 let SubRegIndices = [sub_32];47}48 49// Mips 32-bit FPU Registers50class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;51 52// Mips 64-bit (aliased) FPU Registers53class AFPR<bits<16> Enc, string n, list<Register> subregs>54 : MipsRegWithSubRegs<Enc, n, subregs> {55 let SubRegIndices = [sub_lo, sub_hi];56 let CoveredBySubRegs = 1;57}58 59class AFPR64<bits<16> Enc, string n, list<Register> subregs>60 : MipsRegWithSubRegs<Enc, n, subregs> {61 let SubRegIndices = [sub_lo, sub_hi];62 let CoveredBySubRegs = 1;63}64 65// Mips 128-bit (aliased) MSA Registers66class AFPR128<bits<16> Enc, string n, list<Register> subregs>67 : MipsRegWithSubRegs<Enc, n, subregs> {68 let SubRegIndices = [sub_64];69}70 71// Accumulator Registers72class ACCReg<bits<16> Enc, string n, list<Register> subregs>73 : MipsRegWithSubRegs<Enc, n, subregs> {74 let SubRegIndices = [sub_lo, sub_hi];75 let CoveredBySubRegs = 1;76}77 78// Mips Hardware Registers79class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;80 81//===----------------------------------------------------------------------===//82// Registers83//===----------------------------------------------------------------------===//84 85let Namespace = "Mips" in {86 // General Purpose Registers87 let isConstant = true in88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;120 121 // General Purpose 64-bit Registers122 let isConstant = true in123 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;124 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;125 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;126 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;127 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;128 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;129 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;130 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;131 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;132 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;133 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;134 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;135 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;136 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;137 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;138 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;139 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;140 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;141 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;142 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;143 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;144 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;145 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;146 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;147 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;148 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;149 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;150 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;151 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;152 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;153 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;154 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;155 156 /// Mips Single point precision FPU Registers157 foreach I = 0-31 in158 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;159 160 // Higher half of 64-bit FP registers.161 foreach I = 0-31 in162 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;163 164 /// Mips Double point precision FPU Registers (aliased165 /// with the single precision to hold 64 bit values)166 foreach I = 0-15 in167 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),168 [!cast<FPR>("F"#!shl(I, 1)),169 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;170 171 /// Mips Double point precision FPU Registers in MFP64 mode.172 foreach I = 0-31 in173 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,174 DwarfRegNum<[!add(I, 32)]>;175 176 /// Mips MSA registers177 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers178 foreach I = 0-31 in179 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,180 DwarfRegNum<[!add(I, 32)]>;181 182 // Hi/Lo registers183 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;184 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;185 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;186 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;187 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;188 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;189 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;190 def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>;191 192 let SubRegIndices = [sub_32] in {193 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;194 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;195 }196 197 // FP control registers.198 foreach I = 0-31 in199 def FCR#I : MipsReg<I, ""#I>;200 201 // FP condition code registers.202 foreach I = 0-7 in203 def FCC#I : MipsReg<I, "fcc"#I>;204 205 // COP0 registers.206 foreach I = 0-31 in207 def COP0#I : MipsReg<I, ""#I>;208 209 // COP2 registers.210 foreach I = 0-31 in211 def COP2#I : MipsReg<I, ""#I>;212 213 // COP3 registers.214 foreach I = 0-31 in215 def COP3#I : MipsReg<I, ""#I>;216 217 // PC register218 def PC : Register<"pc">;219 220 // Hardware registers221 def HWR0 : MipsReg<0, "hwr_cpunum">;222 def HWR1 : MipsReg<1, "hwr_synci_step">;223 def HWR2 : MipsReg<2, "hwr_cc">;224 def HWR3 : MipsReg<3, "hwr_ccres">;225 226 foreach I = 4-31 in227 def HWR#I : MipsReg<I, ""#I>;228 229 // Accum registers230 foreach I = 0-3 in231 def AC#I : ACCReg<I, "ac"#I,232 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;233 234 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;235 236 // DSP-ASE control register fields.237 def DSPPos : Register<"">;238 def DSPSCount : Register<"">;239 def DSPCarry : Register<"">;240 def DSPEFI : Register<"">;241 def DSPOutFlag16_19 : Register<"">;242 def DSPOutFlag20 : Register<"">;243 def DSPOutFlag21 : Register<"">;244 def DSPOutFlag22 : Register<"">;245 def DSPOutFlag23 : Register<"">;246 def DSPCCond : Register<"">;247 248 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,249 sub_dsp23] in250 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,251 DSPOutFlag21, DSPOutFlag22,252 DSPOutFlag23]>;253 254 // MSA-ASE control registers.255 def MSAIR : MipsReg<0, "0">;256 def MSACSR : MipsReg<1, "1">;257 def MSAAccess : MipsReg<2, "2">;258 def MSASave : MipsReg<3, "3">;259 def MSAModify : MipsReg<4, "4">;260 def MSARequest : MipsReg<5, "5">;261 def MSAMap : MipsReg<6, "6">;262 def MSAUnmap : MipsReg<7, "7">;263 // MSA-ASE fake control registers.264 // These registers do not exist, but instructions like `cfcmsa`265 // and `ctcmsa` allows to specify them.266 foreach I = 8-31 in267 def MSA#I : MipsReg<I, ""#I>;268 269 // Octeon multiplier and product registers270 def MPL0 : MipsReg<0, "mpl0">;271 def MPL1 : MipsReg<1, "mpl1">;272 def MPL2 : MipsReg<2, "mpl2">;273 def P0 : MipsReg<0, "p0">;274 def P1 : MipsReg<1, "p1">;275 def P2 : MipsReg<2, "p2">;276 277}278 279//===----------------------------------------------------------------------===//280// Register Classes281//===----------------------------------------------------------------------===//282 283class GPR32Class<list<ValueType> regTypes> :284 RegisterClass<"Mips", regTypes, 32, (add285 // Reserved286 ZERO, AT,287 // Return Values and Arguments288 V0, V1, A0, A1, A2, A3,289 // Not preserved across procedure calls290 T0, T1, T2, T3, T4, T5, T6, T7,291 // Callee save292 S0, S1, S2, S3, S4, S5, S6, S7,293 // Not preserved across procedure calls294 T8, T9,295 // Reserved296 K0, K1, GP, SP, FP, RA)>;297 298def GPR32 : GPR32Class<[i32]>;299 300def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add301 // Reserved302 ZERO)>;303 304def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add305 // Reserved306 AT,307 // Return Values and Arguments308 V0, V1, A0, A1, A2, A3,309 // Not preserved across procedure calls310 T0, T1, T2, T3, T4, T5, T6, T7,311 // Callee save312 S0, S1, S2, S3, S4, S5, S6, S7,313 // Not preserved across procedure calls314 T8, T9,315 // Reserved316 K0, K1, GP, SP, FP, RA)>;317 318def DSPR : GPR32Class<[v4i8, v2i16]>;319 320def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add321 // Callee save322 S0, S1,323 // Return Values and Arguments324 V0, V1, A0, A1, A2, A3)>;325 326def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add327 // Reserved328 ZERO,329 // Callee save330 S1,331 // Return Values and Arguments332 V0, V1, A0, A1, A2, A3)>;333 334def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add335 // Reserved336 ZERO,337 // Callee save338 S1,339 // Return Values and Arguments340 V0, V1,341 // Callee save342 S0, S2, S3, S4)>;343 344def GPRMM16MovePPairFirst : RegisterClass<"Mips", [i32], 32, (add345 // Arguments346 A0, A1, A2)>;347 348def GPRMM16MovePPairSecond : RegisterClass<"Mips", [i32], 32, (add349 // Arguments350 A1, A2, A3,351 // Callee save352 S5, S6)>;353 354def GPR64 : RegisterClass<"Mips", [i64], 64, (add355 // Reserved356 ZERO_64, AT_64,357 // Return Values and Arguments358 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,359 // Not preserved across procedure calls360 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,361 // Callee save362 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,363 // Not preserved across procedure calls364 T8_64, T9_64,365 // Reserved366 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;367 368def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add369 // Return Values and Arguments370 V0, V1, A0, A1, A2, A3,371 // Callee save372 S0, S1)>;373 374def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add375 // Return Values and Arguments376 V0, V1, A0, A1, A2, A3,377 // Callee save378 S0, S1,379 SP)>;380 381def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;382 383def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;384 385// 64bit fp:386// * FGR64 - 32 64-bit registers387// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)388//389// 32bit fp:390// * FGR32 - 16 32-bit even registers391// * FGR32 - 32 32-bit registers (single float only mode)392def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> {393 // Do not allocate odd registers when given -mattr=+nooddspreg.394 let AltOrders = [(decimate FGR32, 2)];395 let AltOrderSelect = [{396 const auto & S = MF.getSubtarget<MipsSubtarget>();397 return S.isABI_O32() && !S.useOddSPReg();398 }];399}400 401def AFGR64 : RegisterClass<"Mips", [f64], 64, (add402 // Return Values and Arguments403 D0, D1,404 // Not preserved across procedure calls405 D2, D3, D4, D5,406 // Return Values and Arguments407 D6, D7,408 // Not preserved across procedure calls409 D8, D9,410 // Callee save411 D10, D11, D12, D13, D14, D15)>;412 413def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {414 // Do not allocate odd registers when given -mattr=+nooddspreg.415 let AltOrders = [(decimate FGR64, 2)];416 let AltOrderSelect = [{417 const auto & S = MF.getSubtarget<MipsSubtarget>();418 return S.isABI_O32() && !S.useOddSPReg();419 }];420}421 422// FP control registers.423def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,424 Unallocatable;425 426// FP condition code registers.427def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,428 Unallocatable;429 430// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.431// This class allows us to represent this in codegen patterns.432def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;433 434def MSA128F16 : RegisterClass<"Mips", [f16], 128, (sequence "W%u", 0, 31)>;435 436def MSA128B: RegisterClass<"Mips", [v16i8], 128,437 (sequence "W%u", 0, 31)>;438def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,439 (sequence "W%u", 0, 31)>;440def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,441 (sequence "W%u", 0, 31)>;442def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,443 (sequence "W%u", 0, 31)>;444def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,445 (decimate (sequence "W%u", 0, 31), 2)>;446 447def MSACtrl: RegisterClass<"Mips", [i32], 32, (add448 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap,449 (sequence "MSA%u", 8, 31))>, Unallocatable;450 451// Hi/Lo Registers452def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;453def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;454def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;455def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;456def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;457def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;458 459// Hardware registers460def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,461 Unallocatable;462 463// Accumulator Registers464def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {465 let Size = 64;466}467 468def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {469 let Size = 128;470}471 472def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {473 let Size = 64;474}475 476def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;477 478// Coprocessor 0 registers.479def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,480 Unallocatable;481 482// Coprocessor 2 registers.483def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,484 Unallocatable;485 486// Coprocessor 3 registers.487def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,488 Unallocatable;489 490// Stack pointer and global pointer classes for instructions that are limited491// to a single register such as lwgp/lwsp in microMIPS.492def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;493def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;494def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable;495def GP64 : RegisterClass<"Mips", [i64], 64, (add GP_64)>, Unallocatable;496 497// Octeon multiplier and product registers498def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,499 Unallocatable;500def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,501 Unallocatable;502 503// Register Operands.504 505class MipsAsmRegOperand : AsmOperandClass {506 let ParserMethod = "parseAnyRegister";507}508 509def GPR64AsmOperand : MipsAsmRegOperand {510 let Name = "GPR64AsmReg";511 let PredicateMethod = "isGPRAsmReg";512}513 514def GPR32ZeroAsmOperand : MipsAsmRegOperand {515 let Name = "GPR32ZeroAsmReg";516 let PredicateMethod = "isGPRZeroAsmReg";517}518 519def GPR32NonZeroAsmOperand : MipsAsmRegOperand {520 let Name = "GPR32NonZeroAsmReg";521 let PredicateMethod = "isGPRNonZeroAsmReg";522}523 524def GPR32AsmOperand : MipsAsmRegOperand {525 let Name = "GPR32AsmReg";526 let PredicateMethod = "isGPRAsmReg";527}528 529def GPRMM16AsmOperand : MipsAsmRegOperand {530 let Name = "GPRMM16AsmReg";531 let PredicateMethod = "isMM16AsmReg";532}533 534def GPRMM16AsmOperandZero : MipsAsmRegOperand {535 let Name = "GPRMM16AsmRegZero";536 let PredicateMethod = "isMM16AsmRegZero";537}538 539def GPRMM16AsmOperandMoveP : MipsAsmRegOperand {540 let Name = "GPRMM16AsmRegMoveP";541 let PredicateMethod = "isMM16AsmRegMoveP";542}543 544def GPRMM16AsmOperandMovePPairFirst : MipsAsmRegOperand {545 let Name = "GPRMM16AsmRegMovePPairFirst";546 let PredicateMethod = "isMM16AsmRegMovePPairFirst";547}548 549def GPRMM16AsmOperandMovePPairSecond : MipsAsmRegOperand {550 let Name = "GPRMM16AsmRegMovePPairSecond";551 let PredicateMethod = "isMM16AsmRegMovePPairSecond";552}553 554def ACC64DSPAsmOperand : MipsAsmRegOperand {555 let Name = "ACC64DSPAsmReg";556 let PredicateMethod = "isACCAsmReg";557}558 559def HI32DSPAsmOperand : MipsAsmRegOperand {560 let Name = "HI32DSPAsmReg";561 let PredicateMethod = "isACCAsmReg";562}563 564def LO32DSPAsmOperand : MipsAsmRegOperand {565 let Name = "LO32DSPAsmReg";566 let PredicateMethod = "isACCAsmReg";567}568 569def CCRAsmOperand : MipsAsmRegOperand {570 let Name = "CCRAsmReg";571}572 573def AFGR64AsmOperand : MipsAsmRegOperand {574 let Name = "AFGR64AsmReg";575 let PredicateMethod = "isFGRAsmReg";576}577 578def StrictlyAFGR64AsmOperand : MipsAsmRegOperand {579 let Name = "StrictlyAFGR64AsmReg";580 let PredicateMethod = "isStrictlyFGRAsmReg";581}582 583def FGR64AsmOperand : MipsAsmRegOperand {584 let Name = "FGR64AsmReg";585 let PredicateMethod = "isFGRAsmReg";586}587 588def StrictlyFGR64AsmOperand : MipsAsmRegOperand {589 let Name = "StrictlyFGR64AsmReg";590 let PredicateMethod = "isStrictlyFGRAsmReg";591}592 593def FGR32AsmOperand : MipsAsmRegOperand {594 let Name = "FGR32AsmReg";595 let PredicateMethod = "isFGRAsmReg";596}597 598def StrictlyFGR32AsmOperand : MipsAsmRegOperand {599 let Name = "StrictlyFGR32AsmReg";600 let PredicateMethod = "isStrictlyFGRAsmReg";601}602 603def FCCRegsAsmOperand : MipsAsmRegOperand {604 let Name = "FCCAsmReg";605}606 607def MSA128AsmOperand : MipsAsmRegOperand {608 let Name = "MSA128AsmReg";609}610 611def MSACtrlAsmOperand : MipsAsmRegOperand {612 let Name = "MSACtrlAsmReg";613}614 615def GPR32ZeroOpnd : RegisterOperand<GPR32ZERO> {616 let ParserMatchClass = GPR32ZeroAsmOperand;617}618 619def GPR32NonZeroOpnd : RegisterOperand<GPR32NONZERO> {620 let ParserMatchClass = GPR32NonZeroAsmOperand;621}622 623def GPR32Opnd : RegisterOperand<GPR32> {624 let ParserMatchClass = GPR32AsmOperand;625}626 627def GPRMM16Opnd : RegisterOperand<GPRMM16> {628 let ParserMatchClass = GPRMM16AsmOperand;629}630 631def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {632 let ParserMatchClass = GPRMM16AsmOperandZero;633}634 635def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {636 let ParserMatchClass = GPRMM16AsmOperandMoveP;637 let EncoderMethod = "getMovePRegSingleOpValue";638}639 640def GPRMM16OpndMovePPairFirst : RegisterOperand<GPRMM16MovePPairFirst> {641 let ParserMatchClass = GPRMM16AsmOperandMovePPairFirst;642}643 644def GPRMM16OpndMovePPairSecond : RegisterOperand<GPRMM16MovePPairSecond> {645 let ParserMatchClass = GPRMM16AsmOperandMovePPairSecond;646}647 648def GPR64Opnd : RegisterOperand<GPR64> {649 let ParserMatchClass = GPR64AsmOperand;650}651 652def DSPROpnd : RegisterOperand<DSPR> {653 let ParserMatchClass = GPR32AsmOperand;654}655 656def CCROpnd : RegisterOperand<CCR> {657 let ParserMatchClass = CCRAsmOperand;658}659 660def HWRegsAsmOperand : MipsAsmRegOperand {661 let Name = "HWRegsAsmReg";662}663 664def COP0AsmOperand : MipsAsmRegOperand {665 let Name = "COP0AsmReg";666}667 668def COP2AsmOperand : MipsAsmRegOperand {669 let Name = "COP2AsmReg";670}671 672def COP3AsmOperand : MipsAsmRegOperand {673 let Name = "COP3AsmReg";674}675 676def HWRegsOpnd : RegisterOperand<HWRegs> {677 let ParserMatchClass = HWRegsAsmOperand;678}679 680def AFGR64Opnd : RegisterOperand<AFGR64> {681 let ParserMatchClass = AFGR64AsmOperand;682}683 684def StrictlyAFGR64Opnd : RegisterOperand<AFGR64> {685 let ParserMatchClass = StrictlyAFGR64AsmOperand;686}687 688def FGR64Opnd : RegisterOperand<FGR64> {689 let ParserMatchClass = FGR64AsmOperand;690}691 692def StrictlyFGR64Opnd : RegisterOperand<FGR64> {693 let ParserMatchClass = StrictlyFGR64AsmOperand;694}695 696def FGR32Opnd : RegisterOperand<FGR32> {697 let ParserMatchClass = FGR32AsmOperand;698}699 700def StrictlyFGR32Opnd : RegisterOperand<FGR32> {701 let ParserMatchClass = StrictlyFGR32AsmOperand;702}703 704def FGRCCOpnd : RegisterOperand<FGRCC> {705 // The assembler doesn't use register classes so we can re-use706 // FGR32AsmOperand.707 let ParserMatchClass = FGR32AsmOperand;708}709 710def FCCRegsOpnd : RegisterOperand<FCC> {711 let ParserMatchClass = FCCRegsAsmOperand;712}713 714def LO32DSPOpnd : RegisterOperand<LO32DSP> {715 let ParserMatchClass = LO32DSPAsmOperand;716}717 718def HI32DSPOpnd : RegisterOperand<HI32DSP> {719 let ParserMatchClass = HI32DSPAsmOperand;720}721 722def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {723 let ParserMatchClass = ACC64DSPAsmOperand;724}725 726def COP0Opnd : RegisterOperand<COP0> {727 let ParserMatchClass = COP0AsmOperand;728}729 730def COP2Opnd : RegisterOperand<COP2> {731 let ParserMatchClass = COP2AsmOperand;732}733 734def COP3Opnd : RegisterOperand<COP3> {735 let ParserMatchClass = COP3AsmOperand;736}737 738def MSA128F16Opnd : RegisterOperand<MSA128F16> {739 let ParserMatchClass = MSA128AsmOperand;740}741 742def MSA128BOpnd : RegisterOperand<MSA128B> {743 let ParserMatchClass = MSA128AsmOperand;744}745 746def MSA128HOpnd : RegisterOperand<MSA128H> {747 let ParserMatchClass = MSA128AsmOperand;748}749 750def MSA128WOpnd : RegisterOperand<MSA128W> {751 let ParserMatchClass = MSA128AsmOperand;752}753 754def MSA128DOpnd : RegisterOperand<MSA128D> {755 let ParserMatchClass = MSA128AsmOperand;756}757 758def MSA128CROpnd : RegisterOperand<MSACtrl> {759 let ParserMatchClass = MSACtrlAsmOperand;760}761 762def mips_ptr_rc : RegClassByHwMode<763 [MIPS32, MIPS64],764 [GPR32, GPR64]>;765 766def ptr_gpr16mm_rc : RegClassByHwMode<767 [MIPS32, MIPS64],768 [GPRMM16, GPRMM16]>; // FIXME: Why even use this if it's just a constant769 770def ptr_sp_rc : RegClassByHwMode<771 [MIPS32, MIPS64],772 [SP32, SP64]>;773 774def ptr_gp_rc : RegClassByHwMode<775 [MIPS32, MIPS64],776 [GP32, GP64]>;777