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1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the entry points for global functions defined in10// the LLVM NVPTX back-end.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H15#define LLVM_LIB_TARGET_NVPTX_NVPTX_H16 17#include "llvm/CodeGen/ISDOpcodes.h"18#include "llvm/IR/PassManager.h"19#include "llvm/Pass.h"20#include "llvm/Support/AtomicOrdering.h"21#include "llvm/Support/CodeGen.h"22#include "llvm/Target/TargetMachine.h"23namespace llvm {24class FunctionPass;25class MachineFunctionPass;26class NVPTXTargetMachine;27class PassRegistry;28 29namespace NVPTXCC {30enum CondCodes {31 EQ,32 NE,33 LT,34 LE,35 GT,36 GE37};38}39 40FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,41 llvm::CodeGenOptLevel OptLevel);42ModulePass *createNVPTXAssignValidGlobalNamesPass();43ModulePass *createGenericToNVVMLegacyPass();44ModulePass *createNVPTXCtorDtorLoweringLegacyPass();45FunctionPass *createNVVMIntrRangePass();46ModulePass *createNVVMReflectPass(unsigned int SmVersion);47MachineFunctionPass *createNVPTXPrologEpilogPass();48MachineFunctionPass *createNVPTXReplaceImageHandlesPass();49FunctionPass *createNVPTXImageOptimizerPass();50FunctionPass *createNVPTXLowerArgsPass();51FunctionPass *createNVPTXLowerAllocaPass();52FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable,53 bool NoTrapAfterNoreturn);54FunctionPass *createNVPTXTagInvariantLoadsPass();55MachineFunctionPass *createNVPTXPeephole();56MachineFunctionPass *createNVPTXProxyRegErasurePass();57MachineFunctionPass *createNVPTXForwardParamsPass();58 59void initializeNVVMReflectLegacyPassPass(PassRegistry &);60void initializeGenericToNVVMLegacyPassPass(PassRegistry &);61void initializeNVPTXAllocaHoistingPass(PassRegistry &);62void initializeNVPTXAsmPrinterPass(PassRegistry &);63void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &);64void initializeNVPTXAtomicLowerPass(PassRegistry &);65void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);66void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);67void initializeNVPTXLowerAllocaPass(PassRegistry &);68void initializeNVPTXLowerUnreachablePass(PassRegistry &);69void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &);70void initializeNVPTXProxyRegErasurePass(PassRegistry &);71void initializeNVPTXForwardParamsPassPass(PassRegistry &);72void initializeNVVMIntrRangePass(PassRegistry &);73void initializeNVVMReflectPass(PassRegistry &);74void initializeNVPTXAAWrapperPassPass(PassRegistry &);75void initializeNVPTXExternalAAWrapperPass(PassRegistry &);76void initializeNVPTXPeepholePass(PassRegistry &);77void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &);78void initializeNVPTXPrologEpilogPassPass(PassRegistry &);79 80struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {81 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);82};83 84struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {85 NVVMReflectPass() : SmVersion(0) {}86 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}87 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM);88 89private:90 unsigned SmVersion;91};92 93struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {94 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);95};96 97struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> {98 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);99};100 101struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> {102private:103 TargetMachine &TM;104 105public:106 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {};107 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);108};109 110struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> {111 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);112};113 114namespace NVPTX {115enum DrvInterface {116 NVCL,117 CUDA118};119 120// A field inside TSFlags needs a shift and a mask. The usage is121// always as follows :122// ((TSFlags & fieldMask) >> fieldShift)123// The enum keeps the mask, the shift, and all valid values of the124// field in one place.125enum VecInstType {126 VecInstTypeShift = 0,127 VecInstTypeMask = 0xF,128 129 VecNOP = 0,130 VecLoad = 1,131 VecStore = 2,132 VecBuild = 3,133 VecShuffle = 4,134 VecExtract = 5,135 VecInsert = 6,136 VecDest = 7,137 VecOther = 15138};139 140enum SimpleMove {141 SimpleMoveMask = 0x10,142 SimpleMoveShift = 4143};144enum LoadStore {145 isLoadMask = 0x20,146 isLoadShift = 5,147 isStoreMask = 0x40,148 isStoreShift = 6149};150 151// Extends LLVM AtomicOrdering with PTX Orderings:152using OrderingUnderlyingType = unsigned int;153enum Ordering : OrderingUnderlyingType {154 NotAtomic = (OrderingUnderlyingType)155 AtomicOrdering::NotAtomic, // PTX calls these: "Weak"156 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed157 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic,158 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire"159 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire,160 Release = (OrderingUnderlyingType)AtomicOrdering::Release,161 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease,162 SequentiallyConsistent =163 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent,164 Volatile = SequentiallyConsistent + 1,165 RelaxedMMIO = Volatile + 1,166};167 168using ScopeUnderlyingType = unsigned int;169enum Scope : ScopeUnderlyingType {170 Thread = 0,171 Block = 1,172 Cluster = 2,173 Device = 3,174 System = 4,175 DefaultDevice = 5, // For SM < 70: denotes PTX op implicit/default .gpu scope176 LASTSCOPE = DefaultDevice177};178 179using AddressSpaceUnderlyingType = unsigned int;180enum AddressSpace : AddressSpaceUnderlyingType {181 Generic = 0,182 Global = 1,183 Shared = 3,184 Const = 4,185 Local = 5,186 SharedCluster = 7,187 188 // NVPTX Backend Private:189 Param = 101190};191 192namespace PTXLdStInstCode {193enum FromType { Unsigned = 0, Signed, Float, Untyped };194} // namespace PTXLdStInstCode195 196/// PTXCvtMode - Conversion code enumeration197namespace PTXCvtMode {198enum CvtMode {199 NONE = 0,200 RNI,201 RZI,202 RMI,203 RPI,204 RN,205 RZ,206 RM,207 RP,208 RNA,209 RS,210 211 BASE_MASK = 0x0F,212 FTZ_FLAG = 0x10,213 SAT_FLAG = 0x20,214 RELU_FLAG = 0x40215};216}217 218/// PTXCmpMode - Comparison mode enumeration219namespace PTXCmpMode {220enum CmpMode {221 EQ = 0,222 NE,223 LT,224 LE,225 GT,226 GE,227 EQU,228 NEU,229 LTU,230 LEU,231 GTU,232 GEU,233 NUM,234 // NAN is a MACRO235 NotANumber,236};237}238 239namespace PTXPrmtMode {240enum PrmtMode {241 NONE,242 F4E,243 B4E,244 RC8,245 ECL,246 ECR,247 RC16,248};249}250 251enum class DivPrecisionLevel : unsigned {252 Approx = 0,253 Full = 1,254 IEEE754 = 2,255 IEEE754_NoFTZ = 3,256};257 258} // namespace NVPTX259void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);260} // namespace llvm261 262// Defines symbolic names for NVPTX registers. This defines a mapping from263// register name to register number.264#define GET_REGINFO_ENUM265#include "NVPTXGenRegisterInfo.inc"266 267// Defines symbolic names for the NVPTX instructions.268#define GET_INSTRINFO_ENUM269#define GET_INSTRINFO_MC_HELPER_DECLS270#include "NVPTXGenInstrInfo.inc"271 272#endif273