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1//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// This is the top level entry point for the NVPTX target.9//===----------------------------------------------------------------------===//10 11//===----------------------------------------------------------------------===//12// Target-independent interfaces13//===----------------------------------------------------------------------===//14 15include "llvm/Target/Target.td"16 17include "NVPTXRegisterInfo.td"18include "NVPTXInstrInfo.td"19 20//===----------------------------------------------------------------------===//21// Subtarget Features.22// - We use the SM version number instead of explicit feature table.23// - Need at least one feature to avoid generating zero sized array by24// TableGen in NVPTXGenSubtarget.inc.25//===----------------------------------------------------------------------===//26 27class FeatureSM<string sm, int value>:28 SubtargetFeature<"sm_"# sm, "FullSmVersion",29 "" # value,30 "Target SM " # sm>;31 32class FeaturePTX<int version>:33 SubtargetFeature<"ptx"# version, "PTXVersion",34 "" # version,35 "Use PTX version " # version>;36// NVPTX Architecture Hierarchy and Ordering:37//38// GPU architectures: sm_2Y/sm_3Y/sm_5Y/sm_6Y/sm_7Y/sm_8Y/sm_9Y/sm_10Y/sm_12Y39// ('Y' represents version within the architecture)40// The architectures have name of form sm_XYz where 'X' represent the generation41// number, 'Y' represents the version within the architecture, and 'z' represents42// the optional feature suffix.43// If X1Y1 <= X2Y2, then GPU capabilities of sm_X1Y1 are included in sm_X2Y2.44// For example, take sm_90 (9 represents 'X', 0 represents 'Y', and no feature45// suffix) and sm_103 architectures (10 represents 'X', 3 represents 'Y', and no46// feature suffix). Since 90 <= 103, sm_90 is compatible with sm_103.47//48// The family-specific variants have 'f' feature suffix and they follow49// following order:50// sm_X{Y2}f > sm_X{Y1}f iff Y2 > Y151// sm_XY{f} > sm_{XY}{}52//53// For example, take sm_100f (10 represents 'X', 0 represents 'Y', and 'f'54// represents 'z') and sm_103f (10 represents 'X', 3 represents 'Y', and 'f'55// represents 'z') architecture variants. Since Y1 < Y2, sm_100f is compatible with56// sm_103f. Similarly based on the second rule, sm_90 is compatible with sm_103f.57//58// Some counter examples, take sm_100f and sm_120f (12 represents 'X', 059// represents 'Y', and 'f' represents 'z') architecture variants. Since both60// belongs to different family i.e. X1 != X2, sm_100f is not compatible with61// sm_120f.62//63// The architecture-specific variants have 'a' feature suffix and they follow64// following order:65// sm_XY{a} > sm_XY{f} > sm_{XY}{}66//67// For example, take sm_103a (10 represents 'X', 3 represents 'Y', and 'a'68// represents 'z'), sm_103f, and sm_103 architecture variants. The sm_103 is69// compatible with sm_103a and sm_103f, and sm_103f is compatible with sm_103a.70//71// Encoding := Arch * 10 + 2 (for 'f') + 1 (for 'a')72// Arch := X * 10 + Y73//74// For example, sm_103a is encoded as 1033 (103 * 10 + 2 + 1) and sm_103f is75// encoded as 1032 (103 * 10 + 2).76//77// This encoding allows simple partial ordering of the architectures.78// + Compare Family and Arch by dividing FullSMVersion by 100 and 1079// respectively before the comparison.80// + Compare within the family by comparing FullSMVersion, given both belongs to81// the same family.82// + Detect 'a' variants by checking FullSMVersion & 1.83foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53, 60,84 61, 62, 70, 72, 75, 80, 86, 87, 88, 89,85 90, 100, 101, 103, 110, 120, 121] in {86 // Base SM version (e.g. FullSMVersion for sm_100 is 1000)87 def SM#sm : FeatureSM<""#sm, !mul(sm, 10)>;88 89 // Family-specific targets which are compatible within same family90 // (e.g. FullSMVersion for sm_100f is 1002)91 if !ge(sm, 100) then92 def SM#sm#f : FeatureSM<""#sm#"f", !add(!mul(sm, 10), 2)>;93 94 // Architecture-specific targets which are incompatible across architectures95 // (e.g. FullSMVersion for sm_100a is 1003)96 if !ge(sm, 90) then97 def SM#sm#a : FeatureSM<""#sm#"a", !add(!mul(sm, 10), 3)>;98}99 100foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65, 70, 71, 72,101 73, 74, 75, 76, 77, 78, 80, 81, 82, 83, 84, 85, 86, 87, 88,102 90] in103 def PTX#version : FeaturePTX<version>;104 105//===----------------------------------------------------------------------===//106// NVPTX supported processors.107//===----------------------------------------------------------------------===//108 109class Proc<string Name, list<SubtargetFeature> Features>110 : Processor<Name, NoItineraries, Features>;111 112def : Proc<"sm_20", [SM20, PTX32]>;113def : Proc<"sm_21", [SM21, PTX32]>;114def : Proc<"sm_30", [SM30]>;115def : Proc<"sm_32", [SM32, PTX40]>;116def : Proc<"sm_35", [SM35, PTX32]>;117def : Proc<"sm_37", [SM37, PTX41]>;118def : Proc<"sm_50", [SM50, PTX40]>;119def : Proc<"sm_52", [SM52, PTX41]>;120def : Proc<"sm_53", [SM53, PTX42]>;121def : Proc<"sm_60", [SM60, PTX50]>;122def : Proc<"sm_61", [SM61, PTX50]>;123def : Proc<"sm_62", [SM62, PTX50]>;124def : Proc<"sm_70", [SM70, PTX60]>;125def : Proc<"sm_72", [SM72, PTX61]>;126def : Proc<"sm_75", [SM75, PTX63]>;127def : Proc<"sm_80", [SM80, PTX70]>;128def : Proc<"sm_86", [SM86, PTX71]>;129def : Proc<"sm_87", [SM87, PTX74]>;130def : Proc<"sm_88", [SM88, PTX90]>;131def : Proc<"sm_89", [SM89, PTX78]>;132def : Proc<"sm_90", [SM90, PTX78]>;133def : Proc<"sm_90a", [SM90a, PTX80]>;134def : Proc<"sm_100", [SM100, PTX86]>;135def : Proc<"sm_100a", [SM100a, PTX86]>;136def : Proc<"sm_100f", [SM100f, PTX88]>;137def : Proc<"sm_101", [SM101, PTX86]>;138def : Proc<"sm_101a", [SM101a, PTX86]>;139def : Proc<"sm_101f", [SM101f, PTX88]>;140def : Proc<"sm_103", [SM103, PTX88]>;141def : Proc<"sm_103a", [SM103a, PTX88]>;142def : Proc<"sm_103f", [SM103f, PTX88]>;143def : Proc<"sm_110", [SM110, PTX90]>;144def : Proc<"sm_110a", [SM110a, PTX90]>;145def : Proc<"sm_110f", [SM110f, PTX90]>;146def : Proc<"sm_120", [SM120, PTX87]>;147def : Proc<"sm_120a", [SM120a, PTX87]>;148def : Proc<"sm_120f", [SM120f, PTX88]>;149def : Proc<"sm_121", [SM121, PTX88]>;150def : Proc<"sm_121a", [SM121a, PTX88]>;151def : Proc<"sm_121f", [SM121f, PTX88]>;152 153 154def Is64Bit : Predicate<"Subtarget->getTargetTriple().getArch() == Triple::nvptx64">;155def NVPTX64 : HwMode<[Is64Bit]>;156 157def nvptx_ptr_rc : RegClassByHwMode<158 [DefaultMode, NVPTX64],159 [B32, B64]>;160 161defm : RemapAllTargetPseudoPointerOperands<nvptx_ptr_rc>;162 163def NVPTXInstrInfo : InstrInfo {164}165 166def NVPTX : Target {167 let InstructionSet = NVPTXInstrInfo;168}169