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1//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Declarations that describe the PTX register file11//===----------------------------------------------------------------------===//12 13class NVPTXReg<string n> : Register<n> {14 let Namespace = "NVPTX";15}16 17class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>18 : RegisterClass <"NVPTX", regTypes, alignment, regList>;19 20//===----------------------------------------------------------------------===//21// Registers22//===----------------------------------------------------------------------===//23 24// Special Registers used as stack pointer25def VRFrame32 : NVPTXReg<"%SP">;26def VRFrame64 : NVPTXReg<"%SP">;27def VRFrameLocal32 : NVPTXReg<"%SPL">;28def VRFrameLocal64 : NVPTXReg<"%SPL">;29 30// Special Registers used as the stack31def VRDepot : NVPTXReg<"%Depot">;32 33// We use virtual registers, but define a few physical registers here to keep34// SDAG and the MachineInstr layers happy.35foreach i = 0...4 in {36 def P#i : NVPTXReg<"%p"#i>; // Predicate37 def RS#i : NVPTXReg<"%rs"#i>; // 16-bit38 def R#i : NVPTXReg<"%r"#i>; // 32-bit39 def RL#i : NVPTXReg<"%rd"#i>; // 64-bit40 def RQ#i : NVPTXReg<"%rq"#i>; // 128-bit41}42 43foreach i = 0...31 in {44 def ENVREG#i : NVPTXReg<"%envreg"#i>;45}46 47//===----------------------------------------------------------------------===//48// Register classes.49// NOTE: if you add new vector types for a register, you must update50// NVPTX::packed_types() in NVPTXUtilities.h accordingly!51//===----------------------------------------------------------------------===//52def B1 : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;53def B16 : NVPTXRegClass<[i16, f16, bf16], 16, (add (sequence "RS%u", 0, 4))>;54def B32 : NVPTXRegClass<[i32, v2f16, v2bf16, v2i16, v4i8, f32], 32,55 (add (sequence "R%u", 0, 4),56 VRFrame32, VRFrameLocal32)>;57def B64 : NVPTXRegClass<[i64, v2i32, v2f32, f64], 64,58 (add (sequence "RL%u", 0, 4),59 VRFrame64, VRFrameLocal64)>;60// 128-bit regs are not defined as general regs in NVPTX. They are used for inlineASM only.61def B128 : NVPTXRegClass<[i128], 128, (add (sequence "RQ%u", 0, 4))>;62 63// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.64def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame32, VRFrameLocal32, VRDepot,65 (sequence "ENVREG%u", 0, 31))>;66