487 lines · cpp
1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Top-level implementation for the NVPTX target.10//11//===----------------------------------------------------------------------===//12 13#include "NVPTXTargetMachine.h"14#include "NVPTX.h"15#include "NVPTXAliasAnalysis.h"16#include "NVPTXAllocaHoisting.h"17#include "NVPTXAtomicLower.h"18#include "NVPTXCtorDtorLowering.h"19#include "NVPTXLowerAggrCopies.h"20#include "NVPTXMachineFunctionInfo.h"21#include "NVPTXTargetObjectFile.h"22#include "NVPTXTargetTransformInfo.h"23#include "TargetInfo/NVPTXTargetInfo.h"24#include "llvm/Analysis/KernelInfo.h"25#include "llvm/Analysis/TargetTransformInfo.h"26#include "llvm/CodeGen/Passes.h"27#include "llvm/CodeGen/TargetPassConfig.h"28#include "llvm/IR/IntrinsicsNVPTX.h"29#include "llvm/MC/TargetRegistry.h"30#include "llvm/Pass.h"31#include "llvm/Passes/PassBuilder.h"32#include "llvm/Support/CommandLine.h"33#include "llvm/Support/Compiler.h"34#include "llvm/Target/TargetMachine.h"35#include "llvm/Target/TargetOptions.h"36#include "llvm/TargetParser/Triple.h"37#include "llvm/Transforms/IPO/ExpandVariadics.h"38#include "llvm/Transforms/Scalar.h"39#include "llvm/Transforms/Scalar/GVN.h"40#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"41#include <cassert>42#include <optional>43#include <string>44 45using namespace llvm;46 47// LSV is still relatively new; this switch lets us turn it off in case we48// encounter (or suspect) a bug.49static cl::opt<bool>50 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",51 cl::desc("Disable load/store vectorizer"),52 cl::init(false), cl::Hidden);53 54// TODO: Remove this flag when we are confident with no regressions.55static cl::opt<bool> DisableRequireStructuredCFG(56 "disable-nvptx-require-structured-cfg",57 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "58 "structured CFG. The requirement should be disabled only when "59 "unexpected regressions happen."),60 cl::init(false), cl::Hidden);61 62static cl::opt<bool> UseShortPointersOpt(63 "nvptx-short-ptr",64 cl::desc(65 "Use 32-bit pointers for accessing const/local/shared address spaces."),66 cl::init(false), cl::Hidden);67 68// byval arguments in NVPTX are special. We're only allowed to read from them69// using a special instruction, and if we ever need to write to them or take an70// address, we must make a local copy and use it, instead.71//72// The problem is that local copies are very expensive, and we create them very73// late in the compilation pipeline, so LLVM does not have much of a chance to74// eliminate them, if they turn out to be unnecessary.75//76// One way around that is to create such copies early on, and let them percolate77// through the optimizations. The copying itself will never trigger creation of78// another copy later on, as the reads are allowed. If LLVM can eliminate it,79// it's a win. It the full optimization pipeline can't remove the copy, that's80// as good as it gets in terms of the effort we could've done, and it's81// certainly a much better effort than what we do now.82//83// This early injection of the copies has potential to create undesireable84// side-effects, so it's disabled by default, for now, until it sees more85// testing.86static cl::opt<bool> EarlyByValArgsCopy(87 "nvptx-early-byval-copy",88 cl::desc("Create a copy of byval function arguments early."),89 cl::init(false), cl::Hidden);90 91extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {92 // Register the target.93 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());94 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());95 96 PassRegistry &PR = *PassRegistry::getPassRegistry();97 // FIXME: This pass is really intended to be invoked during IR optimization,98 // but it's very NVPTX-specific.99 initializeNVVMReflectLegacyPassPass(PR);100 initializeNVVMIntrRangePass(PR);101 initializeGenericToNVVMLegacyPassPass(PR);102 initializeNVPTXAllocaHoistingPass(PR);103 initializeNVPTXAsmPrinterPass(PR);104 initializeNVPTXAssignValidGlobalNamesPass(PR);105 initializeNVPTXAtomicLowerPass(PR);106 initializeNVPTXLowerArgsLegacyPassPass(PR);107 initializeNVPTXLowerAllocaPass(PR);108 initializeNVPTXLowerUnreachablePass(PR);109 initializeNVPTXCtorDtorLoweringLegacyPass(PR);110 initializeNVPTXLowerAggrCopiesPass(PR);111 initializeNVPTXProxyRegErasurePass(PR);112 initializeNVPTXForwardParamsPassPass(PR);113 initializeNVPTXDAGToDAGISelLegacyPass(PR);114 initializeNVPTXAAWrapperPassPass(PR);115 initializeNVPTXExternalAAWrapperPass(PR);116 initializeNVPTXPeepholePass(PR);117 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);118 initializeNVPTXPrologEpilogPassPass(PR);119}120 121NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,122 StringRef CPU, StringRef FS,123 const TargetOptions &Options,124 std::optional<Reloc::Model> RM,125 std::optional<CodeModel::Model> CM,126 CodeGenOptLevel OL, bool is64bit)127 // The pic relocation model is used regardless of what the client has128 // specified, as it is the only relocation model currently supported.129 : CodeGenTargetMachineImpl(130 T, TT.computeDataLayout(UseShortPointersOpt ? "shortptr" : ""), TT,131 CPU, FS, Options, Reloc::PIC_,132 getEffectiveCodeModel(CM, CodeModel::Small), OL),133 is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),134 Subtarget(TT, std::string(CPU), std::string(FS), *this),135 StrPool(StrAlloc) {136 if (TT.getOS() == Triple::NVCL)137 drvInterface = NVPTX::NVCL;138 else139 drvInterface = NVPTX::CUDA;140 if (!DisableRequireStructuredCFG)141 setRequiresStructuredCFG(true);142 initAsmInfo();143}144 145NVPTXTargetMachine::~NVPTXTargetMachine() = default;146 147void NVPTXTargetMachine32::anchor() {}148 149NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,150 StringRef CPU, StringRef FS,151 const TargetOptions &Options,152 std::optional<Reloc::Model> RM,153 std::optional<CodeModel::Model> CM,154 CodeGenOptLevel OL, bool JIT)155 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}156 157void NVPTXTargetMachine64::anchor() {}158 159NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,160 StringRef CPU, StringRef FS,161 const TargetOptions &Options,162 std::optional<Reloc::Model> RM,163 std::optional<CodeModel::Model> CM,164 CodeGenOptLevel OL, bool JIT)165 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}166 167namespace {168 169class NVPTXPassConfig : public TargetPassConfig {170public:171 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)172 : TargetPassConfig(TM, PM) {}173 174 NVPTXTargetMachine &getNVPTXTargetMachine() const {175 return getTM<NVPTXTargetMachine>();176 }177 178 void addIRPasses() override;179 bool addInstSelector() override;180 void addPreRegAlloc() override;181 void addPostRegAlloc() override;182 void addMachineSSAOptimization() override;183 184 FunctionPass *createTargetRegisterAllocator(bool) override;185 void addFastRegAlloc() override;186 void addOptimizedRegAlloc() override;187 188 bool addRegAssignAndRewriteFast() override {189 llvm_unreachable("should not be used");190 }191 192 bool addRegAssignAndRewriteOptimized() override {193 llvm_unreachable("should not be used");194 }195 196private:197 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This198 // function is only called in opt mode.199 void addEarlyCSEOrGVNPass();200 201 // Add passes that propagate special memory spaces.202 void addAddressSpaceInferencePasses();203 204 // Add passes that perform straight-line scalar optimizations.205 void addStraightLineScalarOptimizationPasses();206};207 208} // end anonymous namespace209 210TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {211 return new NVPTXPassConfig(*this, PM);212}213 214MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(215 BumpPtrAllocator &Allocator, const Function &F,216 const TargetSubtargetInfo *STI) const {217 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,218 F, STI);219}220 221void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {222 AAM.registerFunctionAnalysis<NVPTXAA>();223}224 225void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {226#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"227#include "llvm/Passes/TargetPassRegistry.inc"228 229 PB.registerPipelineStartEPCallback(230 [this](ModulePassManager &PM, OptimizationLevel Level) {231 // We do not want to fold out calls to nvvm.reflect early if the user232 // has not provided a target architecture just yet.233 if (Subtarget.hasTargetName())234 PM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));235 236 FunctionPassManager FPM;237 // Note: NVVMIntrRangePass was causing numerical discrepancies at one238 // point, if issues crop up, consider disabling.239 FPM.addPass(NVVMIntrRangePass());240 if (EarlyByValArgsCopy)241 FPM.addPass(NVPTXCopyByValArgsPass());242 PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));243 });244 245 if (!NoKernelInfoEndLTO) {246 PB.registerFullLinkTimeOptimizationLastEPCallback(247 [this](ModulePassManager &PM, OptimizationLevel Level) {248 FunctionPassManager FPM;249 FPM.addPass(KernelInfoPrinter(this));250 PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));251 });252 }253}254 255TargetTransformInfo256NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {257 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(this, F));258}259 260std::pair<const Value *, unsigned>261NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {262 if (auto *II = dyn_cast<IntrinsicInst>(V)) {263 switch (II->getIntrinsicID()) {264 case Intrinsic::nvvm_isspacep_const:265 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_CONST);266 case Intrinsic::nvvm_isspacep_global:267 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_GLOBAL);268 case Intrinsic::nvvm_isspacep_local:269 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_LOCAL);270 case Intrinsic::nvvm_isspacep_shared:271 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_SHARED);272 case Intrinsic::nvvm_isspacep_shared_cluster:273 return std::make_pair(II->getArgOperand(0),274 llvm::ADDRESS_SPACE_SHARED_CLUSTER);275 default:276 break;277 }278 }279 return std::make_pair(nullptr, -1);280}281 282void NVPTXPassConfig::addEarlyCSEOrGVNPass() {283 if (getOptLevel() == CodeGenOptLevel::Aggressive)284 addPass(createGVNPass());285 else286 addPass(createEarlyCSEPass());287}288 289void NVPTXPassConfig::addAddressSpaceInferencePasses() {290 // NVPTXLowerArgs emits alloca for byval parameters which can often291 // be eliminated by SROA.292 addPass(createSROAPass());293 addPass(createNVPTXLowerAllocaPass());294 // TODO: Consider running InferAddressSpaces during opt, earlier in the295 // compilation flow.296 addPass(createInferAddressSpacesPass());297 addPass(createNVPTXAtomicLowerPass());298}299 300void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {301 addPass(createSeparateConstOffsetFromGEPPass());302 addPass(createSpeculativeExecutionPass());303 // ReassociateGEPs exposes more opportunites for SLSR. See304 // the example in reassociate-geps-and-slsr.ll.305 addPass(createStraightLineStrengthReducePass());306 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or307 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE308 // for some of our benchmarks.309 addEarlyCSEOrGVNPass();310 // Run NaryReassociate after EarlyCSE/GVN to be more effective.311 addPass(createNaryReassociatePass());312 // NaryReassociate on GEPs creates redundant common expressions, so run313 // EarlyCSE after it.314 addPass(createEarlyCSEPass());315}316 317void NVPTXPassConfig::addIRPasses() {318 // The following passes are known to not play well with virtual regs hanging319 // around after register allocation (which in our case, is *all* registers).320 // We explicitly disable them here. We do, however, need some functionality321 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the322 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).323 disablePass(&PrologEpilogCodeInserterID);324 disablePass(&MachineLateInstrsCleanupID);325 disablePass(&MachineCopyPropagationID);326 disablePass(&TailDuplicateLegacyID);327 disablePass(&StackMapLivenessID);328 disablePass(&PostRAMachineSinkingID);329 disablePass(&PostRASchedulerID);330 disablePass(&FuncletLayoutID);331 disablePass(&PatchableFunctionID);332 disablePass(&ShrinkWrapID);333 disablePass(&RemoveLoadsIntoFakeUsesID);334 335 addPass(createNVPTXAAWrapperPass());336 addPass(createNVPTXExternalAAWrapperPass());337 338 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running339 // it here does nothing. But since we need it for correctness when lowering340 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't341 // call addEarlyAsPossiblePasses.342 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();343 addPass(createNVVMReflectPass(ST.getSmVersion()));344 345 if (getOptLevel() != CodeGenOptLevel::None)346 addPass(createNVPTXImageOptimizerPass());347 addPass(createNVPTXAssignValidGlobalNamesPass());348 addPass(createGenericToNVVMLegacyPass());349 350 // NVPTXLowerArgs is required for correctness and should be run right351 // before the address space inference passes.352 addPass(createNVPTXLowerArgsPass());353 if (getOptLevel() != CodeGenOptLevel::None) {354 addAddressSpaceInferencePasses();355 addStraightLineScalarOptimizationPasses();356 }357 358 addPass(createAtomicExpandLegacyPass());359 addPass(createExpandVariadicsPass(ExpandVariadicsMode::Lowering));360 addPass(createNVPTXCtorDtorLoweringLegacyPass());361 362 // === LSR and other generic IR passes ===363 TargetPassConfig::addIRPasses();364 // EarlyCSE is not always strong enough to clean up what LSR produces. For365 // example, GVN can combine366 //367 // %0 = add %a, %b368 // %1 = add %b, %a369 //370 // and371 //372 // %0 = shl nsw %a, 2373 // %1 = shl %a, 2374 //375 // but EarlyCSE can do neither of them.376 if (getOptLevel() != CodeGenOptLevel::None) {377 addEarlyCSEOrGVNPass();378 if (!DisableLoadStoreVectorizer)379 addPass(createLoadStoreVectorizerPass());380 addPass(createSROAPass());381 addPass(createNVPTXTagInvariantLoadsPass());382 }383 384 if (ST.hasPTXASUnreachableBug()) {385 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of386 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.387 const auto &Options = getNVPTXTargetMachine().Options;388 addPass(createNVPTXLowerUnreachablePass(Options.TrapUnreachable,389 Options.NoTrapAfterNoreturn));390 }391}392 393bool NVPTXPassConfig::addInstSelector() {394 addPass(createLowerAggrCopies());395 addPass(createAllocaHoisting());396 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));397 addPass(createNVPTXReplaceImageHandlesPass());398 399 return false;400}401 402void NVPTXPassConfig::addPreRegAlloc() {403 addPass(createNVPTXForwardParamsPass());404 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.405 addPass(createNVPTXProxyRegErasurePass());406}407 408void NVPTXPassConfig::addPostRegAlloc() {409 addPass(createNVPTXPrologEpilogPass());410 if (getOptLevel() != CodeGenOptLevel::None) {411 // NVPTXPrologEpilogPass calculates frame object offset and replace frame412 // index with VRFrame register. NVPTXPeephole need to be run after that and413 // will replace VRFrame with VRFrameLocal when possible.414 addPass(createNVPTXPeephole());415 }416}417 418FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {419 return nullptr; // No reg alloc420}421 422void NVPTXPassConfig::addFastRegAlloc() {423 addPass(&PHIEliminationID);424 addPass(&TwoAddressInstructionPassID);425}426 427void NVPTXPassConfig::addOptimizedRegAlloc() {428 addPass(&ProcessImplicitDefsID);429 addPass(&LiveVariablesID);430 addPass(&MachineLoopInfoID);431 addPass(&PHIEliminationID);432 433 addPass(&TwoAddressInstructionPassID);434 addPass(&RegisterCoalescerID);435 436 // PreRA instruction scheduling.437 if (addPass(&MachineSchedulerID))438 printAndVerify("After Machine Scheduling");439 440 addPass(&StackSlotColoringID);441 442 // FIXME: Needs physical registers443 // addPass(&MachineLICMID);444 445 printAndVerify("After StackSlotColoring");446}447 448void NVPTXPassConfig::addMachineSSAOptimization() {449 // Pre-ra tail duplication.450 if (addPass(&EarlyTailDuplicateLegacyID))451 printAndVerify("After Pre-RegAlloc TailDuplicate");452 453 // Optimize PHIs before DCE: removing dead PHI cycles may make more454 // instructions dead.455 addPass(&OptimizePHIsLegacyID);456 457 // This pass merges large allocas. StackSlotColoring is a different pass458 // which merges spill slots.459 addPass(&StackColoringLegacyID);460 461 // If the target requests it, assign local variables to stack slots relative462 // to one another and simplify frame index references where possible.463 addPass(&LocalStackSlotAllocationID);464 465 // With optimization, dead code should already be eliminated. However466 // there is one known exception: lowered code for arguments that are only467 // used by tail calls, where the tail calls reuse the incoming stack468 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).469 addPass(&DeadMachineInstructionElimID);470 printAndVerify("After codegen DCE pass");471 472 // Allow targets to insert passes that improve instruction level parallelism,473 // like if-conversion. Such passes will typically need dominator trees and474 // loop info, just like LICM and CSE below.475 if (addILPOpts())476 printAndVerify("After ILP optimizations");477 478 addPass(&EarlyMachineLICMID);479 addPass(&MachineCSELegacyID);480 481 addPass(&MachineSinkingLegacyID);482 printAndVerify("After Machine LICM, CSE and Sinking passes");483 484 addPass(&PeepholeOptimizerLegacyID);485 printAndVerify("After codegen peephole optimization pass");486}487