687 lines · cpp
1//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This class prints an PPC MCInst to a .s file.10//11//===----------------------------------------------------------------------===//12 13#include "MCTargetDesc/PPCInstPrinter.h"14#include "MCTargetDesc/PPCMCTargetDesc.h"15#include "MCTargetDesc/PPCPredicates.h"16#include "PPCMCAsmInfo.h"17#include "llvm/MC/MCAsmInfo.h"18#include "llvm/MC/MCExpr.h"19#include "llvm/MC/MCInst.h"20#include "llvm/MC/MCInstrInfo.h"21#include "llvm/MC/MCRegisterInfo.h"22#include "llvm/MC/MCSubtargetInfo.h"23#include "llvm/MC/MCSymbol.h"24#include "llvm/Support/Casting.h"25#include "llvm/Support/CommandLine.h"26#include "llvm/Support/raw_ostream.h"27using namespace llvm;28 29#define DEBUG_TYPE "asm-printer"30 31// FIXME: Once the integrated assembler supports full register names, tie this32// to the verbose-asm setting.33static cl::opt<bool>34FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),35 cl::desc("Use full register names when printing assembly"));36 37// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.38static cl::opt<bool>39ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),40 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));41 42// Prints full register names with percent symbol.43static cl::opt<bool>44FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,45 cl::init(false),46 cl::desc("Prints full register names with percent"));47 48#define PRINT_ALIAS_INSTR49#include "PPCGenAsmWriter.inc"50 51void PPCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {52 const char *RegName = getRegisterName(Reg);53 OS << RegName;54}55 56void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,57 StringRef Annot, const MCSubtargetInfo &STI,58 raw_ostream &O) {59 // Customize printing of the addis instruction on AIX. When an operand is a60 // symbol reference, the instruction syntax is changed to look like a load61 // operation, i.e:62 // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).63 if (TT.isOSAIX() &&64 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&65 MI->getOperand(2).isExpr()) {66 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&67 "The first and the second operand of an addis instruction"68 " should be registers.");69 70 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&71 "The third operand of an addis instruction should be a symbol "72 "reference expression if it is an expression at all.");73 74 O << "\taddis ";75 printOperand(MI, 0, STI, O);76 O << ", ";77 printOperand(MI, 2, STI, O);78 O << "(";79 printOperand(MI, 1, STI, O);80 O << ")";81 return;82 }83 84 // Check if the last operand is an expression with the variant kind85 // VK_PCREL_OPT. If this is the case then this is a linker optimization86 // relocation and the .reloc directive needs to be added.87 unsigned LastOp = MI->getNumOperands() - 1;88 if (MI->getNumOperands() > 1) {89 const MCOperand &Operand = MI->getOperand(LastOp);90 if (Operand.isExpr()) {91 const MCExpr *Expr = Operand.getExpr();92 const MCSymbolRefExpr *SymExpr =93 static_cast<const MCSymbolRefExpr *>(Expr);94 95 if (SymExpr && getSpecifier(SymExpr) == PPC::S_PCREL_OPT) {96 const MCSymbol &Symbol = SymExpr->getSymbol();97 if (MI->getOpcode() == PPC::PLDpc) {98 printInstruction(MI, Address, STI, O);99 O << "\n";100 Symbol.print(O, &MAI);101 O << ":";102 return;103 } else {104 O << "\t.reloc ";105 Symbol.print(O, &MAI);106 O << "-8,R_PPC64_PCREL_OPT,.-(";107 Symbol.print(O, &MAI);108 O << "-8)\n";109 }110 }111 }112 }113 114 // Check for slwi/srwi mnemonics.115 if (MI->getOpcode() == PPC::RLWINM) {116 unsigned char SH = MI->getOperand(2).getImm();117 unsigned char MB = MI->getOperand(3).getImm();118 unsigned char ME = MI->getOperand(4).getImm();119 bool useSubstituteMnemonic = false;120 if (SH <= 31 && MB == 0 && ME == (31-SH)) {121 O << "\tslwi "; useSubstituteMnemonic = true;122 }123 if (SH <= 31 && MB == (32-SH) && ME == 31) {124 O << "\tsrwi "; useSubstituteMnemonic = true;125 SH = 32-SH;126 }127 if (useSubstituteMnemonic) {128 printOperand(MI, 0, STI, O);129 O << ", ";130 printOperand(MI, 1, STI, O);131 O << ", " << (unsigned int)SH;132 133 printAnnotation(O, Annot);134 return;135 }136 }137 138 if (MI->getOpcode() == PPC::RLDICR ||139 MI->getOpcode() == PPC::RLDICR_32) {140 unsigned char SH = MI->getOperand(2).getImm();141 unsigned char ME = MI->getOperand(3).getImm();142 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH143 if (63-SH == ME) {144 O << "\tsldi ";145 printOperand(MI, 0, STI, O);146 O << ", ";147 printOperand(MI, 1, STI, O);148 O << ", " << (unsigned int)SH;149 printAnnotation(O, Annot);150 return;151 }152 }153 154 // dcbt[st] is printed manually here because:155 // 1. The assembly syntax is different between embedded and server targets156 // 2. We must print the short mnemonics for TH == 0 because the157 // embedded/server syntax default will not be stable across assemblers158 // The syntax for dcbt is:159 // dcbt ra, rb, th [server]160 // dcbt th, ra, rb [embedded]161 // where th can be omitted when it is 0. dcbtst is the same.162 // On AIX, only emit the extended mnemonics for dcbt and dcbtst if163 // the "modern assembler" is available.164 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&165 (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) {166 unsigned char TH = MI->getOperand(0).getImm();167 O << "\tdcbt";168 if (MI->getOpcode() == PPC::DCBTST)169 O << "st";170 if (TH == 16)171 O << "t";172 O << " ";173 174 bool IsBookE = STI.hasFeature(PPC::FeatureBookE);175 if (IsBookE && TH != 0 && TH != 16)176 O << (unsigned int) TH << ", ";177 178 printOperand(MI, 1, STI, O);179 O << ", ";180 printOperand(MI, 2, STI, O);181 182 if (!IsBookE && TH != 0 && TH != 16)183 O << ", " << (unsigned int) TH;184 185 printAnnotation(O, Annot);186 return;187 }188 189 if (MI->getOpcode() == PPC::DCBF) {190 unsigned char L = MI->getOperand(0).getImm();191 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {192 O << "\tdcb";193 if (L != 6)194 O << "f";195 if (L == 1)196 O << "l";197 if (L == 3)198 O << "lp";199 if (L == 4)200 O << "ps";201 if (L == 6)202 O << "stps";203 O << " ";204 205 printOperand(MI, 1, STI, O);206 O << ", ";207 printOperand(MI, 2, STI, O);208 209 printAnnotation(O, Annot);210 return;211 }212 }213 214 if (!printAliasInstr(MI, Address, STI, O))215 printInstruction(MI, Address, STI, O);216 printAnnotation(O, Annot);217}218 219void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,220 const MCSubtargetInfo &STI,221 raw_ostream &O, StringRef Modifier) {222 unsigned Code = MI->getOperand(OpNo).getImm();223 224 if (Modifier == "cc") {225 switch ((PPC::Predicate)Code) {226 case PPC::PRED_LT_MINUS:227 case PPC::PRED_LT_PLUS:228 case PPC::PRED_LT:229 O << "lt";230 return;231 case PPC::PRED_LE_MINUS:232 case PPC::PRED_LE_PLUS:233 case PPC::PRED_LE:234 O << "le";235 return;236 case PPC::PRED_EQ_MINUS:237 case PPC::PRED_EQ_PLUS:238 case PPC::PRED_EQ:239 O << "eq";240 return;241 case PPC::PRED_GE_MINUS:242 case PPC::PRED_GE_PLUS:243 case PPC::PRED_GE:244 O << "ge";245 return;246 case PPC::PRED_GT_MINUS:247 case PPC::PRED_GT_PLUS:248 case PPC::PRED_GT:249 O << "gt";250 return;251 case PPC::PRED_NE_MINUS:252 case PPC::PRED_NE_PLUS:253 case PPC::PRED_NE:254 O << "ne";255 return;256 case PPC::PRED_UN_MINUS:257 case PPC::PRED_UN_PLUS:258 case PPC::PRED_UN:259 O << "un";260 return;261 case PPC::PRED_NU_MINUS:262 case PPC::PRED_NU_PLUS:263 case PPC::PRED_NU:264 O << "nu";265 return;266 case PPC::PRED_BIT_SET:267 case PPC::PRED_BIT_UNSET:268 llvm_unreachable("Invalid use of bit predicate code");269 }270 llvm_unreachable("Invalid predicate code");271 }272 273 if (Modifier == "pm") {274 switch ((PPC::Predicate)Code) {275 case PPC::PRED_LT:276 case PPC::PRED_LE:277 case PPC::PRED_EQ:278 case PPC::PRED_GE:279 case PPC::PRED_GT:280 case PPC::PRED_NE:281 case PPC::PRED_UN:282 case PPC::PRED_NU:283 return;284 case PPC::PRED_LT_MINUS:285 case PPC::PRED_LE_MINUS:286 case PPC::PRED_EQ_MINUS:287 case PPC::PRED_GE_MINUS:288 case PPC::PRED_GT_MINUS:289 case PPC::PRED_NE_MINUS:290 case PPC::PRED_UN_MINUS:291 case PPC::PRED_NU_MINUS:292 O << "-";293 return;294 case PPC::PRED_LT_PLUS:295 case PPC::PRED_LE_PLUS:296 case PPC::PRED_EQ_PLUS:297 case PPC::PRED_GE_PLUS:298 case PPC::PRED_GT_PLUS:299 case PPC::PRED_NE_PLUS:300 case PPC::PRED_UN_PLUS:301 case PPC::PRED_NU_PLUS:302 O << "+";303 return;304 case PPC::PRED_BIT_SET:305 case PPC::PRED_BIT_UNSET:306 llvm_unreachable("Invalid use of bit predicate code");307 }308 llvm_unreachable("Invalid predicate code");309 }310 311 assert(Modifier == "reg" &&312 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");313 printOperand(MI, OpNo + 1, STI, O);314}315 316void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,317 const MCSubtargetInfo &STI,318 raw_ostream &O) {319 unsigned Code = MI->getOperand(OpNo).getImm();320 if (Code == 2)321 O << "-";322 else if (Code == 3)323 O << "+";324}325 326void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,327 const MCSubtargetInfo &STI,328 raw_ostream &O) {329 unsigned int Value = MI->getOperand(OpNo).getImm();330 assert(Value <= 1 && "Invalid u1imm argument!");331 O << (unsigned int)Value;332}333 334void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,335 const MCSubtargetInfo &STI,336 raw_ostream &O) {337 unsigned int Value = MI->getOperand(OpNo).getImm();338 assert(Value <= 3 && "Invalid u2imm argument!");339 O << (unsigned int)Value;340}341 342void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,343 const MCSubtargetInfo &STI,344 raw_ostream &O) {345 unsigned int Value = MI->getOperand(OpNo).getImm();346 assert(Value <= 8 && "Invalid u3imm argument!");347 O << (unsigned int)Value;348}349 350void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,351 const MCSubtargetInfo &STI,352 raw_ostream &O) {353 unsigned int Value = MI->getOperand(OpNo).getImm();354 assert(Value <= 15 && "Invalid u4imm argument!");355 O << (unsigned int)Value;356}357 358void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,359 const MCSubtargetInfo &STI,360 raw_ostream &O) {361 int Value = MI->getOperand(OpNo).getImm();362 Value = SignExtend32<5>(Value);363 O << (int)Value;364}365 366void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,367 const MCSubtargetInfo &STI,368 raw_ostream &O) {369 unsigned int Value = MI->getOperand(OpNo).getImm();370 assert(Value == 0 && "Operand must be zero");371 O << (unsigned int)Value;372}373 374void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,375 const MCSubtargetInfo &STI,376 raw_ostream &O) {377 unsigned int Value = MI->getOperand(OpNo).getImm();378 assert(Value <= 31 && "Invalid u5imm argument!");379 O << (unsigned int)Value;380}381 382void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,383 const MCSubtargetInfo &STI,384 raw_ostream &O) {385 unsigned int Value = MI->getOperand(OpNo).getImm();386 assert(Value <= 63 && "Invalid u6imm argument!");387 O << (unsigned int)Value;388}389 390void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,391 const MCSubtargetInfo &STI,392 raw_ostream &O) {393 unsigned int Value = MI->getOperand(OpNo).getImm();394 assert(Value <= 127 && "Invalid u7imm argument!");395 O << (unsigned int)Value;396}397 398// Operands of BUILD_VECTOR are signed and we use this to print operands399// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and400// print as unsigned.401void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,402 const MCSubtargetInfo &STI,403 raw_ostream &O) {404 unsigned char Value = MI->getOperand(OpNo).getImm();405 O << (unsigned int)Value;406}407 408void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,409 const MCSubtargetInfo &STI,410 raw_ostream &O) {411 unsigned short Value = MI->getOperand(OpNo).getImm();412 assert(Value <= 1023 && "Invalid u10imm argument!");413 O << (unsigned short)Value;414}415 416void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,417 const MCSubtargetInfo &STI,418 raw_ostream &O) {419 unsigned short Value = MI->getOperand(OpNo).getImm();420 assert(Value <= 4095 && "Invalid u12imm argument!");421 O << (unsigned short)Value;422}423 424void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,425 const MCSubtargetInfo &STI,426 raw_ostream &O) {427 if (MI->getOperand(OpNo).isImm())428 O << (short)MI->getOperand(OpNo).getImm();429 else430 printOperand(MI, OpNo, STI, O);431}432 433void PPCInstPrinter::printS32ImmOperand(const MCInst *MI, unsigned OpNo,434 const MCSubtargetInfo &STI,435 raw_ostream &O) {436 if (MI->getOperand(OpNo).isImm()) {437 long long Value = MI->getOperand(OpNo).getImm();438 assert(isInt<32>(Value) && "Invalid s32imm argument!");439 O << (long long)Value;440 } else441 printOperand(MI, OpNo, STI, O);442}443 444void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,445 const MCSubtargetInfo &STI,446 raw_ostream &O) {447 if (MI->getOperand(OpNo).isImm()) {448 long long Value = MI->getOperand(OpNo).getImm();449 assert(isInt<34>(Value) && "Invalid s34imm argument!");450 O << (long long)Value;451 }452 else453 printOperand(MI, OpNo, STI, O);454}455 456void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,457 const MCSubtargetInfo &STI,458 raw_ostream &O) {459 if (MI->getOperand(OpNo).isImm())460 O << (unsigned short)MI->getOperand(OpNo).getImm();461 else462 printOperand(MI, OpNo, STI, O);463}464 465void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,466 unsigned OpNo,467 const MCSubtargetInfo &STI,468 raw_ostream &O) {469 if (!MI->getOperand(OpNo).isImm())470 return printOperand(MI, OpNo, STI, O);471 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);472 if (PrintBranchImmAsAddress) {473 uint64_t Target = Address + Imm;474 if (!TT.isPPC64())475 Target &= 0xffffffff;476 O << formatHex(Target);477 } else {478 // Branches can take an immediate operand. This is used by the branch479 // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)480 // to express an eight byte displacement from the program counter.481 if (!TT.isOSAIX())482 O << ".";483 else484 O << "$";485 486 if (Imm >= 0)487 O << "+";488 O << Imm;489 }490}491 492void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,493 const MCSubtargetInfo &STI,494 raw_ostream &O) {495 if (!MI->getOperand(OpNo).isImm())496 return printOperand(MI, OpNo, STI, O);497 498 uint64_t Imm = static_cast<uint64_t>(MI->getOperand(OpNo).getImm()) << 2;499 if (!TT.isPPC64())500 Imm = static_cast<uint32_t>(Imm);501 O << formatHex(Imm);502}503 504void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,505 const MCSubtargetInfo &STI, raw_ostream &O) {506 MCRegister CCReg = MI->getOperand(OpNo).getReg();507 unsigned RegNo;508 switch (CCReg.id()) {509 default: llvm_unreachable("Unknown CR register");510 case PPC::CR0: RegNo = 0; break;511 case PPC::CR1: RegNo = 1; break;512 case PPC::CR2: RegNo = 2; break;513 case PPC::CR3: RegNo = 3; break;514 case PPC::CR4: RegNo = 4; break;515 case PPC::CR5: RegNo = 5; break;516 case PPC::CR6: RegNo = 6; break;517 case PPC::CR7: RegNo = 7; break;518 }519 O << (0x80 >> RegNo);520}521 522void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,523 const MCSubtargetInfo &STI,524 raw_ostream &O) {525 printS16ImmOperand(MI, OpNo, STI, O);526 O << '(';527 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)528 O << "0";529 else530 printOperand(MI, OpNo + 1, STI, O);531 O << ')';532}533 534void PPCInstPrinter::printMemRegImmHash(const MCInst *MI, unsigned OpNo,535 const MCSubtargetInfo &STI,536 raw_ostream &O) {537 O << MI->getOperand(OpNo).getImm();538 O << '(';539 printOperand(MI, OpNo + 1, STI, O);540 O << ')';541}542 543void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,544 const MCSubtargetInfo &STI,545 raw_ostream &O) {546 printS34ImmOperand(MI, OpNo, STI, O);547 O << '(';548 printImmZeroOperand(MI, OpNo + 1, STI, O);549 O << ')';550}551 552void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,553 const MCSubtargetInfo &STI,554 raw_ostream &O) {555 printS34ImmOperand(MI, OpNo, STI, O);556 O << '(';557 printOperand(MI, OpNo + 1, STI, O);558 O << ')';559}560 561void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,562 const MCSubtargetInfo &STI,563 raw_ostream &O) {564 // When used as the base register, r0 reads constant zero rather than565 // the value contained in the register. For this reason, the darwin566 // assembler requires that we print r0 as 0 (no r) when used as the base.567 if (MI->getOperand(OpNo).getReg() == PPC::R0)568 O << "0";569 else570 printOperand(MI, OpNo, STI, O);571 O << ", ";572 printOperand(MI, OpNo + 1, STI, O);573}574 575void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,576 const MCSubtargetInfo &STI, raw_ostream &O) {577 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must578 // come at the _end_ of the expression.579 const MCOperand &Op = MI->getOperand(OpNo);580 const MCSymbolRefExpr *RefExp = nullptr;581 const MCExpr *Rhs = nullptr;582 if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {583 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());584 Rhs = BinExpr->getRHS();585 } else586 RefExp = cast<MCSymbolRefExpr>(Op.getExpr());587 588 O << RefExp->getSymbol().getName();589 // The variant kind VK_NOTOC needs to be handled as a special case590 // because we do not want the assembly to print out the @notoc at the591 // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look592 // like __tls_get_addr@notoc(x@tlsgd).593 if (getSpecifier(RefExp) == PPC::S_NOTOC)594 O << '@' << MAI.getSpecifierName(RefExp->getKind());595 O << '(';596 printOperand(MI, OpNo + 1, STI, O);597 O << ')';598 if (getSpecifier(RefExp) != PPC::S_None &&599 getSpecifier(RefExp) != PPC::S_NOTOC)600 O << '@' << MAI.getSpecifierName(RefExp->getKind());601 if (Rhs) {602 SmallString<0> Buf;603 raw_svector_ostream Tmp(Buf);604 MAI.printExpr(Tmp, *Rhs);605 if (isdigit(Buf[0]))606 O << '+';607 O << Buf;608 }609}610 611/// showRegistersWithPercentPrefix - Check if this register name should be612/// printed with a percentage symbol as prefix.613bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {614 if ((!FullRegNamesWithPercent && !MAI.useFullRegisterNames()) ||615 TT.getOS() == Triple::AIX)616 return false;617 618 switch (RegName[0]) {619 default:620 return false;621 case 'r':622 case 'f':623 case 'q':624 case 'v':625 case 'c':626 return true;627 }628}629 630/// getVerboseConditionalRegName - This method expands the condition register631/// when requested explicitly or targetting Darwin.632const char *633PPCInstPrinter::getVerboseConditionRegName(MCRegister Reg,634 unsigned RegEncoding) const {635 if (!FullRegNames && !MAI.useFullRegisterNames())636 return nullptr;637 if (Reg < PPC::CR0EQ || Reg > PPC::CR7UN)638 return nullptr;639 const char *CRBits[] = {640 "lt", "gt", "eq", "un",641 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",642 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",643 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",644 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",645 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",646 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",647 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"648 };649 return CRBits[RegEncoding];650}651 652// showRegistersWithPrefix - This method determines whether registers653// should be number-only or include the prefix.654bool PPCInstPrinter::showRegistersWithPrefix() const {655 return FullRegNamesWithPercent || FullRegNames || MAI.useFullRegisterNames();656}657 658void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,659 const MCSubtargetInfo &STI, raw_ostream &O) {660 const MCOperand &Op = MI->getOperand(OpNo);661 if (Op.isReg()) {662 MCRegister Reg = Op.getReg();663 if (!ShowVSRNumsAsVR)664 Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo);665 666 const char *RegName;667 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));668 if (RegName == nullptr)669 RegName = getRegisterName(Reg);670 if (showRegistersWithPercentPrefix(RegName))671 O << "%";672 if (!showRegistersWithPrefix())673 RegName = PPC::stripRegisterPrefix(RegName);674 675 O << RegName;676 return;677 }678 679 if (Op.isImm()) {680 O << Op.getImm();681 return;682 }683 684 assert(Op.isExpr() && "unknown operand kind in printOperand");685 MAI.printExpr(O, *Op.getExpr());686}687