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1//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides PowerPC specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H14#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H15 16// GCC #defines PPC on Linux but we use it as our namespace name17#undef PPC18 19#include "llvm/MC/MCRegisterInfo.h"20#include "llvm/Support/MathExtras.h"21#include <cstdint>22#include <memory>23 24namespace llvm {25 26class MCAsmBackend;27class MCCodeEmitter;28class MCContext;29class MCInstrDesc;30class MCInstrInfo;31class MCObjectTargetWriter;32class MCRegisterInfo;33class MCSubtargetInfo;34class MCTargetOptions;35class Target;36 37namespace PPC {38/// stripRegisterPrefix - This method strips the character prefix from a39/// register name so that only the number is left. Used by for linux asm.40const char *stripRegisterPrefix(const char *RegName);41 42/// getRegNumForOperand - some operands use different numbering schemes43/// for the same registers. For example, a VSX instruction may have any of44/// vs0-vs63 allocated whereas an Altivec instruction could only have45/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual46/// register number needed for the opcode/operand number combination.47/// The operand number argument will be useful when we need to extend this48/// to instructions that use both Altivec and VSX numbering (for different49/// operands).50MCRegister getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg,51 unsigned OpNo);52 53} // namespace PPC54 55MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,56 MCContext &Ctx);57 58MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,59 const MCRegisterInfo &MRI,60 const MCTargetOptions &Options);61 62/// Construct an PPC ELF object writer.63std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,64 uint8_t OSABI);65/// Construct a PPC Mach-O object writer.66std::unique_ptr<MCObjectTargetWriter>67createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);68 69/// Construct a PPC XCOFF object writer.70std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);71 72/// Returns true iff Val consists of one contiguous run of 1s with any number of73/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so74/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,75/// since all 1s are not contiguous.76static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {77 if (!Val)78 return false;79 80 if (isShiftedMask_32(Val)) {81 // look for the first non-zero bit82 MB = llvm::countl_zero(Val);83 // look for the first zero bit after the run of ones84 ME = llvm::countl_zero((Val - 1) ^ Val);85 return true;86 } else {87 Val = ~Val; // invert mask88 if (isShiftedMask_32(Val)) {89 // effectively look for the first zero bit90 ME = llvm::countl_zero(Val) - 1;91 // effectively look for the first one bit after the run of zeros92 MB = llvm::countl_zero((Val - 1) ^ Val) + 1;93 return true;94 }95 }96 // no run present97 return false;98}99 100static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {101 if (!Val)102 return false;103 104 if (isShiftedMask_64(Val)) {105 // look for the first non-zero bit106 MB = llvm::countl_zero(Val);107 // look for the first zero bit after the run of ones108 ME = llvm::countl_zero((Val - 1) ^ Val);109 return true;110 } else {111 Val = ~Val; // invert mask112 if (isShiftedMask_64(Val)) {113 // effectively look for the first zero bit114 ME = llvm::countl_zero(Val) - 1;115 // effectively look for the first one bit after the run of zeros116 MB = llvm::countl_zero((Val - 1) ^ Val) + 1;117 return true;118 }119 }120 // no run present121 return false;122}123 124/// PPCII - This namespace holds all of the PowerPC target-specific125/// per-instruction flags. These must match the corresponding definitions in126/// PPC.td and PPCInstrFormats.td.127namespace PPCII {128enum {129 // PPC970 Instruction Flags. These flags describe the characteristics of the130 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of131 // raw machine instructions.132 133 /// PPC970_First - This instruction starts a new dispatch group, so it will134 /// always be the first one in the group.135 PPC970_First = 0x1,136 137 /// PPC970_Single - This instruction starts a new dispatch group and138 /// terminates it, so it will be the sole instruction in the group.139 PPC970_Single = 0x2,140 141 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring142 /// two dispatch pipes to be available to issue.143 PPC970_Cracked = 0x4,144 145 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that146 /// an instruction is issued to.147 PPC970_Shift = 3,148 PPC970_Mask = 0x07 << PPC970_Shift149};150enum PPC970_Unit {151 /// These are the various PPC970 execution unit pipelines. Each instruction152 /// is one of these.153 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction154 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit155 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit156 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit157 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit158 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU159 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit160 PPC970_BRU = 7 << PPC970_Shift // Branch Unit161};162 163enum {164 /// Shift count to bypass PPC970 flags165 NewDef_Shift = 6,166 167 /// This instruction is an X-Form memory operation.168 XFormMemOp = 0x1 << NewDef_Shift,169 /// This instruction is prefixed.170 Prefixed = 0x1 << (NewDef_Shift + 1),171 /// This instruction produced a sign extended result.172 SExt32To64 = 0x1 << (NewDef_Shift + 2),173 /// This instruction produced a zero extended result.174 ZExt32To64 = 0x1 << (NewDef_Shift + 3),175 /// This instruction takes a register+immediate memory operand.176 MemriOp = 0x1 << (NewDef_Shift + 4)177};178} // end namespace PPCII179 180} // end namespace llvm181 182// Defines symbolic names for PowerPC registers. This defines a mapping from183// register name to register number.184//185#define GET_REGINFO_ENUM186#include "PPCGenRegisterInfo.inc"187 188// Defines symbolic names for the PowerPC instructions.189//190#define GET_INSTRINFO_ENUM191#define GET_INSTRINFO_SCHED_ENUM192#define GET_INSTRINFO_MC_HELPER_DECLS193#include "PPCGenInstrInfo.inc"194 195#define GET_SUBTARGETINFO_ENUM196#include "PPCGenSubtargetInfo.inc"197 198#define PPC_REGS0_7(X) \199 { \200 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \201 }202 203#define PPC_REGS0_31(X) \204 { \205 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \206 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \207 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \208 }209 210#define PPC_REGS_EVEN0_30(X) \211 { \212 X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, X##18, X##20, \213 X##22, X##24, X##26, X##28, X##30 \214 }215 216#define PPC_REGS0_63(X) \217 { \218 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \219 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \220 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \221 X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \222 X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \223 X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \224 X##62, X##63 \225 }226 227#define PPC_REGS_NO0_31(Z, X) \228 { \229 Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \230 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \231 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \232 }233 234#define PPC_REGS_LO_HI(LO, HI) \235 { \236 LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \237 LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \238 LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \239 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \240 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \241 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \242 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \243 HI##28, HI##29, HI##30, HI##31 \244 }245 246#define PPC_REGS0_7(X) \247 { \248 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \249 }250 251#define PPC_REGS0_3(X) \252 { \253 X##0, X##1, X##2, X##3 \254 }255 256using llvm::MCPhysReg;257 258#define DEFINE_PPC_REGCLASSES \259 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \260 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \261 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \262 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \263 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \264 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \265 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \266 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \267 static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \268 static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \269 static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V); \270 static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \271 static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \272 static const MCPhysReg CRBITRegs[32] = { \273 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, \274 PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \275 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, \276 PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \277 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, \278 PPC::CR7EQ, PPC::CR7UN}; \279 static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \280 static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \281 static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \282 static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \283 static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \284 static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \285 static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \286 static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);287 288namespace llvm {289namespace PPC {290static inline bool isVFRegister(MCRegister Reg) {291 return Reg >= PPC::VF0 && Reg <= PPC::VF31;292}293 294static inline bool isVRRegister(MCRegister Reg) {295 return Reg >= PPC::V0 && Reg <= PPC::V31;296}297 298static inline bool isDMRROWpRegister(unsigned Reg) {299 return Reg >= PPC::DMRROWp0 && Reg <= PPC::DMRROWp31;300}301} // namespace PPC302} // namespace llvm303 304#endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H305