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1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This is the top level entry point for the PowerPC target.10//11//===----------------------------------------------------------------------===//12 13// Get the target-independent interfaces which we are implementing.14//15include "llvm/Target/Target.td"16 17//===----------------------------------------------------------------------===//18// PowerPC Subtarget features.19//20 21//===----------------------------------------------------------------------===//22// CPU Directives //23//===----------------------------------------------------------------------===//24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;37def DirectiveE500 : SubtargetFeature<"", "CPUDirective",38 "PPC::DIR_E500", "">;39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",40 "PPC::DIR_E500mc", "">;41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective",42 "PPC::DIR_E5500", "">;43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;46def DirectivePwr5x47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;49def DirectivePwr6x50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;55def DirectivePwr11: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR11", "">;56def DirectivePwrFuture57 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;58 59// Specifies that the selected CPU supports 64-bit instructions, regardless of60// whether we are in 32-bit or 64-bit mode.61def Feature64BitSupport : SubtargetFeature<"64bit-support", "Has64BitSupport", "true",62 "Supports 64-bit instructions">;63// 64-bit is enabled.64def Feature64Bit : SubtargetFeature<"64bit", "IsPPC64", "true",65 "Enable 64-bit mode",66 [Feature64BitSupport]>;67 68def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;69def FeatureModernAIXAs70 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",71 "AIX system assembler is modern enough to support new mnes">;72def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",73 "Enable floating-point instructions">;74 75// Specifies that we are in 64-bit mode or that we should use 64-bit registers76// in 32-bit mode when possible. Requires Feature64Bit to be enabled.77def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",78 "Enable 64-bit registers usage for ppc32 [beta]">;79 80// Specify if we should store and manipulate i1 values in the individual81// condition register bits.82def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",83 "Use condition-register bits individually">;84def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",85 "Enable classic FPU instructions",86 [FeatureHardFloat]>;87def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",88 "Enable Altivec instructions",89 [FeatureFPU]>;90def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",91 "Enable SPE instructions",92 [FeatureHardFloat]>;93def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",94 "Enable Embedded Floating-Point APU 2 instructions",95 [FeatureSPE]>;96def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",97 "Enable the MFOCRF instruction">;98def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",99 "Enable the fsqrt instruction",100 [FeatureFPU]>;101def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",102 "Enable the fcpsgn instruction",103 [FeatureFPU]>;104def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",105 "Enable the fre instruction",106 [FeatureFPU]>;107def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",108 "Enable the fres instruction",109 [FeatureFPU]>;110def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",111 "Enable the frsqrte instruction",112 [FeatureFPU]>;113def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",114 "Enable the frsqrtes instruction",115 [FeatureFPU]>;116def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",117 "Assume higher precision reciprocal estimates">;118def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",119 "Enable the stfiwx instruction",120 [FeatureFPU]>;121def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",122 "Enable the lfiwax instruction",123 [FeatureFPU]>;124def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",125 "Enable the fri[mnpz] instructions",126 [FeatureFPU]>;127def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",128 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",129 [FeatureFPU]>;130def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",131 "Enable the isel instruction">;132def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",133 "Enable the bpermd instruction">;134def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",135 "Enable extended divide instructions">;136def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",137 "Enable the ldbrx instruction">;138def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",139 "Enable the cmpb instruction">;140def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",141 "Enable icbt instruction">;142def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",143 "Enable Book E instructions",144 [FeatureICBT]>;145def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",146 "Has only the msync instruction instead of sync",147 [FeatureBookE]>;148def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",149 "Enable E500/E500mc instructions">;150def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",151 "Enable secure plt mode">;152def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",153 "Enable PPC 4xx instructions">;154def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",155 "Enable PPC 6xx instructions">;156def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",157 "Enable VSX instructions",158 [FeatureAltivec]>;159def FeatureTwoConstNR :160 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",161 "Requires two constant Newton-Raphson computation">;162def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",163 "Enable POWER8 Altivec instructions",164 [FeatureAltivec]>;165def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",166 "Enable POWER8 Crypto instructions",167 [FeatureP8Altivec]>;168def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",169 "Enable POWER8 vector instructions",170 [FeatureVSX, FeatureP8Altivec]>;171def FeatureDirectMove :172 SubtargetFeature<"direct-move", "HasDirectMove", "true",173 "Enable Power8 direct move instructions",174 [FeatureVSX]>;175def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",176 "HasPartwordAtomics", "true",177 "Enable l[bh]arx and st[bh]cx.">;178def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",179 "HasQuadwordAtomics", "true",180 "Enable lqarx and stqcx.">;181def FeatureInvariantFunctionDescriptors :182 SubtargetFeature<"invariant-function-descriptors",183 "HasInvariantFunctionDescriptors", "true",184 "Assume function descriptors are invariant">;185def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",186 "Always use indirect calls">;187def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",188 "Enable Hardware Transactional Memory instructions">;189def FeatureMFTB : SubtargetFeature<"", "IsFeatureMFTB", "true",190 "Implement mftb using the mfspr instruction">;191def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",192 "Target supports instruction fusion">;193def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",194 "HasAddiLoadFusion", "true",195 "Power8 Addi-Load fusion",196 [FeatureFusion]>;197def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",198 "HasAddisLoadFusion", "true",199 "Power8 Addis-Load fusion",200 [FeatureFusion]>;201def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",202 "Target supports store clustering",203 [FeatureFusion]>;204def FeatureArithAddFusion :205 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",206 "Target supports Arithmetic Operations with Add fusion",207 [FeatureFusion]>;208def FeatureAddLogicalFusion :209 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",210 "Target supports Add with Logical Operations fusion",211 [FeatureFusion]>;212def FeatureLogicalAddFusion :213 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",214 "Target supports Logical with Add Operations fusion",215 [FeatureFusion]>;216def FeatureLogicalFusion :217 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",218 "Target supports Logical Operations fusion",219 [FeatureFusion]>;220def FeatureSha3Fusion :221 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",222 "Target supports SHA3 assist fusion",223 [FeatureFusion]>;224def FeatureCompareFusion:225 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",226 "Target supports Comparison Operations fusion",227 [FeatureFusion]>;228def FeatureWideImmFusion:229 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",230 "Target supports Wide-Immediate fusion",231 [FeatureFusion]>;232def FeatureZeroMoveFusion:233 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",234 "Target supports move to SPR with branch fusion",235 [FeatureFusion]>;236def FeatureBack2BackFusion:237 SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",238 "Target supports general back to back fusion",239 [FeatureFusion]>;240def FeatureUnalignedFloats :241 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",242 "true", "CPU does not trap on unaligned FP access">;243def FeaturePPCPreRASched:244 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",245 "Use PowerPC pre-RA scheduling strategy">;246def FeaturePPCPostRASched:247 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",248 "Use PowerPC post-RA scheduling strategy">;249def FeatureFloat128 :250 SubtargetFeature<"float128", "HasFloat128", "true",251 "Enable the __float128 data type for IEEE-754R Binary128.",252 [FeatureVSX]>;253def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD",254 "POPCNTD_Fast",255 "Enable the popcnt[dw] instructions">;256// Note that for the a2 processor models we should not use popcnt[dw] by257// default. These processors do support the instructions, but they're258// microcoded, and the software emulation is about twice as fast.259def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",260 "POPCNTD_Slow",261 "Has slow popcnt[dw] instructions">;262 263def DeprecatedDST : SubtargetFeature<"", "IsDeprecatedDST", "true",264 "Treat vector data stream cache control instructions as deprecated">;265 266def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",267 "true",268 "Enable instructions in ISA 2.06.">;269def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",270 "true",271 "Enable instructions in ISA 2.07.">;272def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",273 "true",274 "Enable instructions in ISA 3.0.",275 [FeatureISA2_07]>;276def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",277 "true",278 "Enable instructions in ISA 3.1.",279 [FeatureISA3_0]>;280def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",281 "IsISAFuture", "true",282 "Enable instructions for Future ISA.",283 [FeatureISA3_1]>;284def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",285 "Enable POWER9 Altivec instructions",286 [FeatureISA3_0, FeatureP8Altivec]>;287def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",288 "Enable POWER9 vector instructions",289 [FeatureISA3_0, FeatureP8Vector,290 FeatureP9Altivec]>;291def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector",292 "true",293 "Enable POWER10 vector instructions",294 [FeatureISA3_1, FeatureP9Vector]>;295// A separate feature for this even though it is equivalent to P9Vector296// because this is a feature of the implementation rather than the architecture297// and may go away with future CPU's.298def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",299 "VectorsUseTwoUnits",300 "true",301 "Vectors use two units">;302def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",303 "true",304 "Enable prefixed instructions",305 [FeatureISA3_1]>;306def FeaturePCRelativeMemops :307 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",308 "Enable PC relative Memory Ops",309 [FeatureISA3_0, FeaturePrefixInstrs]>;310def FeaturePairedVectorMemops:311 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",312 "32Byte load and store instructions",313 [FeatureISA3_0]>;314def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",315 "Enable MMA instructions",316 [FeatureP8Vector, FeatureP9Altivec,317 FeaturePairedVectorMemops]>;318def FeatureROPProtect :319 SubtargetFeature<"rop-protect", "HasROPProtect", "true",320 "Add ROP protect">;321 322def FeaturePrivileged :323 SubtargetFeature<"privileged", "HasPrivileged", "true",324 "Add privileged instructions">;325 326// Specifies that local-exec TLS accesses in any function with this target327// attribute should use the optimized TOC-free sequence (where the offset is an328// immediate off of R13 for which the linker might add fix-up code if the329// immediate is too large).330// Clearly, this isn't really a feature of the subtarget, but is used as a331// convenient way to affect code generation for individual functions.332def FeatureAIXLocalExecTLS :333 SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true",334 "Produce a TOC-free local-exec TLS sequence for this function "335 "for 64-bit AIX">;336 337// Specifies that local-dynamic TLS accesses in any function with this target338// attribute should use the optimized sequence (where the offset is an immediate339// off the module-handle for which the linker might add fix-up code for if the340// immediate is too large).341def FeatureAIXLocalDynamicTLS :342 SubtargetFeature<"aix-small-local-dynamic-tls", "HasAIXSmallLocalDynamicTLS",343 "true", "Produce a faster local-dynamic TLS sequence for this "344 "function for 64-bit AIX">;345 346def FeatureAIXSharedLibTLSModelOpt :347 SubtargetFeature<"aix-shared-lib-tls-model-opt",348 "HasAIXShLibTLSModelOpt", "true",349 "Tune TLS model at function level in shared library loaded "350 "with the main program (for 64-bit AIX only)">;351 352def FeaturePredictableSelectIsExpensive :353 SubtargetFeature<"predictable-select-expensive",354 "PredictableSelectIsExpensive",355 "true",356 "Prefer likely predicted branches over selects">;357 358def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",359 "MFLR is a fast instruction">;360 361//===----------------------------------------------------------------------===//362// PowerPC Instruction Predicate Definitions.363 364def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;365def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;366def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;367def IsPPC64 : Predicate<"Subtarget->isPPC64()">;368def IsBookE : Predicate<"Subtarget->isBookE()">;369def IsNotBookE : Predicate<"!Subtarget->isBookE()">;370def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;371def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">;372def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">;373def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">;374def IsE500 : Predicate<"Subtarget->isE500()">;375def HasSPE : Predicate<"Subtarget->hasSPE()">;376def HasICBT : Predicate<"Subtarget->hasICBT()">;377def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;378def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">;379def NoNaNsFPMath380 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;381def NaNsFPMath382 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;383def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;384def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;385def HasFPU : Predicate<"Subtarget->hasFPU()">;386def HasHTM : Predicate<"Subtarget->hasHTM()">;387def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;388def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;389def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;390def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;391def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;392def MMA : Predicate<"Subtarget->hasMMA()">;393 394// Vector support predicates395def HasVSX : Predicate<"Subtarget->hasVSX()">;396def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">;397def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;398def HasAltivec : Predicate<"Subtarget->hasAltivec()">;399def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;400def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;401def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;402def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;403def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;404def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;405def NoP10Vector : Predicate<"!Subtarget->hasP10Vector()">;406def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">;407 408// Predicates used to differenciate between different ISAs.409def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;410def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;411def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;412def IsNotISA3_0 : Predicate<"!Subtarget->isISA3_0()">;413def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;414def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;415def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;416def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;417 418// AIX assembler may not be modern enough to support some extended mne.419def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,420 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;421def IsAIX : Predicate<"Subtarget->isAIXABI()">;422def NotAIX : Predicate<"!Subtarget->isAIXABI()">;423 424//===----------------------------------------------------------------------===//425// HwModes426//===----------------------------------------------------------------------===//427 428defvar PPC32 = DefaultMode;429def PPC64 : HwMode<[IsPPC64]>;430 431// Since new processors generally contain a superset of features of those that432// came before them, the idea is to make implementations of new processors433// less error prone and easier to read.434// Namely:435// list<SubtargetFeature> P8InheritableFeatures = ...436// list<SubtargetFeature> FutureProcessorAddtionalFeatures =437// [ features that Power8 does not support but inheritable ]438// list<SubtargetFeature> FutureProcessorSpecificFeatures =439// [ features that Power8 does not support and not inheritable ]440// list<SubtargetFeature> FutureProcessorInheritableFeatures =441// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)442// list<SubtargetFeature> FutureProcessorFeatures =443// !listconcat(FutureProcessorInheritableFeatures,444// FutureProcessorSpecificFeatures)445 446// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as447// well as providing a single point of definition if the feature set will be448// used elsewhere.449def ProcessorFeatures {450 // Power7451 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,452 FeatureAltivec,453 FeatureVSX,454 FeatureMFOCRF,455 FeatureFCPSGN,456 FeatureFSqrt,457 FeatureFRE,458 FeatureFRES,459 FeatureFRSQRTE,460 FeatureFRSQRTES,461 FeatureRecipPrec,462 FeatureSTFIWX,463 FeatureLFIWAX,464 FeatureFPRND,465 FeatureFPCVT,466 FeatureISEL,467 FeaturePOPCNTD,468 FeatureCMPB,469 FeatureLDBRX,470 Feature64BitSupport,471 /* Feature64BitRegs, */472 FeatureBPERMD,473 FeatureExtDiv,474 FeatureMFTB,475 DeprecatedDST,476 FeatureTwoConstNR,477 FeatureUnalignedFloats,478 FeatureISA2_06];479 list<SubtargetFeature> P7SpecificFeatures = [];480 list<SubtargetFeature> P7Features =481 !listconcat(P7InheritableFeatures, P7SpecificFeatures);482 483 // Power8484 list<SubtargetFeature> P8AdditionalFeatures =485 [DirectivePwr8,486 FeatureP8Altivec,487 FeatureP8Vector,488 FeatureP8Crypto,489 FeatureDirectMove,490 FeatureICBT,491 FeaturePartwordAtomic,492 FeatureQuadwordAtomic,493 FeaturePredictableSelectIsExpensive,494 FeatureISA2_07,495 FeatureCRBits496 ];497 498 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,499 FeatureHTM,500 FeatureAddisLoadFusion];501 list<SubtargetFeature> P8InheritableFeatures =502 !listconcat(P7InheritableFeatures, P8AdditionalFeatures);503 list<SubtargetFeature> P8Features =504 !listconcat(P8InheritableFeatures, P8SpecificFeatures);505 506 // Power9507 list<SubtargetFeature> P9AdditionalFeatures =508 [DirectivePwr9,509 FeatureP9Altivec,510 FeatureP9Vector,511 FeaturePPCPreRASched,512 FeaturePPCPostRASched,513 FeatureISA3_0514 ];515 516 // Some features are unique to Power9 and there is no reason to assume517 // they will be part of any future CPUs. One example is the narrower518 // dispatch for vector operations than scalar ones. For the time being,519 // this list also includes scheduling-related features since we do not have520 // enough info to create custom scheduling strategies for future CPUs.521 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, FeatureHTM];522 list<SubtargetFeature> P9InheritableFeatures =523 !listconcat(P8InheritableFeatures, P9AdditionalFeatures);524 list<SubtargetFeature> P9Features =525 !listconcat(P9InheritableFeatures, P9SpecificFeatures);526 527 // Power10528 // For P10 CPU we assume that all of the existing features from Power9529 // still exist with the exception of those we know are Power9 specific.530 list<SubtargetFeature> FusionFeatures = [531 FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,532 FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,533 ];534 list<SubtargetFeature> P10AdditionalFeatures =535 !listconcat(FusionFeatures, [536 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,537 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,538 FeaturePairedVectorMemops, FeatureFastMFLR]);539 list<SubtargetFeature> P10SpecificFeatures = [];540 list<SubtargetFeature> P10InheritableFeatures =541 !listconcat(P9InheritableFeatures, P10AdditionalFeatures);542 list<SubtargetFeature> P10Features =543 !listconcat(P10InheritableFeatures, P10SpecificFeatures);544 545 // Power11546 // For P11 CPU we assume that all the existing features from Power10547 // still exist with the exception of those we know are Power10 specific.548 list<SubtargetFeature> P11AdditionalFeatures =549 [DirectivePwr11];550 list<SubtargetFeature> P11SpecificFeatures =551 [];552 list<SubtargetFeature> P11InheritableFeatures =553 !listconcat(P10InheritableFeatures, P11AdditionalFeatures);554 list<SubtargetFeature> P11Features =555 !listconcat(P11InheritableFeatures, P11SpecificFeatures);556 557 // Future558 // For future CPU we assume that all of the existing features from Power11559 // still exist with the exception of those we know are Power11 specific.560 list<SubtargetFeature> FutureAdditionalFeatures = [DirectivePwrFuture,561 FeatureISAFuture];562 list<SubtargetFeature> FutureSpecificFeatures = [];563 list<SubtargetFeature> FutureInheritableFeatures =564 !listconcat(P11InheritableFeatures, FutureAdditionalFeatures);565 list<SubtargetFeature> FutureFeatures =566 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);567}568 569// Note: Future features to add when support is extended to more570// recent ISA levels:571//572// DFP p6, p6x, p7 decimal floating-point instructions573// POPCNTB p5 through p7 popcntb and related instructions574 575//===----------------------------------------------------------------------===//576// Classes used for relation maps.577//===----------------------------------------------------------------------===//578// RecFormRel - Filter class used to relate non-record-form instructions with579// their record-form variants.580class RecFormRel;581 582// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX583// FMA instruction forms with their corresponding factor-killing forms.584class AltVSXFMARel {585 bit IsVSXFMAAlt = 0;586}587 588//===----------------------------------------------------------------------===//589// Relation Map Definitions.590//===----------------------------------------------------------------------===//591 592def getRecordFormOpcode : InstrMapping {593 let FilterClass = "RecFormRel";594 // Instructions with the same BaseName and Interpretation64Bit values595 // form a row.596 let RowFields = ["BaseName", "Interpretation64Bit"];597 // Instructions with the same RC value form a column.598 let ColFields = ["RC"];599 // The key column are the non-record-form instructions.600 let KeyCol = ["0"];601 // Value columns RC=1602 let ValueCols = [["1"]];603}604 605def getNonRecordFormOpcode : InstrMapping {606 let FilterClass = "RecFormRel";607 // Instructions with the same BaseName and Interpretation64Bit values608 // form a row.609 let RowFields = ["BaseName", "Interpretation64Bit"];610 // Instructions with the same RC value form a column.611 let ColFields = ["RC"];612 // The key column are the record-form instructions.613 let KeyCol = ["1"];614 // Value columns are RC=0615 let ValueCols = [["0"]];616}617 618def getAltVSXFMAOpcode : InstrMapping {619 let FilterClass = "AltVSXFMARel";620 // Instructions with the same BaseName value form a row.621 let RowFields = ["BaseName"];622 // Instructions with the same IsVSXFMAAlt value form a column.623 let ColFields = ["IsVSXFMAAlt"];624 // The key column are the (default) addend-killing instructions.625 let KeyCol = ["0"];626 // Value columns IsVSXFMAAlt=1627 let ValueCols = [["1"]];628}629 630def get64BitInstrFromSignedExt32BitInstr : InstrMapping {631 let FilterClass = "SExt32To64";632 // Instructions with the same opcode.633 let RowFields = ["Inst"];634 // Instructions with the same Interpretation64Bit value form a column.635 let ColFields = ["Interpretation64Bit"];636 // The key column are not the Interpretation64Bit-form instructions.637 let KeyCol = ["0"];638 // Value columns are the Interpretation64Bit-form instructions.639 let ValueCols = [["1"]];640}641 642//===----------------------------------------------------------------------===//643// Register File Description644//===----------------------------------------------------------------------===//645 646include "PPCRegisterInfo.td"647include "PPCSchedule.td"648include "GISel/PPCRegisterBanks.td"649 650//===----------------------------------------------------------------------===//651// PowerPC processors supported.652//653 654def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,655 FeatureMFTB]>;656def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,657 FeatureFRES, FeatureFRSQRTE,658 FeatureICBT, FeatureBookE,659 FeatureMSYNC, FeatureMFTB]>;660def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,661 FeatureFRES, FeatureFRSQRTE,662 FeatureICBT, FeatureBookE,663 FeatureMSYNC, FeatureMFTB]>;664def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;665def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,666 FeatureMFTB]>;667def : Processor<"603", G3Itineraries, [Directive603,668 FeatureFRES, FeatureFRSQRTE,669 FeatureMFTB]>;670def : Processor<"603e", G3Itineraries, [Directive603,671 FeatureFRES, FeatureFRSQRTE,672 FeatureMFTB]>;673def : Processor<"603ev", G3Itineraries, [Directive603,674 FeatureFRES, FeatureFRSQRTE,675 FeatureMFTB]>;676def : Processor<"604", G3Itineraries, [Directive604,677 FeatureFRES, FeatureFRSQRTE,678 FeatureMFTB]>;679def : Processor<"604e", G3Itineraries, [Directive604,680 FeatureFRES, FeatureFRSQRTE,681 FeatureMFTB]>;682def : Processor<"620", G3Itineraries, [Directive620,683 FeatureFRES, FeatureFRSQRTE,684 FeatureMFTB]>;685def : Processor<"750", G4Itineraries, [Directive750,686 FeatureFRES, FeatureFRSQRTE,687 FeatureMFTB]>;688def : Processor<"g3", G3Itineraries, [Directive750,689 FeatureFRES, FeatureFRSQRTE,690 FeatureMFTB]>;691def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,692 FeatureFRES, FeatureFRSQRTE,693 FeatureMFTB]>;694def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,695 FeatureFRES, FeatureFRSQRTE,696 FeatureMFTB]>;697def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,698 FeatureFRES, FeatureFRSQRTE,699 FeatureMFTB]>;700def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,701 FeatureFRES, FeatureFRSQRTE,702 FeatureMFTB]>;703 704def : ProcessorModel<"970", G5Model,705 [Directive970, FeatureAltivec,706 FeatureMFOCRF, FeatureFSqrt,707 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,708 Feature64BitSupport /*, Feature64BitRegs */,709 FeatureMFTB]>;710def : ProcessorModel<"g5", G5Model,711 [Directive970, FeatureAltivec,712 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,713 FeatureFRES, FeatureFRSQRTE,714 Feature64BitSupport /*, Feature64BitRegs */,715 FeatureMFTB, DeprecatedDST]>;716def : ProcessorModel<"e500", PPCE500Model,717 [DirectiveE500,718 FeatureICBT, FeatureBookE,719 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;720def : ProcessorModel<"e500mc", PPCE500mcModel,721 [DirectiveE500mc,722 FeatureSTFIWX, FeatureICBT, FeatureBookE,723 FeatureISEL, FeatureMFTB]>;724def : ProcessorModel<"e5500", PPCE5500Model,725 [DirectiveE5500, FeatureMFOCRF, Feature64BitSupport,726 FeatureSTFIWX, FeatureICBT, FeatureBookE,727 FeatureISEL, FeatureMFTB]>;728def : ProcessorModel<"a2", PPCA2Model,729 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,730 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,731 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,732 FeatureSTFIWX, FeatureLFIWAX,733 FeatureFPRND, FeatureFPCVT, FeatureISEL,734 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,735 Feature64BitSupport /*, Feature64BitRegs */, FeatureMFTB,736 FeatureISA2_06]>;737def : ProcessorModel<"pwr3", G5Model,738 [DirectivePwr3, FeatureAltivec,739 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,740 FeatureSTFIWX, Feature64BitSupport]>;741def : ProcessorModel<"pwr4", G5Model,742 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,743 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,744 FeatureSTFIWX, Feature64BitSupport, FeatureMFTB]>;745def : ProcessorModel<"pwr5", G5Model,746 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,747 FeatureFSqrt, FeatureFRE, FeatureFRES,748 FeatureFRSQRTE, FeatureFRSQRTES,749 FeatureSTFIWX, Feature64BitSupport,750 FeatureMFTB, DeprecatedDST]>;751def : ProcessorModel<"pwr5x", G5Model,752 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,753 FeatureFSqrt, FeatureFRE, FeatureFRES,754 FeatureFRSQRTE, FeatureFRSQRTES,755 FeatureSTFIWX, FeatureFPRND, Feature64BitSupport,756 FeatureMFTB, DeprecatedDST]>;757def : ProcessorModel<"pwr6", G5Model,758 [DirectivePwr6, FeatureAltivec,759 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,760 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,761 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,762 FeatureFPRND, Feature64BitSupport /*, Feature64BitRegs */,763 FeatureMFTB, DeprecatedDST]>;764def : ProcessorModel<"pwr6x", G5Model,765 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,766 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,767 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,768 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,769 FeatureFPRND, Feature64BitSupport,770 FeatureMFTB, DeprecatedDST]>;771def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;772def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;773def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;774def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;775def : ProcessorModel<"pwr11", P10Model, ProcessorFeatures.P11Features>;776// No scheduler model for future CPU.777def : ProcessorModel<"future", NoSchedModel,778 ProcessorFeatures.FutureFeatures>;779def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,780 FeatureMFTB]>;781def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,782 FeatureMFTB]>;783def : ProcessorModel<"ppc64", G5Model,784 [Directive64, FeatureAltivec,785 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,786 FeatureFRSQRTE, FeatureSTFIWX,787 Feature64BitSupport /*, Feature64BitRegs */,788 FeatureMFTB]>;789def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;790 791//===----------------------------------------------------------------------===//792// Calling Conventions793//===----------------------------------------------------------------------===//794 795include "PPCCallingConv.td"796 797def PPCInstrInfo : InstrInfo {798 let isLittleEndianEncoding = 1;799}800 801def PPCAsmWriter : AsmWriter {802 string AsmWriterClassName = "InstPrinter";803 int PassSubtarget = 1;804 int Variant = 0;805 bit isMCAsmWriter = 1;806}807 808def PPCAsmParser : AsmParser {809 let ShouldEmitMatchRegisterName = 1;810 let AllowDuplicateRegisterNames = 1;811}812 813def PPCAsmParserVariant : AsmParserVariant {814 int Variant = 0;815 816 // We do not use hard coded registers in asm strings. However, some817 // InstAlias definitions use immediate literals. Set RegisterPrefix818 // so that those are not misinterpreted as registers.819 string RegisterPrefix = "%";820 string BreakCharacters = ".";821}822 823defm : RemapAllTargetPseudoPointerOperands<ppc_ptr_rc>;824 825def PPC : Target {826 // Information about the instructions.827 let InstructionSet = PPCInstrInfo;828 829 let AssemblyWriters = [PPCAsmWriter];830 let AssemblyParsers = [PPCAsmParser];831 let AssemblyParserVariants = [PPCAsmParserVariant];832 let AllowRegisterRenaming = 1;833}834 835//===----------------------------------------------------------------------===//836// Pfm Counters837//===----------------------------------------------------------------------===//838 839include "PPCPfmCounters.td"840