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1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This describes the calling conventions for the PowerPC 32- and 64-bit10// architectures.11//12//===----------------------------------------------------------------------===//13 14/// CCIfSubtarget - Match if the current subtarget has a feature F.15class CCIfSubtarget<string F, CCAction A>16 : CCIf<!strconcat("State.getMachineFunction().getSubtarget<PPCSubtarget>().",17 F),18 A>;19class CCIfNotSubtarget<string F, CCAction A>20 : CCIf<!strconcat("!State.getMachineFunction().getSubtarget<PPCSubtarget>().",21 F),22 A>;23class CCIfOrigArgWasNotPPCF128<CCAction A>24 : CCIf<"!OrigTy->isPPC_FP128Ty()", A>;25class CCIfOrigArgWasPPCF128<CCAction A>26 : CCIf<"OrigTy->isPPC_FP128Ty()", A>;27 28//===----------------------------------------------------------------------===//29// Return Value Calling Convention30//===----------------------------------------------------------------------===//31 32// PPC64 AnyReg return-value convention. No explicit register is specified for33// the return-value. The register allocator is allowed and expected to choose34// any free register.35//36// This calling convention is currently only supported by the stackmap and37// patchpoint intrinsics. All other uses will result in an assert on Debug38// builds. On Release builds we fallback to the PPC C calling convention.39def RetCC_PPC64_AnyReg : CallingConv<[40 CCCustom<"CC_PPC_AnyReg_Error">41]>;42 43// Return-value convention for PowerPC coldcc.44let Entry = 1 in45def RetCC_PPC_Cold : CallingConv<[46 // Use the same return registers as RetCC_PPC, but limited to only47 // one return value. The remaining return values will be saved to48 // the stack.49 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,50 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,51 52 CCIfType<[i32], CCAssignToReg<[R3]>>,53 CCIfType<[i64], CCAssignToReg<[X3]>>,54 CCIfType<[i128], CCAssignToReg<[X3]>>,55 56 CCIfType<[f32], CCAssignToReg<[F1]>>,57 CCIfType<[f64], CCAssignToReg<[F1]>>,58 CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2]>>>,59 60 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],61 CCIfSubtarget<"hasAltivec()",62 CCAssignToReg<[V2]>>>63]>;64 65// Return-value convention for PowerPC66let Entry = 1 in67def RetCC_PPC : CallingConv<[68 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,69 70 // On PPC64, integer return values are always promoted to i6471 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,72 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,73 74 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,75 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,76 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,77 78 // Floating point types returned as "direct" go into F1 .. F8; note that79 // only the ELFv2 ABI fully utilizes all these registers.80 CCIfNotSubtarget<"hasSPE()",81 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,82 CCIfNotSubtarget<"hasSPE()",83 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,84 CCIfSubtarget<"hasSPE()",85 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,86 CCIfSubtarget<"hasSPE()",87 CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>,88 89 // For P9, f128 are passed in vector registers.90 CCIfType<[f128],91 CCIfSubtarget<"hasAltivec()",92 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,93 94 // Vector types returned as "direct" go into V2 .. V9; note that only the95 // ELFv2 ABI fully utilizes all these registers.96 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],97 CCIfSubtarget<"hasAltivec()",98 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>99]>;100 101// No explicit register is specified for the AnyReg calling convention. The102// register allocator may assign the arguments to any free register.103//104// This calling convention is currently only supported by the stackmap and105// patchpoint intrinsics. All other uses will result in an assert on Debug106// builds. On Release builds we fallback to the PPC C calling convention.107def CC_PPC64_AnyReg : CallingConv<[108 CCCustom<"CC_PPC_AnyReg_Error">109]>;110 111// Calling Convention corresponding to the 64-bit PowerPC ELFv2 ABI.112// This calling convention currently only handles integers, floats and113// vectors within registers, as well as it handles the shadowing of GPRs114// when floating point and vector arguments are used.115// FIXME: This calling convention needs to be extended to handle all types and116// complexities of the ABI.117let Entry = 1 in118def CC_PPC64_ELF : CallingConv<[119 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,120 121 CCIfType<[i1], CCPromoteToType<i64>>,122 CCIfType<[i8], CCPromoteToType<i64>>,123 CCIfType<[i16], CCPromoteToType<i64>>,124 CCIfType<[i32], CCPromoteToType<i64>>,125 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,126 127 // Handle fp types and shadow the corresponding registers as necessary.128 CCIfType<[f32, f64], CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>,129 CCIfType<[f32, f64],130 CCIfNotVarArg<CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,131 F11, F12, F13]>>>,132 133 // f128 is handled through vector registers instead of fp registers.134 CCIfType<[f128],135 CCIfSubtarget<"hasAltivec()",136 CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>>,137 CCIfType<[f128],138 CCIfSubtarget<"hasAltivec()",139 CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,140 V11, V12, V13]>>>>,141 142 // Handle support for vector types, and shadow GPRs as necessary.143 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],144 CCIfSubtarget<"hasAltivec()",145 CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>>,146 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],147 CCIfSubtarget<"hasAltivec()",148 CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,149 V11, V12, V13]>>>>,150]>;151 152// Simple calling convention for 64-bit ELF PowerPC fast isel.153// Only handle ints and floats. All ints are promoted to i64.154// Vector types and quadword ints are not handled.155let Entry = 1 in156def CC_PPC64_ELF_FIS : CallingConv<[157 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,158 159 CCIfType<[i1], CCPromoteToType<i64>>,160 CCIfType<[i8], CCPromoteToType<i64>>,161 CCIfType<[i16], CCPromoteToType<i64>>,162 CCIfType<[i32], CCPromoteToType<i64>>,163 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,164 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>165]>;166 167// Simple return-value convention for 64-bit ELF PowerPC fast isel.168// All small ints are promoted to i64. Vector types, quadword ints,169// and multiple register returns are "supported" to avoid compile170// errors, but none are handled by the fast selector.171let Entry = 1 in172def RetCC_PPC64_ELF_FIS : CallingConv<[173 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,174 175 CCIfType<[i1], CCPromoteToType<i64>>,176 CCIfType<[i8], CCPromoteToType<i64>>,177 CCIfType<[i16], CCPromoteToType<i64>>,178 CCIfType<[i32], CCPromoteToType<i64>>,179 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,180 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,181 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,182 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,183 CCIfType<[f128],184 CCIfSubtarget<"hasAltivec()",185 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,186 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],187 CCIfSubtarget<"hasAltivec()",188 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>189]>;190 191//===----------------------------------------------------------------------===//192// PowerPC System V Release 4 32-bit ABI193//===----------------------------------------------------------------------===//194 195def CC_PPC32_SVR4_Common : CallingConv<[196 CCIfType<[i1], CCPromoteToType<i32>>,197 198 // The ABI requires i64 to be passed in two adjacent registers with the first199 // register having an odd register number.200 CCIfType<[i32],201 CCIfSplit<CCIfSubtarget<"useSoftFloat()", 202 CCIfOrigArgWasNotPPCF128<203 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>>,204 205 CCIfType<[i32],206 CCIfSplit<CCIfNotSubtarget<"useSoftFloat()", 207 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>,208 CCIfType<[f64],209 CCIfSubtarget<"hasSPE()",210 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,211 CCIfSplit<CCIfSubtarget<"useSoftFloat()",212 CCIfOrigArgWasPPCF128<CCCustom<213 "CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>,214 215 // The 'nest' parameter, if any, is passed in R11.216 CCIfNest<CCAssignToReg<[R11]>>,217 218 // The first 8 integer arguments are passed in integer registers.219 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,220 221 // Make sure the i64 words from a long double are either both passed in222 // registers or both passed on the stack.223 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,224 225 // FP values are passed in F1 - F8.226 CCIfType<[f32, f64],227 CCIfNotSubtarget<"hasSPE()",228 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,229 CCIfType<[f64],230 CCIfSubtarget<"hasSPE()",231 CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>,232 CCIfType<[f32],233 CCIfSubtarget<"hasSPE()",234 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,235 236 // Split arguments have an alignment of 8 bytes on the stack.237 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,238 239 CCIfType<[i32], CCAssignToStack<4, 4>>,240 241 CCIfType<[f32], CCAssignToStack<4, 4>>,242 CCIfType<[f64], CCAssignToStack<8, 8>>,243 244 // Vectors and float128 get 16-byte stack slots that are 16-byte aligned.245 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,246 CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToStack<16, 16>>>247]>;248 249// This calling convention puts vector arguments always on the stack. It is used250// to assign vector arguments which belong to the variable portion of the251// parameter list of a variable argument function.252let Entry = 1 in253def CC_PPC32_SVR4_VarArg : CallingConv<[254 CCDelegateTo<CC_PPC32_SVR4_Common>255]>;256 257// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to258// put vector arguments in vector registers before putting them on the stack.259let Entry = 1 in260def CC_PPC32_SVR4 : CallingConv<[261 // The first 12 Vector arguments are passed in AltiVec registers.262 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],263 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,264 V8, V9, V10, V11, V12, V13]>>>,265 266 // Float128 types treated as vector arguments.267 CCIfType<[f128],268 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,269 V8, V9, V10, V11, V12, V13]>>>,270 271 CCDelegateTo<CC_PPC32_SVR4_Common>272]>; 273 274// Helper "calling convention" to handle aggregate by value arguments.275// Aggregate by value arguments are always placed in the local variable space276// of the caller. This calling convention is only used to assign those stack277// offsets in the callers stack frame.278//279// Still, the address of the aggregate copy in the callers stack frame is passed280// in a GPR (or in the parameter list area if all GPRs are allocated) from the281// caller to the callee. The location for the address argument is assigned by282// the CC_PPC32_SVR4 calling convention.283//284// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are285// not passed by value.286 287let Entry = 1 in288def CC_PPC32_SVR4_ByVal : CallingConv<[289 CCIfByVal<CCPassByVal<4, 4>>,290 291 CCCustom<"CC_PPC32_SVR4_Custom_Dummy">292]>;293 294def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,295 V28, V29, V30, V31)>;296 297// SPE does not use FPRs, so break out the common register set as base.298def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,299 R21, R22, R23, R24, R25, R26, R27,300 R28, R29, R30, R31, CR2, CR3, CR4301 )>;302def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,303 F19, F20, F21, F22, F23, F24, F25, F26,304 F27, F28, F29, F30, F31305 )>;306def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,307 S23, S24, S25, S26, S27, S28, S29, S30 308 )>;309 310def CSR_SPE_NO_S30_31 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,311 S22, S23, S24, S25, S26, S27, S28, S29312 )>;313 314def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;315 316def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;317 318def CSR_SVR432_SPE_NO_S30_31 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30_31)>;319 320def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,321 R21, R22, R23, R24, R25, R26, R27, R28,322 R29, R30, R31, F14, F15, F16, F17, F18,323 F19, F20, F21, F22, F23, F24, F25, F26,324 F27, F28, F29, F30, F31, CR2, CR3, CR4325 )>;326 327def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;328 329// Common CalleeSavedRegs for SVR4 and AIX.330def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,331 X21, X22, X23, X24, X25, X26, X27, X28,332 X29, X30, X31, F14, F15, F16, F17, F18,333 F19, F20, F21, F22, F23, F24, F25, F26,334 F27, F28, F29, F30, F31, CR2, CR3, CR4335 )>;336 337 338def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>;339 340def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>;341 342def CSR_PPC64_R2_Altivec : CalleeSavedRegs<(add CSR_PPC64_Altivec, X2)>;343 344def CSR_NoRegs : CalleeSavedRegs<(add)>;345 346// coldcc calling convection marks most registers as non-volatile.347// Do not include r1 since the stack pointer is never considered a CSR.348// Do not include r2, since it is the TOC register and is added depending349// on whether or not the function uses the TOC and is a non-leaf.350// Do not include r0,r11,r13 as they are optional in functional linkage351// and value may be altered by inter-library calls.352// Do not include r12 as it is used as a scratch register.353// Do not include return registers r3, f1, v2.354def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),355 (sequence "R%u", 14, 31),356 (sequence "CR%u", 0, 7))>;357 358def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,359 F0, (sequence "F%u", 2, 31))>;360 361 362def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC,363 (sequence "V%u", 0, 1),364 (sequence "V%u", 3, 31))>;365 366def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,367 (sequence "S%u", 4, 10),368 (sequence "S%u", 14, 31))>;369 370def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10),371 (sequence "X%u", 14, 31),372 F0, (sequence "F%u", 2, 31),373 (sequence "CR%u", 0, 7))>;374 375def CSR_SVR64_ColdCC_R2: CalleeSavedRegs<(add CSR_SVR64_ColdCC, X2)>;376 377def CSR_SVR64_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC,378 (sequence "V%u", 0, 1),379 (sequence "V%u", 3, 31))>;380 381def CSR_SVR64_ColdCC_R2_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC_Altivec, X2)>;382 383def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),384 (sequence "X%u", 14, 31),385 (sequence "F%u", 0, 31),386 (sequence "CR%u", 0, 7))>;387 388def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,389 (sequence "V%u", 0, 31))>;390 391def CSR_64_AllRegs_AIX_Dflt_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,392 (sequence "V%u", 0, 19))>;393 394def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,395 (sequence "VSL%u", 0, 31))>;396 397def CSR_64_AllRegs_AIX_Dflt_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,398 (sequence "VSL%u", 0, 19))>;399 400def CSR_ALL_VSRP : CalleeSavedRegs<(sequence "VSRp%u", 0, 31)>;401 402def CSR_VSRP :403 CalleeSavedRegs<(add VSRp26, VSRp27, VSRp28, VSRp29, VSRp30, VSRp31)>;404 405def CSR_SVR432_VSRP : CalleeSavedRegs<(add CSR_SVR432_Altivec, CSR_VSRP)>;406 407def CSR_SVR464_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;408 409def CSR_SVR464_R2_VSRP : CalleeSavedRegs<(add CSR_SVR464_VSRP, X2)>;410 411def CSR_SVR32_ColdCC_VSRP : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Altivec,412 (sub CSR_ALL_VSRP, VSRp17))>;413 414def CSR_SVR64_ColdCC_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC,415 (sub CSR_ALL_VSRP, VSRp17))>;416 417def CSR_SVR64_ColdCC_R2_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC_VSRP, X2)>;418 419def CSR_64_AllRegs_VSRP :420 CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;421 422def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;423 424def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;425 426def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;427