2819 lines · cpp
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the PPC implementation of TargetFrameLowering class.10//11//===----------------------------------------------------------------------===//12 13#include "PPCFrameLowering.h"14#include "MCTargetDesc/PPCPredicates.h"15#include "PPCInstrBuilder.h"16#include "PPCInstrInfo.h"17#include "PPCMachineFunctionInfo.h"18#include "PPCSubtarget.h"19#include "PPCTargetMachine.h"20#include "llvm/ADT/Statistic.h"21#include "llvm/CodeGen/LivePhysRegs.h"22#include "llvm/CodeGen/MachineFrameInfo.h"23#include "llvm/CodeGen/MachineFunction.h"24#include "llvm/CodeGen/MachineInstrBuilder.h"25#include "llvm/CodeGen/MachineModuleInfo.h"26#include "llvm/CodeGen/MachineRegisterInfo.h"27#include "llvm/CodeGen/RegisterScavenging.h"28#include "llvm/IR/Function.h"29#include "llvm/Target/TargetOptions.h"30 31using namespace llvm;32 33#define DEBUG_TYPE "framelowering"34STATISTIC(NumPESpillVSR, "Number of spills to vector in prologue");35STATISTIC(NumPEReloadVSR, "Number of reloads from vector in epilogue");36STATISTIC(NumPrologProbed, "Number of prologues probed");37 38static cl::opt<bool>39EnablePEVectorSpills("ppc-enable-pe-vector-spills",40 cl::desc("Enable spills in prologue to vector registers."),41 cl::init(false), cl::Hidden);42 43static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {44 if (STI.isAIXABI())45 return STI.isPPC64() ? 16 : 8;46 // SVR4 ABI:47 return STI.isPPC64() ? 16 : 4;48}49 50static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {51 if (STI.isAIXABI())52 return STI.isPPC64() ? 40 : 20;53 return STI.isELFv2ABI() ? 24 : 40;54}55 56static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {57 // First slot in the general register save area.58 return STI.isPPC64() ? -8U : -4U;59}60 61static unsigned computeLinkageSize(const PPCSubtarget &STI) {62 if (STI.isAIXABI() || STI.isPPC64())63 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);64 65 // 32-bit SVR4 ABI:66 return 8;67}68 69static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {70 // Third slot in the general purpose register save area.71 if (STI.is32BitELFABI() && STI.getTargetMachine().isPositionIndependent())72 return -12U;73 74 // Second slot in the general purpose register save area.75 return STI.isPPC64() ? -16U : -8U;76}77 78static unsigned computeCRSaveOffset(const PPCSubtarget &STI) {79 return (STI.isAIXABI() && !STI.isPPC64()) ? 4 : 8;80}81 82PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)83 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,84 STI.getPlatformStackAlignment(), 0),85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),88 LinkageSize(computeLinkageSize(Subtarget)),89 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),90 CRSaveOffset(computeCRSaveOffset(Subtarget)) {}91 92// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.93const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(94 unsigned &NumEntries) const {95 96// Floating-point register save area offsets.97#define CALLEE_SAVED_FPRS \98 {PPC::F31, -8}, \99 {PPC::F30, -16}, \100 {PPC::F29, -24}, \101 {PPC::F28, -32}, \102 {PPC::F27, -40}, \103 {PPC::F26, -48}, \104 {PPC::F25, -56}, \105 {PPC::F24, -64}, \106 {PPC::F23, -72}, \107 {PPC::F22, -80}, \108 {PPC::F21, -88}, \109 {PPC::F20, -96}, \110 {PPC::F19, -104}, \111 {PPC::F18, -112}, \112 {PPC::F17, -120}, \113 {PPC::F16, -128}, \114 {PPC::F15, -136}, \115 {PPC::F14, -144}116 117// 32-bit general purpose register save area offsets shared by ELF and118// AIX. AIX has an extra CSR with r13.119#define CALLEE_SAVED_GPRS32 \120 {PPC::R31, -4}, \121 {PPC::R30, -8}, \122 {PPC::R29, -12}, \123 {PPC::R28, -16}, \124 {PPC::R27, -20}, \125 {PPC::R26, -24}, \126 {PPC::R25, -28}, \127 {PPC::R24, -32}, \128 {PPC::R23, -36}, \129 {PPC::R22, -40}, \130 {PPC::R21, -44}, \131 {PPC::R20, -48}, \132 {PPC::R19, -52}, \133 {PPC::R18, -56}, \134 {PPC::R17, -60}, \135 {PPC::R16, -64}, \136 {PPC::R15, -68}, \137 {PPC::R14, -72}138 139// 64-bit general purpose register save area offsets.140#define CALLEE_SAVED_GPRS64 \141 {PPC::X31, -8}, \142 {PPC::X30, -16}, \143 {PPC::X29, -24}, \144 {PPC::X28, -32}, \145 {PPC::X27, -40}, \146 {PPC::X26, -48}, \147 {PPC::X25, -56}, \148 {PPC::X24, -64}, \149 {PPC::X23, -72}, \150 {PPC::X22, -80}, \151 {PPC::X21, -88}, \152 {PPC::X20, -96}, \153 {PPC::X19, -104}, \154 {PPC::X18, -112}, \155 {PPC::X17, -120}, \156 {PPC::X16, -128}, \157 {PPC::X15, -136}, \158 {PPC::X14, -144}159 160// Vector register save area offsets.161#define CALLEE_SAVED_VRS \162 {PPC::V31, -16}, \163 {PPC::V30, -32}, \164 {PPC::V29, -48}, \165 {PPC::V28, -64}, \166 {PPC::V27, -80}, \167 {PPC::V26, -96}, \168 {PPC::V25, -112}, \169 {PPC::V24, -128}, \170 {PPC::V23, -144}, \171 {PPC::V22, -160}, \172 {PPC::V21, -176}, \173 {PPC::V20, -192}174 175 // Note that the offsets here overlap, but this is fixed up in176 // processFunctionBeforeFrameFinalized.177 178 static const SpillSlot ELFOffsets32[] = {179 CALLEE_SAVED_FPRS,180 CALLEE_SAVED_GPRS32,181 182 // CR save area offset. We map each of the nonvolatile CR fields183 // to the slot for CR2, which is the first of the nonvolatile CR184 // fields to be assigned, so that we only allocate one save slot.185 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.186 {PPC::CR2, -4},187 188 // VRSAVE save area offset.189 {PPC::VRSAVE, -4},190 191 CALLEE_SAVED_VRS,192 193 // SPE register save area (overlaps Vector save area).194 {PPC::S31, -8},195 {PPC::S30, -16},196 {PPC::S29, -24},197 {PPC::S28, -32},198 {PPC::S27, -40},199 {PPC::S26, -48},200 {PPC::S25, -56},201 {PPC::S24, -64},202 {PPC::S23, -72},203 {PPC::S22, -80},204 {PPC::S21, -88},205 {PPC::S20, -96},206 {PPC::S19, -104},207 {PPC::S18, -112},208 {PPC::S17, -120},209 {PPC::S16, -128},210 {PPC::S15, -136},211 {PPC::S14, -144}};212 213 static const SpillSlot ELFOffsets64[] = {214 CALLEE_SAVED_FPRS,215 CALLEE_SAVED_GPRS64,216 217 // VRSAVE save area offset.218 {PPC::VRSAVE, -4},219 CALLEE_SAVED_VRS220 };221 222 static const SpillSlot AIXOffsets32[] = {CALLEE_SAVED_FPRS,223 CALLEE_SAVED_GPRS32,224 // Add AIX's extra CSR.225 {PPC::R13, -76},226 CALLEE_SAVED_VRS};227 228 static const SpillSlot AIXOffsets64[] = {229 CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS};230 231 if (Subtarget.is64BitELFABI()) {232 NumEntries = std::size(ELFOffsets64);233 return ELFOffsets64;234 }235 236 if (Subtarget.is32BitELFABI()) {237 NumEntries = std::size(ELFOffsets32);238 return ELFOffsets32;239 }240 241 assert(Subtarget.isAIXABI() && "Unexpected ABI.");242 243 if (Subtarget.isPPC64()) {244 NumEntries = std::size(AIXOffsets64);245 return AIXOffsets64;246 }247 248 NumEntries = std::size(AIXOffsets32);249 return AIXOffsets32;250}251 252static bool spillsCR(const MachineFunction &MF) {253 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();254 return FuncInfo->isCRSpilled();255}256 257static bool hasSpills(const MachineFunction &MF) {258 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();259 return FuncInfo->hasSpills();260}261 262static bool hasNonRISpills(const MachineFunction &MF) {263 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();264 return FuncInfo->hasNonRISpills();265}266 267/// MustSaveLR - Return true if this function requires that we save the LR268/// register onto the stack in the prolog and restore it in the epilog of the269/// function.270static bool MustSaveLR(const MachineFunction &MF, MCRegister LR) {271 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();272 273 // We need a save/restore of LR if there is any def of LR (which is274 // defined by calls, including the PIC setup sequence), or if there is275 // some use of the LR stack slot (e.g. for builtin_return_address).276 // (LR comes in 32 and 64 bit versions.)277 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);278 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();279}280 281/// determineFrameLayoutAndUpdate - Determine the size of the frame and maximum282/// call frame size. Update the MachineFunction object with the stack size.283uint64_t284PPCFrameLowering::determineFrameLayoutAndUpdate(MachineFunction &MF,285 bool UseEstimate) const {286 unsigned NewMaxCallFrameSize = 0;287 uint64_t FrameSize = determineFrameLayout(MF, UseEstimate,288 &NewMaxCallFrameSize);289 MF.getFrameInfo().setStackSize(FrameSize);290 MF.getFrameInfo().setMaxCallFrameSize(NewMaxCallFrameSize);291 return FrameSize;292}293 294/// determineFrameLayout - Determine the size of the frame and maximum call295/// frame size.296uint64_t297PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,298 bool UseEstimate,299 unsigned *NewMaxCallFrameSize) const {300 const MachineFrameInfo &MFI = MF.getFrameInfo();301 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();302 303 // Get the number of bytes to allocate from the FrameInfo304 uint64_t FrameSize =305 UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();306 307 // Get stack alignments. The frame must be aligned to the greatest of these:308 Align TargetAlign = getStackAlign(); // alignment required per the ABI309 Align MaxAlign = MFI.getMaxAlign(); // algmt required by data in frame310 Align Alignment = std::max(TargetAlign, MaxAlign);311 312 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();313 314 MCRegister LR = RegInfo->getRARegister();315 bool DisableRedZone = MF.getFunction().hasFnAttribute(Attribute::NoRedZone);316 bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.317 !MFI.adjustsStack() && // No calls.318 !MustSaveLR(MF, LR) && // No need to save LR.319 !FI->mustSaveTOC() && // No need to save TOC.320 !RegInfo->hasBasePointer(MF) && // No special alignment.321 !MFI.isFrameAddressTaken();322 323 // Note: for PPC32 SVR4ABI, we can still generate stackless324 // code if all local vars are reg-allocated.325 bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize();326 327 // Check whether we can skip adjusting the stack pointer (by using red zone)328 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {329 // No need for frame330 return 0;331 }332 333 // Get the maximum call frame size of all the calls.334 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();335 336 // Maximum call frame needs to be at least big enough for linkage area.337 unsigned minCallFrameSize = getLinkageSize();338 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);339 340 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so341 // that allocations will be aligned.342 if (MFI.hasVarSizedObjects())343 maxCallFrameSize = alignTo(maxCallFrameSize, Alignment);344 345 // Update the new max call frame size if the caller passes in a valid pointer.346 if (NewMaxCallFrameSize)347 *NewMaxCallFrameSize = maxCallFrameSize;348 349 // Include call frame size in total.350 FrameSize += maxCallFrameSize;351 352 // Make sure the frame is aligned.353 FrameSize = alignTo(FrameSize, Alignment);354 355 return FrameSize;356}357 358// hasFPImpl - Return true if the specified function actually has a dedicated359// frame pointer register.360bool PPCFrameLowering::hasFPImpl(const MachineFunction &MF) const {361 const MachineFrameInfo &MFI = MF.getFrameInfo();362 // FIXME: This is pretty much broken by design: hasFP() might be called really363 // early, before the stack layout was calculated and thus hasFP() might return364 // true or false here depending on the time of call.365 return (MFI.getStackSize()) && needsFP(MF);366}367 368// needsFP - Return true if the specified function should have a dedicated frame369// pointer register. This is true if the function has variable sized allocas or370// if frame pointer elimination is disabled.371bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {372 const MachineFrameInfo &MFI = MF.getFrameInfo();373 374 // Naked functions have no stack frame pushed, so we don't have a frame375 // pointer.376 if (MF.getFunction().hasFnAttribute(Attribute::Naked))377 return false;378 379 return MF.getTarget().Options.DisableFramePointerElim(MF) ||380 MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||381 MF.exposesReturnsTwice() ||382 (MF.getTarget().Options.GuaranteedTailCallOpt &&383 MF.getInfo<PPCFunctionInfo>()->hasFastCall());384}385 386void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {387 // When there is dynamic alloca in this function, we can not use the frame388 // pointer X31/R31 for the frameaddress lowering. In this case, only X1/R1389 // always points to the backchain.390 bool is31 = needsFP(MF) && !MF.getFrameInfo().hasVarSizedObjects();391 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;392 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;393 394 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();395 bool HasBP = RegInfo->hasBasePointer(MF);396 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;397 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;398 399 for (MachineBasicBlock &MBB : MF)400 for (MachineBasicBlock::iterator MBBI = MBB.end(); MBBI != MBB.begin();) {401 --MBBI;402 for (MachineOperand &MO : MBBI->operands()) {403 if (!MO.isReg())404 continue;405 406 switch (MO.getReg()) {407 case PPC::FP:408 MO.setReg(FPReg);409 break;410 case PPC::FP8:411 MO.setReg(FP8Reg);412 break;413 case PPC::BP:414 MO.setReg(BPReg);415 break;416 case PPC::BP8:417 MO.setReg(BP8Reg);418 break;419 420 }421 }422 }423}424 425/* This function will do the following:426 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12427 respectively (defaults recommended by the ABI) and return true428 - If MBB is not an entry block, initialize the register scavenger and look429 for available registers.430 - If the defaults (R0/R12) are available, return true431 - If TwoUniqueRegsRequired is set to true, it looks for two unique432 registers. Otherwise, look for a single available register.433 - If the required registers are found, set SR1 and SR2 and return true.434 - If the required registers are not found, set SR2 or both SR1 and SR2 to435 PPC::NoRegister and return false.436 437 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired438 is not set, this function will attempt to find two different registers, but439 still return true if only one register is available (and set SR1 == SR2).440*/441bool442PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,443 bool UseAtEnd,444 bool TwoUniqueRegsRequired,445 Register *SR1,446 Register *SR2) const {447 RegScavenger RS;448 Register R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;449 Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;450 451 // Set the defaults for the two scratch registers.452 if (SR1)453 *SR1 = R0;454 455 if (SR2) {456 assert (SR1 && "Asking for the second scratch register but not the first?");457 *SR2 = R12;458 }459 460 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.461 if ((UseAtEnd && MBB->isReturnBlock()) ||462 (!UseAtEnd && (&MBB->getParent()->front() == MBB)))463 return true;464 465 if (UseAtEnd) {466 // The scratch register will be used before the first terminator (or at the467 // end of the block if there are no terminators).468 MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator();469 if (MBBI == MBB->begin()) {470 RS.enterBasicBlock(*MBB);471 } else {472 RS.enterBasicBlockEnd(*MBB);473 RS.backward(MBBI);474 }475 } else {476 // The scratch register will be used at the start of the block.477 RS.enterBasicBlock(*MBB);478 }479 480 // If the two registers are available, we're all good.481 // Note that we only return here if both R0 and R12 are available because482 // although the function may not require two unique registers, it may benefit483 // from having two so we should try to provide them.484 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))485 return true;486 487 // Get the list of callee-saved registers for the target.488 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();489 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());490 491 // Get all the available registers in the block.492 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :493 &PPC::GPRCRegClass);494 495 // We shouldn't use callee-saved registers as scratch registers as they may be496 // available when looking for a candidate block for shrink wrapping but not497 // available when the actual prologue/epilogue is being emitted because they498 // were added as live-in to the prologue block by PrologueEpilogueInserter.499 for (int i = 0; CSRegs[i]; ++i)500 BV.reset(CSRegs[i]);501 502 // Set the first scratch register to the first available one.503 if (SR1) {504 int FirstScratchReg = BV.find_first();505 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;506 }507 508 // If there is another one available, set the second scratch register to that.509 // Otherwise, set it to either PPC::NoRegister if this function requires two510 // or to whatever SR1 is set to if this function doesn't require two.511 if (SR2) {512 int SecondScratchReg = BV.find_next(*SR1);513 if (SecondScratchReg != -1)514 *SR2 = SecondScratchReg;515 else516 *SR2 = TwoUniqueRegsRequired ? Register() : *SR1;517 }518 519 // Now that we've done our best to provide both registers, double check520 // whether we were unable to provide enough.521 if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))522 return false;523 524 return true;525}526 527// We need a scratch register for spilling LR and for spilling CR. By default,528// we use two scratch registers to hide latency. However, if only one scratch529// register is available, we can adjust for that by not overlapping the spill530// code. However, if we need to realign the stack (i.e. have a base pointer)531// and the stack frame is large, we need two scratch registers.532// Also, stack probe requires two scratch registers, one for old sp, one for533// large frame and large probe size.534bool535PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {536 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();537 MachineFunction &MF = *(MBB->getParent());538 bool HasBP = RegInfo->hasBasePointer(MF);539 unsigned FrameSize = determineFrameLayout(MF);540 int NegFrameSize = -FrameSize;541 bool IsLargeFrame = !isInt<16>(NegFrameSize);542 MachineFrameInfo &MFI = MF.getFrameInfo();543 Align MaxAlign = MFI.getMaxAlign();544 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();545 const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();546 547 return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||548 TLI.hasInlineStackProbe(MF);549}550 551bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {552 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);553 554 return findScratchRegister(TmpMBB, false,555 twoUniqueScratchRegsRequired(TmpMBB));556}557 558bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {559 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);560 561 return findScratchRegister(TmpMBB, true);562}563 564bool PPCFrameLowering::stackUpdateCanBeMoved(MachineFunction &MF) const {565 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();566 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();567 568 // Abort if there is no register info or function info.569 if (!RegInfo || !FI)570 return false;571 572 // Only move the stack update on ELFv2 ABI and PPC64.573 if (!Subtarget.isELFv2ABI() || !Subtarget.isPPC64())574 return false;575 576 // Check the frame size first and return false if it does not fit the577 // requirements.578 // We need a non-zero frame size as well as a frame that will fit in the red579 // zone. This is because by moving the stack pointer update we are now storing580 // to the red zone until the stack pointer is updated. If we get an interrupt581 // inside the prologue but before the stack update we now have a number of582 // stores to the red zone and those stores must all fit.583 MachineFrameInfo &MFI = MF.getFrameInfo();584 unsigned FrameSize = MFI.getStackSize();585 if (!FrameSize || FrameSize > Subtarget.getRedZoneSize())586 return false;587 588 // Frame pointers and base pointers complicate matters so don't do anything589 // if we have them. For example having a frame pointer will sometimes require590 // a copy of r1 into r31 and that makes keeping track of updates to r1 more591 // difficult. Similar situation exists with setjmp.592 if (hasFP(MF) || RegInfo->hasBasePointer(MF) || MF.exposesReturnsTwice())593 return false;594 595 // Calls to fast_cc functions use different rules for passing parameters on596 // the stack from the ABI and using PIC base in the function imposes597 // similar restrictions to using the base pointer. It is not generally safe598 // to move the stack pointer update in these situations.599 if (FI->hasFastCall() || FI->usesPICBase())600 return false;601 602 // Finally we can move the stack update if we do not require register603 // scavenging. Register scavenging can introduce more spills and so604 // may make the frame size larger than we have computed.605 return !RegInfo->requiresFrameIndexScavenging(MF);606}607 608void PPCFrameLowering::emitPrologue(MachineFunction &MF,609 MachineBasicBlock &MBB) const {610 MachineBasicBlock::iterator MBBI = MBB.begin();611 MachineFrameInfo &MFI = MF.getFrameInfo();612 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();613 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();614 const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();615 616 const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();617 DebugLoc dl;618 // AIX assembler does not support cfi directives.619 const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();620 621 const bool HasFastMFLR = Subtarget.hasFastMFLR();622 623 // Get processor type.624 bool isPPC64 = Subtarget.isPPC64();625 // Get the ABI.626 bool isSVR4ABI = Subtarget.isSVR4ABI();627 bool isELFv2ABI = Subtarget.isELFv2ABI();628 assert((isSVR4ABI || Subtarget.isAIXABI()) && "Unsupported PPC ABI.");629 630 // Work out frame sizes.631 uint64_t FrameSize = determineFrameLayoutAndUpdate(MF);632 int64_t NegFrameSize = -FrameSize;633 if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))634 llvm_unreachable("Unhandled stack size!");635 636 if (MFI.isFrameAddressTaken())637 replaceFPWithRealFP(MF);638 639 // Check if the link register (LR) must be saved.640 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();641 bool MustSaveLR = FI->mustSaveLR();642 bool MustSaveTOC = FI->mustSaveTOC();643 const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();644 bool MustSaveCR = !MustSaveCRs.empty();645 // Do we have a frame pointer and/or base pointer for this function?646 bool HasFP = hasFP(MF);647 bool HasBP = RegInfo->hasBasePointer(MF);648 bool HasRedZone = isPPC64 || !isSVR4ABI;649 const bool HasROPProtect = Subtarget.hasROPProtect();650 bool HasPrivileged = Subtarget.hasPrivileged();651 652 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;653 Register BPReg = RegInfo->getBaseRegister(MF);654 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;655 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;656 Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;657 Register ScratchReg;658 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg659 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)660 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8661 : PPC::MFLR );662 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD663 : PPC::STW );664 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU665 : PPC::STWU );666 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX667 : PPC::STWUX);668 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8669 : PPC::OR );670 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8671 : PPC::SUBFC);672 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8673 : PPC::SUBFIC);674 const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8675 : PPC::MFCR);676 const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW);677 const MCInstrDesc &HashST =678 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)679 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));680 681 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,682 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no683 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &684 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.685 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&686 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");687 688 // Using the same bool variable as below to suppress compiler warnings.689 bool SingleScratchReg = findScratchRegister(690 &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg);691 assert(SingleScratchReg &&692 "Required number of registers not available in this block");693 694 SingleScratchReg = ScratchReg == TempReg;695 696 int64_t LROffset = getReturnSaveOffset();697 698 int64_t FPOffset = 0;699 if (HasFP) {700 MachineFrameInfo &MFI = MF.getFrameInfo();701 int FPIndex = FI->getFramePointerSaveIndex();702 assert(FPIndex && "No Frame Pointer Save Slot!");703 FPOffset = MFI.getObjectOffset(FPIndex);704 }705 706 int64_t BPOffset = 0;707 if (HasBP) {708 MachineFrameInfo &MFI = MF.getFrameInfo();709 int BPIndex = FI->getBasePointerSaveIndex();710 assert(BPIndex && "No Base Pointer Save Slot!");711 BPOffset = MFI.getObjectOffset(BPIndex);712 }713 714 int64_t PBPOffset = 0;715 if (FI->usesPICBase()) {716 MachineFrameInfo &MFI = MF.getFrameInfo();717 int PBPIndex = FI->getPICBasePointerSaveIndex();718 assert(PBPIndex && "No PIC Base Pointer Save Slot!");719 PBPOffset = MFI.getObjectOffset(PBPIndex);720 }721 722 // Get stack alignments.723 Align MaxAlign = MFI.getMaxAlign();724 if (HasBP && MaxAlign > 1)725 assert(Log2(MaxAlign) < 16 && "Invalid alignment!");726 727 // Frames of 32KB & larger require special handling because they cannot be728 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.729 bool isLargeFrame = !isInt<16>(NegFrameSize);730 731 // Check if we can move the stack update instruction (stdu) down the prologue732 // past the callee saves. Hopefully this will avoid the situation where the733 // saves are waiting for the update on the store with update to complete.734 MachineBasicBlock::iterator StackUpdateLoc = MBBI;735 bool MovingStackUpdateDown = false;736 737 // Check if we can move the stack update.738 if (stackUpdateCanBeMoved(MF)) {739 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();740 for (CalleeSavedInfo CSI : Info) {741 // If the callee saved register is spilled to a register instead of the742 // stack then the spill no longer uses the stack pointer.743 // This can lead to two consequences:744 // 1) We no longer need to update the stack because the function does not745 // spill any callee saved registers to stack.746 // 2) We have a situation where we still have to update the stack pointer747 // even though some registers are spilled to other registers. In748 // this case the current code moves the stack update to an incorrect749 // position.750 // In either case we should abort moving the stack update operation.751 if (CSI.isSpilledToReg()) {752 StackUpdateLoc = MBBI;753 MovingStackUpdateDown = false;754 break;755 }756 757 int FrIdx = CSI.getFrameIdx();758 // If the frame index is not negative the callee saved info belongs to a759 // stack object that is not a fixed stack object. We ignore non-fixed760 // stack objects because we won't move the stack update pointer past them.761 if (FrIdx >= 0)762 continue;763 764 if (MFI.isFixedObjectIndex(FrIdx) && MFI.getObjectOffset(FrIdx) < 0) {765 StackUpdateLoc++;766 MovingStackUpdateDown = true;767 } else {768 // We need all of the Frame Indices to meet these conditions.769 // If they do not, abort the whole operation.770 StackUpdateLoc = MBBI;771 MovingStackUpdateDown = false;772 break;773 }774 }775 776 // If the operation was not aborted then update the object offset.777 if (MovingStackUpdateDown) {778 for (CalleeSavedInfo CSI : Info) {779 int FrIdx = CSI.getFrameIdx();780 if (FrIdx < 0)781 MFI.setObjectOffset(FrIdx, MFI.getObjectOffset(FrIdx) + NegFrameSize);782 }783 }784 }785 786 // Where in the prologue we move the CR fields depends on how many scratch787 // registers we have, and if we need to save the link register or not. This788 // lambda is to avoid duplicating the logic in 2 places.789 auto BuildMoveFromCR = [&]() {790 if (isELFv2ABI && MustSaveCRs.size() == 1) {791 // In the ELFv2 ABI, we are not required to save all CR fields.792 // If only one CR field is clobbered, it is more efficient to use793 // mfocrf to selectively save just that field, because mfocrf has short794 // latency compares to mfcr.795 assert(isPPC64 && "V2 ABI is 64-bit only.");796 MachineInstrBuilder MIB =797 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg);798 MIB.addReg(MustSaveCRs[0], RegState::Kill);799 } else {800 MachineInstrBuilder MIB =801 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg);802 for (unsigned CRfield : MustSaveCRs)803 MIB.addReg(CRfield, RegState::ImplicitKill);804 }805 };806 807 // If we need to spill the CR and the LR but we don't have two separate808 // registers available, we must spill them one at a time809 if (MustSaveCR && SingleScratchReg && MustSaveLR) {810 BuildMoveFromCR();811 BuildMI(MBB, MBBI, dl, StoreWordInst)812 .addReg(TempReg, getKillRegState(true))813 .addImm(CRSaveOffset)814 .addReg(SPReg);815 }816 817 if (MustSaveLR)818 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);819 820 if (MustSaveCR && !(SingleScratchReg && MustSaveLR))821 BuildMoveFromCR();822 823 if (HasRedZone) {824 if (HasFP)825 BuildMI(MBB, MBBI, dl, StoreInst)826 .addReg(FPReg)827 .addImm(FPOffset)828 .addReg(SPReg);829 if (FI->usesPICBase())830 BuildMI(MBB, MBBI, dl, StoreInst)831 .addReg(PPC::R30)832 .addImm(PBPOffset)833 .addReg(SPReg);834 if (HasBP)835 BuildMI(MBB, MBBI, dl, StoreInst)836 .addReg(BPReg)837 .addImm(BPOffset)838 .addReg(SPReg);839 }840 841 // Generate the instruction to store the LR. In the case where ROP protection842 // is required the register holding the LR should not be killed as it will be843 // used by the hash store instruction.844 auto SaveLR = [&](int64_t Offset) {845 assert(MustSaveLR && "LR is not required to be saved!");846 BuildMI(MBB, StackUpdateLoc, dl, StoreInst)847 .addReg(ScratchReg, getKillRegState(!HasROPProtect))848 .addImm(Offset)849 .addReg(SPReg);850 851 // Add the ROP protection Hash Store instruction.852 // NOTE: This is technically a violation of the ABI. The hash can be saved853 // up to 512 bytes into the Protected Zone. This can be outside of the854 // initial 288 byte volatile program storage region in the Protected Zone.855 // However, this restriction will be removed in an upcoming revision of the856 // ABI.857 if (HasROPProtect) {858 const int SaveIndex = FI->getROPProtectionHashSaveIndex();859 const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex);860 assert((ImmOffset <= -8 && ImmOffset >= -512) &&861 "ROP hash save offset out of range.");862 assert(((ImmOffset & 0x7) == 0) &&863 "ROP hash save offset must be 8 byte aligned.");864 BuildMI(MBB, StackUpdateLoc, dl, HashST)865 .addReg(ScratchReg, getKillRegState(true))866 .addImm(ImmOffset)867 .addReg(SPReg);868 }869 };870 871 if (MustSaveLR && HasFastMFLR)872 SaveLR(LROffset);873 874 if (MustSaveCR &&875 !(SingleScratchReg && MustSaveLR)) {876 assert(HasRedZone && "A red zone is always available on PPC64");877 BuildMI(MBB, MBBI, dl, StoreWordInst)878 .addReg(TempReg, getKillRegState(true))879 .addImm(CRSaveOffset)880 .addReg(SPReg);881 }882 883 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.884 if (!FrameSize) {885 if (MustSaveLR && !HasFastMFLR)886 SaveLR(LROffset);887 return;888 }889 890 // Adjust stack pointer: r1 += NegFrameSize.891 // If there is a preferred stack alignment, align R1 now892 893 if (HasBP && HasRedZone) {894 // Save a copy of r1 as the base pointer.895 BuildMI(MBB, MBBI, dl, OrInst, BPReg)896 .addReg(SPReg)897 .addReg(SPReg);898 }899 900 // Have we generated a STUX instruction to claim stack frame? If so,901 // the negated frame size will be placed in ScratchReg.902 bool HasSTUX =903 (TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) ||904 (HasBP && MaxAlign > 1) || isLargeFrame;905 906 // If we use STUX to update the stack pointer, we need the two scratch907 // registers TempReg and ScratchReg, we have to save LR here which is stored908 // in ScratchReg.909 // If the offset can not be encoded into the store instruction, we also have910 // to save LR here.911 // If we are using ROP Protection we need to save the LR here as we cannot912 // move the hashst instruction past the point where we get the stack frame.913 if (MustSaveLR && !HasFastMFLR &&914 (HasSTUX || !isInt<16>(FrameSize + LROffset) || HasROPProtect))915 SaveLR(LROffset);916 917 // If FrameSize <= TLI.getStackProbeSize(MF), as POWER ABI requires backchain918 // pointer is always stored at SP, we will get a free probe due to an essential919 // STU(X) instruction.920 if (TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) {921 // To be consistent with other targets, a pseudo instruction is emitted and922 // will be later expanded in `inlineStackProbe`.923 BuildMI(MBB, MBBI, dl,924 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64925 : PPC::PROBED_STACKALLOC_32))926 .addDef(TempReg)927 .addDef(ScratchReg) // ScratchReg stores the old sp.928 .addImm(NegFrameSize);929 // FIXME: HasSTUX is only read if HasRedZone is not set, in such case, we930 // update the ScratchReg to meet the assumption that ScratchReg contains931 // the NegFrameSize. This solution is rather tricky.932 if (!HasRedZone) {933 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)934 .addReg(ScratchReg)935 .addReg(SPReg);936 }937 } else {938 // This condition must be kept in sync with canUseAsPrologue.939 if (HasBP && MaxAlign > 1) {940 if (isPPC64)941 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)942 .addReg(SPReg)943 .addImm(0)944 .addImm(64 - Log2(MaxAlign));945 else // PPC32...946 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)947 .addReg(SPReg)948 .addImm(0)949 .addImm(32 - Log2(MaxAlign))950 .addImm(31);951 if (!isLargeFrame) {952 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)953 .addReg(ScratchReg, RegState::Kill)954 .addImm(NegFrameSize);955 } else {956 assert(!SingleScratchReg && "Only a single scratch reg available");957 TII.materializeImmPostRA(MBB, MBBI, dl, TempReg, NegFrameSize);958 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)959 .addReg(ScratchReg, RegState::Kill)960 .addReg(TempReg, RegState::Kill);961 }962 963 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)964 .addReg(SPReg, RegState::Kill)965 .addReg(SPReg)966 .addReg(ScratchReg);967 } else if (!isLargeFrame) {968 BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)969 .addReg(SPReg)970 .addImm(NegFrameSize)971 .addReg(SPReg);972 } else {973 TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize);974 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)975 .addReg(SPReg, RegState::Kill)976 .addReg(SPReg)977 .addReg(ScratchReg);978 }979 }980 981 // Save the TOC register after the stack pointer update if a prologue TOC982 // save is required for the function.983 if (MustSaveTOC) {984 assert(isELFv2ABI && "TOC saves in the prologue only supported on ELFv2");985 BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD))986 .addReg(TOCReg, getKillRegState(true))987 .addImm(TOCSaveOffset)988 .addReg(SPReg);989 }990 991 if (!HasRedZone) {992 assert(!isPPC64 && "A red zone is always available on PPC64");993 if (HasSTUX) {994 // The negated frame size is in ScratchReg, and the SPReg has been995 // decremented by the frame size: SPReg = old SPReg + ScratchReg.996 // Since FPOffset, PBPOffset, etc. are relative to the beginning of997 // the stack frame (i.e. the old SP), ideally, we would put the old998 // SP into a register and use it as the base for the stores. The999 // problem is that the only available register may be ScratchReg,1000 // which could be R0, and R0 cannot be used as a base address.1001 1002 // First, set ScratchReg to the old SP. This may need to be modified1003 // later.1004 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)1005 .addReg(ScratchReg, RegState::Kill)1006 .addReg(SPReg);1007 1008 if (ScratchReg == PPC::R0) {1009 // R0 cannot be used as a base register, but it can be used as an1010 // index in a store-indexed.1011 int LastOffset = 0;1012 if (HasFP) {1013 // R0 += (FPOffset-LastOffset).1014 // Need addic, since addi treats R0 as 0.1015 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)1016 .addReg(ScratchReg)1017 .addImm(FPOffset-LastOffset);1018 LastOffset = FPOffset;1019 // Store FP into *R0.1020 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))1021 .addReg(FPReg, RegState::Kill) // Save FP.1022 .addReg(PPC::ZERO)1023 .addReg(ScratchReg); // This will be the index (R0 is ok here).1024 }1025 if (FI->usesPICBase()) {1026 // R0 += (PBPOffset-LastOffset).1027 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)1028 .addReg(ScratchReg)1029 .addImm(PBPOffset-LastOffset);1030 LastOffset = PBPOffset;1031 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))1032 .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.1033 .addReg(PPC::ZERO)1034 .addReg(ScratchReg); // This will be the index (R0 is ok here).1035 }1036 if (HasBP) {1037 // R0 += (BPOffset-LastOffset).1038 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)1039 .addReg(ScratchReg)1040 .addImm(BPOffset-LastOffset);1041 LastOffset = BPOffset;1042 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))1043 .addReg(BPReg, RegState::Kill) // Save BP.1044 .addReg(PPC::ZERO)1045 .addReg(ScratchReg); // This will be the index (R0 is ok here).1046 // BP = R0-LastOffset1047 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)1048 .addReg(ScratchReg, RegState::Kill)1049 .addImm(-LastOffset);1050 }1051 } else {1052 // ScratchReg is not R0, so use it as the base register. It is1053 // already set to the old SP, so we can use the offsets directly.1054 1055 // Now that the stack frame has been allocated, save all the necessary1056 // registers using ScratchReg as the base address.1057 if (HasFP)1058 BuildMI(MBB, MBBI, dl, StoreInst)1059 .addReg(FPReg)1060 .addImm(FPOffset)1061 .addReg(ScratchReg);1062 if (FI->usesPICBase())1063 BuildMI(MBB, MBBI, dl, StoreInst)1064 .addReg(PPC::R30)1065 .addImm(PBPOffset)1066 .addReg(ScratchReg);1067 if (HasBP) {1068 BuildMI(MBB, MBBI, dl, StoreInst)1069 .addReg(BPReg)1070 .addImm(BPOffset)1071 .addReg(ScratchReg);1072 BuildMI(MBB, MBBI, dl, OrInst, BPReg)1073 .addReg(ScratchReg, RegState::Kill)1074 .addReg(ScratchReg);1075 }1076 }1077 } else {1078 // The frame size is a known 16-bit constant (fitting in the immediate1079 // field of STWU). To be here we have to be compiling for PPC32.1080 // Since the SPReg has been decreased by FrameSize, add it back to each1081 // offset.1082 if (HasFP)1083 BuildMI(MBB, MBBI, dl, StoreInst)1084 .addReg(FPReg)1085 .addImm(FrameSize + FPOffset)1086 .addReg(SPReg);1087 if (FI->usesPICBase())1088 BuildMI(MBB, MBBI, dl, StoreInst)1089 .addReg(PPC::R30)1090 .addImm(FrameSize + PBPOffset)1091 .addReg(SPReg);1092 if (HasBP) {1093 BuildMI(MBB, MBBI, dl, StoreInst)1094 .addReg(BPReg)1095 .addImm(FrameSize + BPOffset)1096 .addReg(SPReg);1097 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)1098 .addReg(SPReg)1099 .addImm(FrameSize);1100 }1101 }1102 }1103 1104 // Save the LR now.1105 if (!HasSTUX && MustSaveLR && !HasFastMFLR &&1106 isInt<16>(FrameSize + LROffset) && !HasROPProtect)1107 SaveLR(LROffset + FrameSize);1108 1109 // Add Call Frame Information for the instructions we generated above.1110 if (needsCFI) {1111 unsigned CFIIndex;1112 1113 if (HasBP) {1114 // Define CFA in terms of BP. Do this in preference to using FP/SP,1115 // because if the stack needed aligning then CFA won't be at a fixed1116 // offset from FP/SP.1117 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);1118 CFIIndex = MF.addFrameInst(1119 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));1120 } else {1121 // Adjust the definition of CFA to account for the change in SP.1122 assert(NegFrameSize);1123 CFIIndex = MF.addFrameInst(1124 MCCFIInstruction::cfiDefCfaOffset(nullptr, -NegFrameSize));1125 }1126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1127 .addCFIIndex(CFIIndex);1128 1129 if (HasFP) {1130 // Describe where FP was saved, at a fixed offset from CFA.1131 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);1132 CFIIndex = MF.addFrameInst(1133 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));1134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1135 .addCFIIndex(CFIIndex);1136 }1137 1138 if (FI->usesPICBase()) {1139 // Describe where FP was saved, at a fixed offset from CFA.1140 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);1141 CFIIndex = MF.addFrameInst(1142 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));1143 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1144 .addCFIIndex(CFIIndex);1145 }1146 1147 if (HasBP) {1148 // Describe where BP was saved, at a fixed offset from CFA.1149 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);1150 CFIIndex = MF.addFrameInst(1151 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));1152 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1153 .addCFIIndex(CFIIndex);1154 }1155 1156 if (MustSaveLR) {1157 // Describe where LR was saved, at a fixed offset from CFA.1158 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);1159 CFIIndex = MF.addFrameInst(1160 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));1161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1162 .addCFIIndex(CFIIndex);1163 }1164 }1165 1166 // If there is a frame pointer, copy R1 into R311167 if (HasFP) {1168 BuildMI(MBB, MBBI, dl, OrInst, FPReg)1169 .addReg(SPReg)1170 .addReg(SPReg);1171 1172 if (!HasBP && needsCFI) {1173 // Change the definition of CFA from SP+offset to FP+offset, because SP1174 // will change at every alloca.1175 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);1176 unsigned CFIIndex = MF.addFrameInst(1177 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));1178 1179 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1180 .addCFIIndex(CFIIndex);1181 }1182 }1183 1184 if (needsCFI) {1185 // Describe where callee saved registers were saved, at fixed offsets from1186 // CFA.1187 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();1188 for (const CalleeSavedInfo &I : CSI) {1189 MCRegister Reg = I.getReg();1190 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;1191 1192 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just1193 // subregisters of CR2. We just need to emit a move of CR2.1194 if (PPC::CRBITRCRegClass.contains(Reg))1195 continue;1196 1197 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)1198 continue;1199 1200 // For 64-bit SVR4 when we have spilled CRs, the spill location1201 // is SP+8, not a frame-relative slot.1202 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {1203 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for1204 // the whole CR word. In the ELFv2 ABI, every CR that was1205 // actually saved gets its own CFI record.1206 Register CRReg = isELFv2ABI? Reg : PPC::CR2;1207 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(1208 nullptr, MRI->getDwarfRegNum(CRReg, true), CRSaveOffset));1209 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1210 .addCFIIndex(CFIIndex);1211 continue;1212 }1213 1214 if (I.isSpilledToReg()) {1215 unsigned SpilledReg = I.getDstReg();1216 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister(1217 nullptr, MRI->getDwarfRegNum(Reg, true),1218 MRI->getDwarfRegNum(SpilledReg, true)));1219 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1220 .addCFIIndex(CFIRegister);1221 } else {1222 int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());1223 // We have changed the object offset above but we do not want to change1224 // the actual offsets in the CFI instruction so we have to undo the1225 // offset change here.1226 if (MovingStackUpdateDown)1227 Offset -= NegFrameSize;1228 1229 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(1230 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));1231 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))1232 .addCFIIndex(CFIIndex);1233 }1234 }1235 }1236}1237 1238void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,1239 MachineBasicBlock &PrologMBB) const {1240 bool isPPC64 = Subtarget.isPPC64();1241 const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();1242 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();1243 MachineFrameInfo &MFI = MF.getFrameInfo();1244 const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();1245 // AIX assembler does not support cfi directives.1246 const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();1247 auto StackAllocMIPos = llvm::find_if(PrologMBB, [](MachineInstr &MI) {1248 int Opc = MI.getOpcode();1249 return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;1250 });1251 if (StackAllocMIPos == PrologMBB.end())1252 return;1253 const BasicBlock *ProbedBB = PrologMBB.getBasicBlock();1254 MachineBasicBlock *CurrentMBB = &PrologMBB;1255 DebugLoc DL = PrologMBB.findDebugLoc(StackAllocMIPos);1256 MachineInstr &MI = *StackAllocMIPos;1257 int64_t NegFrameSize = MI.getOperand(2).getImm();1258 unsigned ProbeSize = TLI.getStackProbeSize(MF);1259 int64_t NegProbeSize = -(int64_t)ProbeSize;1260 assert(isInt<32>(NegProbeSize) && "Unhandled probe size");1261 int64_t NumBlocks = NegFrameSize / NegProbeSize;1262 int64_t NegResidualSize = NegFrameSize % NegProbeSize;1263 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;1264 Register ScratchReg = MI.getOperand(0).getReg();1265 Register FPReg = MI.getOperand(1).getReg();1266 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();1267 bool HasBP = RegInfo->hasBasePointer(MF);1268 Register BPReg = RegInfo->getBaseRegister(MF);1269 Align MaxAlign = MFI.getMaxAlign();1270 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();1271 const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR);1272 // Subroutines to generate .cfi_* directives.1273 auto buildDefCFAReg = [&](MachineBasicBlock &MBB,1274 MachineBasicBlock::iterator MBBI, Register Reg) {1275 unsigned RegNum = MRI->getDwarfRegNum(Reg, true);1276 unsigned CFIIndex = MF.addFrameInst(1277 MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));1278 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))1279 .addCFIIndex(CFIIndex);1280 };1281 auto buildDefCFA = [&](MachineBasicBlock &MBB,1282 MachineBasicBlock::iterator MBBI, Register Reg,1283 int Offset) {1284 unsigned RegNum = MRI->getDwarfRegNum(Reg, true);1285 unsigned CFIIndex = MBB.getParent()->addFrameInst(1286 MCCFIInstruction::cfiDefCfa(nullptr, RegNum, Offset));1287 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))1288 .addCFIIndex(CFIIndex);1289 };1290 // Subroutine to determine if we can use the Imm as part of d-form.1291 auto CanUseDForm = [](int64_t Imm) { return isInt<16>(Imm) && Imm % 4 == 0; };1292 // Subroutine to materialize the Imm into TempReg.1293 auto MaterializeImm = [&](MachineBasicBlock &MBB,1294 MachineBasicBlock::iterator MBBI, int64_t Imm,1295 Register &TempReg) {1296 assert(isInt<32>(Imm) && "Unhandled imm");1297 if (isInt<16>(Imm))1298 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::LI8 : PPC::LI), TempReg)1299 .addImm(Imm);1300 else {1301 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)1302 .addImm(Imm >> 16);1303 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::ORI8 : PPC::ORI), TempReg)1304 .addReg(TempReg)1305 .addImm(Imm & 0xFFFF);1306 }1307 };1308 // Subroutine to store frame pointer and decrease stack pointer by probe size.1309 auto allocateAndProbe = [&](MachineBasicBlock &MBB,1310 MachineBasicBlock::iterator MBBI, int64_t NegSize,1311 Register NegSizeReg, bool UseDForm,1312 Register StoreReg) {1313 if (UseDForm)1314 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg)1315 .addReg(StoreReg)1316 .addImm(NegSize)1317 .addReg(SPReg);1318 else1319 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)1320 .addReg(StoreReg)1321 .addReg(SPReg)1322 .addReg(NegSizeReg);1323 };1324 // Used to probe stack when realignment is required.1325 // Note that, according to ABI's requirement, *sp must always equals the1326 // value of back-chain pointer, only st(w|d)u(x) can be used to update sp.1327 // Following is pseudo code:1328 // final_sp = (sp & align) + negframesize;1329 // neg_gap = final_sp - sp;1330 // while (neg_gap < negprobesize) {1331 // stdu fp, negprobesize(sp);1332 // neg_gap -= negprobesize;1333 // }1334 // stdux fp, sp, neg_gap1335 //1336 // When HasBP & HasRedzone, back-chain pointer is already saved in BPReg1337 // before probe code, we don't need to save it, so we get one additional reg1338 // that can be used to materialize the probeside if needed to use xform.1339 // Otherwise, we can NOT materialize probeside, so we can only use Dform for1340 // now.1341 //1342 // The allocations are:1343 // if (HasBP && HasRedzone) {1344 // r0: materialize the probesize if needed so that we can use xform.1345 // r12: `neg_gap`1346 // } else {1347 // r0: back-chain pointer1348 // r12: `neg_gap`.1349 // }1350 auto probeRealignedStack = [&](MachineBasicBlock &MBB,1351 MachineBasicBlock::iterator MBBI,1352 Register ScratchReg, Register TempReg) {1353 assert(HasBP && "The function is supposed to have base pointer when its "1354 "stack is realigned.");1355 assert(isPowerOf2_64(ProbeSize) && "Probe size should be power of 2");1356 1357 // FIXME: We can eliminate this limitation if we get more infomation about1358 // which part of redzone are already used. Used redzone can be treated1359 // probed. But there might be `holes' in redzone probed, this could1360 // complicate the implementation.1361 assert(ProbeSize >= Subtarget.getRedZoneSize() &&1362 "Probe size should be larger or equal to the size of red-zone so "1363 "that red-zone is not clobbered by probing.");1364 1365 Register &FinalStackPtr = TempReg;1366 // FIXME: We only support NegProbeSize materializable by DForm currently.1367 // When HasBP && HasRedzone, we can use xform if we have an additional idle1368 // register.1369 NegProbeSize = std::max(NegProbeSize, -((int64_t)1 << 15));1370 assert(isInt<16>(NegProbeSize) &&1371 "NegProbeSize should be materializable by DForm");1372 Register CRReg = PPC::CR0;1373 // Layout of output assembly kinda like:1374 // bb.0:1375 // ...1376 // sub $scratchreg, $finalsp, r11377 // cmpdi $scratchreg, <negprobesize>1378 // bge bb.21379 // bb.1:1380 // stdu <backchain>, <negprobesize>(r1)1381 // sub $scratchreg, $scratchreg, negprobesize1382 // cmpdi $scratchreg, <negprobesize>1383 // blt bb.11384 // bb.2:1385 // stdux <backchain>, r1, $scratchreg1386 MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator());1387 MachineBasicBlock *ProbeLoopBodyMBB = MF.CreateMachineBasicBlock(ProbedBB);1388 MF.insert(MBBInsertPoint, ProbeLoopBodyMBB);1389 MachineBasicBlock *ProbeExitMBB = MF.CreateMachineBasicBlock(ProbedBB);1390 MF.insert(MBBInsertPoint, ProbeExitMBB);1391 // bb.21392 {1393 Register BackChainPointer = HasRedZone ? BPReg : TempReg;1394 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->end(), 0, ScratchReg, false,1395 BackChainPointer);1396 if (HasRedZone)1397 // PROBED_STACKALLOC_64 assumes Operand(1) stores the old sp, copy BPReg1398 // to TempReg to satisfy it.1399 BuildMI(*ProbeExitMBB, ProbeExitMBB->end(), DL, CopyInst, TempReg)1400 .addReg(BPReg)1401 .addReg(BPReg);1402 ProbeExitMBB->splice(ProbeExitMBB->end(), &MBB, MBBI, MBB.end());1403 ProbeExitMBB->transferSuccessorsAndUpdatePHIs(&MBB);1404 }1405 // bb.01406 {1407 BuildMI(&MBB, DL, TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)1408 .addReg(SPReg)1409 .addReg(FinalStackPtr);1410 if (!HasRedZone)1411 BuildMI(&MBB, DL, CopyInst, TempReg).addReg(SPReg).addReg(SPReg);1412 BuildMI(&MBB, DL, TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI), CRReg)1413 .addReg(ScratchReg)1414 .addImm(NegProbeSize);1415 BuildMI(&MBB, DL, TII.get(PPC::BCC))1416 .addImm(PPC::PRED_GE)1417 .addReg(CRReg)1418 .addMBB(ProbeExitMBB);1419 MBB.addSuccessor(ProbeLoopBodyMBB);1420 MBB.addSuccessor(ProbeExitMBB);1421 }1422 // bb.11423 {1424 Register BackChainPointer = HasRedZone ? BPReg : TempReg;1425 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->end(), NegProbeSize,1426 0, true /*UseDForm*/, BackChainPointer);1427 BuildMI(ProbeLoopBodyMBB, DL, TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),1428 ScratchReg)1429 .addReg(ScratchReg)1430 .addImm(-NegProbeSize);1431 BuildMI(ProbeLoopBodyMBB, DL, TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),1432 CRReg)1433 .addReg(ScratchReg)1434 .addImm(NegProbeSize);1435 BuildMI(ProbeLoopBodyMBB, DL, TII.get(PPC::BCC))1436 .addImm(PPC::PRED_LT)1437 .addReg(CRReg)1438 .addMBB(ProbeLoopBodyMBB);1439 ProbeLoopBodyMBB->addSuccessor(ProbeExitMBB);1440 ProbeLoopBodyMBB->addSuccessor(ProbeLoopBodyMBB);1441 }1442 // Update liveins.1443 fullyRecomputeLiveIns({ProbeExitMBB, ProbeLoopBodyMBB});1444 return ProbeExitMBB;1445 };1446 // For case HasBP && MaxAlign > 1, we have to realign the SP by performing1447 // SP = SP - SP % MaxAlign, thus make the probe more like dynamic probe since1448 // the offset subtracted from SP is determined by SP's runtime value.1449 if (HasBP && MaxAlign > 1) {1450 // Calculate final stack pointer.1451 if (isPPC64)1452 BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::RLDICL), ScratchReg)1453 .addReg(SPReg)1454 .addImm(0)1455 .addImm(64 - Log2(MaxAlign));1456 else1457 BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg)1458 .addReg(SPReg)1459 .addImm(0)1460 .addImm(32 - Log2(MaxAlign))1461 .addImm(31);1462 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),1463 FPReg)1464 .addReg(ScratchReg)1465 .addReg(SPReg);1466 MaterializeImm(*CurrentMBB, {MI}, NegFrameSize, ScratchReg);1467 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),1468 FPReg)1469 .addReg(ScratchReg)1470 .addReg(FPReg);1471 CurrentMBB = probeRealignedStack(*CurrentMBB, {MI}, ScratchReg, FPReg);1472 if (needsCFI)1473 buildDefCFAReg(*CurrentMBB, {MI}, FPReg);1474 } else {1475 // Initialize current frame pointer.1476 BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg);1477 // Use FPReg to calculate CFA.1478 if (needsCFI)1479 buildDefCFA(*CurrentMBB, {MI}, FPReg, 0);1480 // Probe residual part.1481 if (NegResidualSize) {1482 bool ResidualUseDForm = CanUseDForm(NegResidualSize);1483 if (!ResidualUseDForm)1484 MaterializeImm(*CurrentMBB, {MI}, NegResidualSize, ScratchReg);1485 allocateAndProbe(*CurrentMBB, {MI}, NegResidualSize, ScratchReg,1486 ResidualUseDForm, FPReg);1487 }1488 bool UseDForm = CanUseDForm(NegProbeSize);1489 // If number of blocks is small, just probe them directly.1490 if (NumBlocks < 3) {1491 if (!UseDForm)1492 MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg);1493 for (int i = 0; i < NumBlocks; ++i)1494 allocateAndProbe(*CurrentMBB, {MI}, NegProbeSize, ScratchReg, UseDForm,1495 FPReg);1496 if (needsCFI) {1497 // Restore using SPReg to calculate CFA.1498 buildDefCFAReg(*CurrentMBB, {MI}, SPReg);1499 }1500 } else {1501 // Since CTR is a volatile register and current shrinkwrap implementation1502 // won't choose an MBB in a loop as the PrologMBB, it's safe to synthesize a1503 // CTR loop to probe.1504 // Calculate trip count and stores it in CTRReg.1505 MaterializeImm(*CurrentMBB, {MI}, NumBlocks, ScratchReg);1506 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))1507 .addReg(ScratchReg, RegState::Kill);1508 if (!UseDForm)1509 MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg);1510 // Create MBBs of the loop.1511 MachineFunction::iterator MBBInsertPoint =1512 std::next(CurrentMBB->getIterator());1513 MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(ProbedBB);1514 MF.insert(MBBInsertPoint, LoopMBB);1515 MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(ProbedBB);1516 MF.insert(MBBInsertPoint, ExitMBB);1517 // Synthesize the loop body.1518 allocateAndProbe(*LoopMBB, LoopMBB->end(), NegProbeSize, ScratchReg,1519 UseDForm, FPReg);1520 BuildMI(LoopMBB, DL, TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))1521 .addMBB(LoopMBB);1522 LoopMBB->addSuccessor(ExitMBB);1523 LoopMBB->addSuccessor(LoopMBB);1524 // Synthesize the exit MBB.1525 ExitMBB->splice(ExitMBB->end(), CurrentMBB,1526 std::next(MachineBasicBlock::iterator(MI)),1527 CurrentMBB->end());1528 ExitMBB->transferSuccessorsAndUpdatePHIs(CurrentMBB);1529 CurrentMBB->addSuccessor(LoopMBB);1530 if (needsCFI) {1531 // Restore using SPReg to calculate CFA.1532 buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg);1533 }1534 // Update liveins.1535 fullyRecomputeLiveIns({ExitMBB, LoopMBB});1536 }1537 }1538 ++NumPrologProbed;1539 MI.eraseFromParent();1540}1541 1542void PPCFrameLowering::emitEpilogue(MachineFunction &MF,1543 MachineBasicBlock &MBB) const {1544 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();1545 DebugLoc dl;1546 1547 if (MBBI != MBB.end())1548 dl = MBBI->getDebugLoc();1549 1550 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();1551 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();1552 1553 // Get alignment info so we know how to restore the SP.1554 const MachineFrameInfo &MFI = MF.getFrameInfo();1555 1556 // Get the number of bytes allocated from the FrameInfo.1557 int64_t FrameSize = MFI.getStackSize();1558 1559 // Get processor type.1560 bool isPPC64 = Subtarget.isPPC64();1561 1562 // Check if the link register (LR) has been saved.1563 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();1564 bool MustSaveLR = FI->mustSaveLR();1565 const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();1566 bool MustSaveCR = !MustSaveCRs.empty();1567 // Do we have a frame pointer and/or base pointer for this function?1568 bool HasFP = hasFP(MF);1569 bool HasBP = RegInfo->hasBasePointer(MF);1570 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();1571 bool HasROPProtect = Subtarget.hasROPProtect();1572 bool HasPrivileged = Subtarget.hasPrivileged();1573 1574 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;1575 Register BPReg = RegInfo->getBaseRegister(MF);1576 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;1577 Register ScratchReg;1578 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg1579 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR81580 : PPC::MTLR );1581 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD1582 : PPC::LWZ );1583 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS81584 : PPC::LIS );1585 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR81586 : PPC::OR );1587 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI81588 : PPC::ORI );1589 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI81590 : PPC::ADDI );1591 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD81592 : PPC::ADD4 );1593 const MCInstrDesc& LoadWordInst = TII.get( isPPC64 ? PPC::LWZ81594 : PPC::LWZ);1595 const MCInstrDesc& MoveToCRInst = TII.get( isPPC64 ? PPC::MTOCRF81596 : PPC::MTOCRF);1597 const MCInstrDesc &HashChk =1598 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)1599 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));1600 int64_t LROffset = getReturnSaveOffset();1601 1602 int64_t FPOffset = 0;1603 1604 // Using the same bool variable as below to suppress compiler warnings.1605 bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,1606 &TempReg);1607 assert(SingleScratchReg &&1608 "Could not find an available scratch register");1609 1610 SingleScratchReg = ScratchReg == TempReg;1611 1612 if (HasFP) {1613 int FPIndex = FI->getFramePointerSaveIndex();1614 assert(FPIndex && "No Frame Pointer Save Slot!");1615 FPOffset = MFI.getObjectOffset(FPIndex);1616 }1617 1618 int64_t BPOffset = 0;1619 if (HasBP) {1620 int BPIndex = FI->getBasePointerSaveIndex();1621 assert(BPIndex && "No Base Pointer Save Slot!");1622 BPOffset = MFI.getObjectOffset(BPIndex);1623 }1624 1625 int64_t PBPOffset = 0;1626 if (FI->usesPICBase()) {1627 int PBPIndex = FI->getPICBasePointerSaveIndex();1628 assert(PBPIndex && "No PIC Base Pointer Save Slot!");1629 PBPOffset = MFI.getObjectOffset(PBPIndex);1630 }1631 1632 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());1633 1634 if (IsReturnBlock) {1635 unsigned RetOpcode = MBBI->getOpcode();1636 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||1637 RetOpcode == PPC::TCRETURNdi ||1638 RetOpcode == PPC::TCRETURNai ||1639 RetOpcode == PPC::TCRETURNri8 ||1640 RetOpcode == PPC::TCRETURNdi8 ||1641 RetOpcode == PPC::TCRETURNai8;1642 1643 if (UsesTCRet) {1644 int MaxTCRetDelta = FI->getTailCallSPDelta();1645 MachineOperand &StackAdjust = MBBI->getOperand(1);1646 assert(StackAdjust.isImm() && "Expecting immediate value.");1647 // Adjust stack pointer.1648 int StackAdj = StackAdjust.getImm();1649 int Delta = StackAdj - MaxTCRetDelta;1650 assert((Delta >= 0) && "Delta must be positive");1651 if (MaxTCRetDelta>0)1652 FrameSize += (StackAdj +Delta);1653 else1654 FrameSize += StackAdj;1655 }1656 }1657 1658 // Frames of 32KB & larger require special handling because they cannot be1659 // indexed into with a simple LD/LWZ immediate offset operand.1660 bool isLargeFrame = !isInt<16>(FrameSize);1661 1662 // On targets without red zone, the SP needs to be restored last, so that1663 // all live contents of the stack frame are upwards of the SP. This means1664 // that we cannot restore SP just now, since there may be more registers1665 // to restore from the stack frame (e.g. R31). If the frame size is not1666 // a simple immediate value, we will need a spare register to hold the1667 // restored SP. If the frame size is known and small, we can simply adjust1668 // the offsets of the registers to be restored, and still use SP to restore1669 // them. In such case, the final update of SP will be to add the frame1670 // size to it.1671 // To simplify the code, set RBReg to the base register used to restore1672 // values from the stack, and set SPAdd to the value that needs to be added1673 // to the SP at the end. The default values are as if red zone was present.1674 unsigned RBReg = SPReg;1675 uint64_t SPAdd = 0;1676 1677 // Check if we can move the stack update instruction up the epilogue1678 // past the callee saves. This will allow the move to LR instruction1679 // to be executed before the restores of the callee saves which means1680 // that the callee saves can hide the latency from the MTLR instrcution.1681 MachineBasicBlock::iterator StackUpdateLoc = MBBI;1682 if (stackUpdateCanBeMoved(MF)) {1683 const std::vector<CalleeSavedInfo> & Info = MFI.getCalleeSavedInfo();1684 for (CalleeSavedInfo CSI : Info) {1685 // If the callee saved register is spilled to another register abort the1686 // stack update movement.1687 if (CSI.isSpilledToReg()) {1688 StackUpdateLoc = MBBI;1689 break;1690 }1691 int FrIdx = CSI.getFrameIdx();1692 // If the frame index is not negative the callee saved info belongs to a1693 // stack object that is not a fixed stack object. We ignore non-fixed1694 // stack objects because we won't move the update of the stack pointer1695 // past them.1696 if (FrIdx >= 0)1697 continue;1698 1699 if (MFI.isFixedObjectIndex(FrIdx) && MFI.getObjectOffset(FrIdx) < 0)1700 StackUpdateLoc--;1701 else {1702 // Abort the operation as we can't update all CSR restores.1703 StackUpdateLoc = MBBI;1704 break;1705 }1706 }1707 }1708 1709 if (FrameSize) {1710 // In the prologue, the loaded (or persistent) stack pointer value is1711 // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red1712 // zone add this offset back now.1713 1714 // If the function has a base pointer, the stack pointer has been copied1715 // to it so we can restore it by copying in the other direction.1716 if (HasRedZone && HasBP) {1717 BuildMI(MBB, MBBI, dl, OrInst, RBReg).1718 addReg(BPReg).1719 addReg(BPReg);1720 }1721 // If this function contained a fastcc call and GuaranteedTailCallOpt is1722 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail1723 // call which invalidates the stack pointer value in SP(0). So we use the1724 // value of R31 in this case. Similar situation exists with setjmp.1725 else if (FI->hasFastCall() || MF.exposesReturnsTwice()) {1726 assert(HasFP && "Expecting a valid frame pointer.");1727 if (!HasRedZone)1728 RBReg = FPReg;1729 if (!isLargeFrame) {1730 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)1731 .addReg(FPReg).addImm(FrameSize);1732 } else {1733 TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, FrameSize);1734 BuildMI(MBB, MBBI, dl, AddInst)1735 .addReg(RBReg)1736 .addReg(FPReg)1737 .addReg(ScratchReg);1738 }1739 } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {1740 if (HasRedZone) {1741 BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)1742 .addReg(SPReg)1743 .addImm(FrameSize);1744 } else {1745 // Make sure that adding FrameSize will not overflow the max offset1746 // size.1747 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&1748 "Local offsets should be negative");1749 SPAdd = FrameSize;1750 FPOffset += FrameSize;1751 BPOffset += FrameSize;1752 PBPOffset += FrameSize;1753 }1754 } else {1755 // We don't want to use ScratchReg as a base register, because it1756 // could happen to be R0. Use FP instead, but make sure to preserve it.1757 if (!HasRedZone) {1758 // If FP is not saved, copy it to ScratchReg.1759 if (!HasFP)1760 BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)1761 .addReg(FPReg)1762 .addReg(FPReg);1763 RBReg = FPReg;1764 }1765 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg)1766 .addImm(0)1767 .addReg(SPReg);1768 }1769 }1770 assert(RBReg != ScratchReg && "Should have avoided ScratchReg");1771 // If there is no red zone, ScratchReg may be needed for holding a useful1772 // value (although not the base register). Make sure it is not overwritten1773 // too early.1774 1775 // If we need to restore both the LR and the CR and we only have one1776 // available scratch register, we must do them one at a time.1777 if (MustSaveCR && SingleScratchReg && MustSaveLR) {1778 // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg1779 // is live here.1780 assert(HasRedZone && "Expecting red zone");1781 BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)1782 .addImm(CRSaveOffset)1783 .addReg(SPReg);1784 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)1785 BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])1786 .addReg(TempReg, getKillRegState(i == e-1));1787 }1788 1789 // Delay restoring of the LR if ScratchReg is needed. This is ok, since1790 // LR is stored in the caller's stack frame. ScratchReg will be needed1791 // if RBReg is anything other than SP. We shouldn't use ScratchReg as1792 // a base register anyway, because it may happen to be R0.1793 bool LoadedLR = false;1794 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {1795 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, ScratchReg)1796 .addImm(LROffset+SPAdd)1797 .addReg(RBReg);1798 LoadedLR = true;1799 }1800 1801 if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {1802 assert(RBReg == SPReg && "Should be using SP as a base register");1803 BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)1804 .addImm(CRSaveOffset)1805 .addReg(RBReg);1806 }1807 1808 if (HasFP) {1809 // If there is red zone, restore FP directly, since SP has already been1810 // restored. Otherwise, restore the value of FP into ScratchReg.1811 if (HasRedZone || RBReg == SPReg)1812 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)1813 .addImm(FPOffset)1814 .addReg(SPReg);1815 else1816 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)1817 .addImm(FPOffset)1818 .addReg(RBReg);1819 }1820 1821 if (FI->usesPICBase())1822 BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)1823 .addImm(PBPOffset)1824 .addReg(RBReg);1825 1826 if (HasBP)1827 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)1828 .addImm(BPOffset)1829 .addReg(RBReg);1830 1831 // There is nothing more to be loaded from the stack, so now we can1832 // restore SP: SP = RBReg + SPAdd.1833 if (RBReg != SPReg || SPAdd != 0) {1834 assert(!HasRedZone && "This should not happen with red zone");1835 // If SPAdd is 0, generate a copy.1836 if (SPAdd == 0)1837 BuildMI(MBB, MBBI, dl, OrInst, SPReg)1838 .addReg(RBReg)1839 .addReg(RBReg);1840 else1841 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)1842 .addReg(RBReg)1843 .addImm(SPAdd);1844 1845 assert(RBReg != ScratchReg && "Should be using FP or SP as base register");1846 if (RBReg == FPReg)1847 BuildMI(MBB, MBBI, dl, OrInst, FPReg)1848 .addReg(ScratchReg)1849 .addReg(ScratchReg);1850 1851 // Now load the LR from the caller's stack frame.1852 if (MustSaveLR && !LoadedLR)1853 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)1854 .addImm(LROffset)1855 .addReg(SPReg);1856 }1857 1858 if (MustSaveCR &&1859 !(SingleScratchReg && MustSaveLR))1860 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)1861 BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])1862 .addReg(TempReg, getKillRegState(i == e-1));1863 1864 if (MustSaveLR) {1865 // If ROP protection is required, an extra instruction is added to compute a1866 // hash and then compare it to the hash stored in the prologue.1867 if (HasROPProtect) {1868 const int SaveIndex = FI->getROPProtectionHashSaveIndex();1869 const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex);1870 assert((ImmOffset <= -8 && ImmOffset >= -512) &&1871 "ROP hash check location offset out of range.");1872 assert(((ImmOffset & 0x7) == 0) &&1873 "ROP hash check location offset must be 8 byte aligned.");1874 BuildMI(MBB, StackUpdateLoc, dl, HashChk)1875 .addReg(ScratchReg)1876 .addImm(ImmOffset)1877 .addReg(SPReg);1878 }1879 BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);1880 }1881 1882 // Callee pop calling convention. Pop parameter/linkage area. Used for tail1883 // call optimization1884 if (IsReturnBlock) {1885 unsigned RetOpcode = MBBI->getOpcode();1886 if (MF.getTarget().Options.GuaranteedTailCallOpt &&1887 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&1888 MF.getFunction().getCallingConv() == CallingConv::Fast) {1889 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();1890 unsigned CallerAllocatedAmt = FI->getMinReservedArea();1891 1892 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {1893 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)1894 .addReg(SPReg).addImm(CallerAllocatedAmt);1895 } else {1896 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)1897 .addImm(CallerAllocatedAmt >> 16);1898 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)1899 .addReg(ScratchReg, RegState::Kill)1900 .addImm(CallerAllocatedAmt & 0xFFFF);1901 BuildMI(MBB, MBBI, dl, AddInst)1902 .addReg(SPReg)1903 .addReg(FPReg)1904 .addReg(ScratchReg);1905 }1906 } else {1907 createTailCallBranchInstr(MBB);1908 }1909 }1910}1911 1912void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {1913 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();1914 1915 // If we got this far a first terminator should exist.1916 assert(MBBI != MBB.end() && "Failed to find the first terminator.");1917 1918 DebugLoc dl = MBBI->getDebugLoc();1919 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();1920 1921 // Create branch instruction for pseudo tail call return instruction.1922 // The TCRETURNdi variants are direct calls. Valid targets for those are1923 // MO_GlobalAddress operands as well as MO_ExternalSymbol with PC-Rel1924 // since we can tail call external functions with PC-Rel (i.e. we don't need1925 // to worry about different TOC pointers). Some of the external functions will1926 // be MO_GlobalAddress while others like memcpy for example, are going to1927 // be MO_ExternalSymbol.1928 unsigned RetOpcode = MBBI->getOpcode();1929 if (RetOpcode == PPC::TCRETURNdi) {1930 MBBI = MBB.getLastNonDebugInstr();1931 MachineOperand &JumpTarget = MBBI->getOperand(0);1932 if (JumpTarget.isGlobal())1933 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).1934 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());1935 else if (JumpTarget.isSymbol())1936 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).1937 addExternalSymbol(JumpTarget.getSymbolName());1938 else1939 llvm_unreachable("Expecting Global or External Symbol");1940 } else if (RetOpcode == PPC::TCRETURNri) {1941 MBBI = MBB.getLastNonDebugInstr();1942 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");1943 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));1944 } else if (RetOpcode == PPC::TCRETURNai) {1945 MBBI = MBB.getLastNonDebugInstr();1946 MachineOperand &JumpTarget = MBBI->getOperand(0);1947 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());1948 } else if (RetOpcode == PPC::TCRETURNdi8) {1949 MBBI = MBB.getLastNonDebugInstr();1950 MachineOperand &JumpTarget = MBBI->getOperand(0);1951 if (JumpTarget.isGlobal())1952 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).1953 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());1954 else if (JumpTarget.isSymbol())1955 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).1956 addExternalSymbol(JumpTarget.getSymbolName());1957 else1958 llvm_unreachable("Expecting Global or External Symbol");1959 } else if (RetOpcode == PPC::TCRETURNri8) {1960 MBBI = MBB.getLastNonDebugInstr();1961 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");1962 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));1963 } else if (RetOpcode == PPC::TCRETURNai8) {1964 MBBI = MBB.getLastNonDebugInstr();1965 MachineOperand &JumpTarget = MBBI->getOperand(0);1966 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());1967 }1968}1969 1970void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,1971 BitVector &SavedRegs,1972 RegScavenger *RS) const {1973 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);1974 if (Subtarget.isAIXABI())1975 updateCalleeSaves(MF, SavedRegs);1976 1977 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();1978 1979 // Do not explicitly save the callee saved VSRp registers.1980 // The individual VSR subregisters will be saved instead.1981 SavedRegs.reset(PPC::VSRp26);1982 SavedRegs.reset(PPC::VSRp27);1983 SavedRegs.reset(PPC::VSRp28);1984 SavedRegs.reset(PPC::VSRp29);1985 SavedRegs.reset(PPC::VSRp30);1986 SavedRegs.reset(PPC::VSRp31);1987 1988 // Save and clear the LR state.1989 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();1990 MCRegister LR = RegInfo->getRARegister();1991 FI->setMustSaveLR(MustSaveLR(MF, LR));1992 SavedRegs.reset(LR);1993 1994 // Save R31 if necessary1995 int FPSI = FI->getFramePointerSaveIndex();1996 const bool isPPC64 = Subtarget.isPPC64();1997 MachineFrameInfo &MFI = MF.getFrameInfo();1998 1999 // If the frame pointer save index hasn't been defined yet.2000 if (!FPSI && needsFP(MF)) {2001 // Find out what the fix offset of the frame pointer save area.2002 int FPOffset = getFramePointerSaveOffset();2003 // Allocate the frame index for frame pointer save area.2004 FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);2005 // Save the result.2006 FI->setFramePointerSaveIndex(FPSI);2007 }2008 2009 int BPSI = FI->getBasePointerSaveIndex();2010 if (!BPSI && RegInfo->hasBasePointer(MF)) {2011 int BPOffset = getBasePointerSaveOffset();2012 // Allocate the frame index for the base pointer save area.2013 BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);2014 // Save the result.2015 FI->setBasePointerSaveIndex(BPSI);2016 }2017 2018 // Reserve stack space for the PIC Base register (R30).2019 // Only used in SVR4 32-bit.2020 if (FI->usesPICBase()) {2021 int PBPSI = MFI.CreateFixedObject(4, -8, true);2022 FI->setPICBasePointerSaveIndex(PBPSI);2023 }2024 2025 // Make sure we don't explicitly spill r31, because, for example, we have2026 // some inline asm which explicitly clobbers it, when we otherwise have a2027 // frame pointer and are using r31's spill slot for the prologue/epilogue2028 // code. Same goes for the base pointer and the PIC base register.2029 if (needsFP(MF))2030 SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);2031 if (RegInfo->hasBasePointer(MF)) {2032 SavedRegs.reset(RegInfo->getBaseRegister(MF));2033 // On AIX, when BaseRegister(R30) is used, need to spill r31 too to match2034 // AIX trackback table requirement.2035 if (!needsFP(MF) && !SavedRegs.test(isPPC64 ? PPC::X31 : PPC::R31) &&2036 Subtarget.isAIXABI()) {2037 assert(2038 (RegInfo->getBaseRegister(MF) == (isPPC64 ? PPC::X30 : PPC::R30)) &&2039 "Invalid base register on AIX!");2040 SavedRegs.set(isPPC64 ? PPC::X31 : PPC::R31);2041 }2042 }2043 if (FI->usesPICBase())2044 SavedRegs.reset(PPC::R30);2045 2046 // Reserve stack space to move the linkage area to in case of a tail call.2047 int TCSPDelta = 0;2048 if (MF.getTarget().Options.GuaranteedTailCallOpt &&2049 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {2050 MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);2051 }2052 2053 // Allocate the nonvolatile CR spill slot iff the function uses CR 2, 3, or 4.2054 // For 64-bit SVR4, and all flavors of AIX we create a FixedStack2055 // object at the offset of the CR-save slot in the linkage area. The actual2056 // save and restore of the condition register will be created as part of the2057 // prologue and epilogue insertion, but the FixedStack object is needed to2058 // keep the CalleSavedInfo valid.2059 if ((SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||2060 SavedRegs.test(PPC::CR4))) {2061 const uint64_t SpillSize = 4; // Condition register is always 4 bytes.2062 const int64_t SpillOffset =2063 Subtarget.isPPC64() ? 8 : Subtarget.isAIXABI() ? 4 : -4;2064 int FrameIdx =2065 MFI.CreateFixedObject(SpillSize, SpillOffset,2066 /* IsImmutable */ true, /* IsAliased */ false);2067 FI->setCRSpillFrameIndex(FrameIdx);2068 }2069}2070 2071void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,2072 RegScavenger *RS) const {2073 // Get callee saved register information.2074 MachineFrameInfo &MFI = MF.getFrameInfo();2075 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();2076 2077 // If the function is shrink-wrapped, and if the function has a tail call, the2078 // tail call might not be in the new RestoreBlock, so real branch instruction2079 // won't be generated by emitEpilogue(), because shrink-wrap has chosen new2080 // RestoreBlock. So we handle this case here.2081 if (!MFI.getSavePoints().empty() && MFI.hasTailCall()) {2082 assert(MFI.getRestorePoints().size() < 2 &&2083 "MFI can't contain multiple restore points!");2084 for (MachineBasicBlock &MBB : MF) {2085 if (MBB.isReturnBlock() && (!MFI.getRestorePoints().contains(&MBB)))2086 createTailCallBranchInstr(MBB);2087 }2088 }2089 2090 // Early exit if no callee saved registers are modified!2091 if (CSI.empty() && !needsFP(MF)) {2092 addScavengingSpillSlot(MF, RS);2093 return;2094 }2095 2096 unsigned MinGPR = PPC::R31;2097 unsigned MinG8R = PPC::X31;2098 unsigned MinFPR = PPC::F31;2099 unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;2100 2101 bool HasGPSaveArea = false;2102 bool HasG8SaveArea = false;2103 bool HasFPSaveArea = false;2104 bool HasVRSaveArea = false;2105 2106 SmallVector<CalleeSavedInfo, 18> GPRegs;2107 SmallVector<CalleeSavedInfo, 18> G8Regs;2108 SmallVector<CalleeSavedInfo, 18> FPRegs;2109 SmallVector<CalleeSavedInfo, 18> VRegs;2110 2111 for (const CalleeSavedInfo &I : CSI) {2112 MCRegister Reg = I.getReg();2113 assert((!MF.getInfo<PPCFunctionInfo>()->mustSaveTOC() ||2114 (Reg != PPC::X2 && Reg != PPC::R2)) &&2115 "Not expecting to try to spill R2 in a function that must save TOC");2116 if (PPC::GPRCRegClass.contains(Reg)) {2117 HasGPSaveArea = true;2118 2119 GPRegs.push_back(I);2120 2121 if (Reg < MinGPR) {2122 MinGPR = Reg;2123 }2124 } else if (PPC::G8RCRegClass.contains(Reg)) {2125 HasG8SaveArea = true;2126 2127 G8Regs.push_back(I);2128 2129 if (Reg < MinG8R) {2130 MinG8R = Reg;2131 }2132 } else if (PPC::F8RCRegClass.contains(Reg)) {2133 HasFPSaveArea = true;2134 2135 FPRegs.push_back(I);2136 2137 if (Reg < MinFPR) {2138 MinFPR = Reg;2139 }2140 } else if (PPC::CRBITRCRegClass.contains(Reg) ||2141 PPC::CRRCRegClass.contains(Reg)) {2142 ; // do nothing, as we already know whether CRs are spilled2143 } else if (PPC::VRRCRegClass.contains(Reg) ||2144 PPC::SPERCRegClass.contains(Reg)) {2145 // Altivec and SPE are mutually exclusive, but have the same stack2146 // alignment requirements, so overload the save area for both cases.2147 HasVRSaveArea = true;2148 2149 VRegs.push_back(I);2150 2151 if (Reg < MinVR) {2152 MinVR = Reg;2153 }2154 } else {2155 llvm_unreachable("Unknown RegisterClass!");2156 }2157 }2158 2159 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();2160 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();2161 2162 int64_t LowerBound = 0;2163 2164 // Take into account stack space reserved for tail calls.2165 int TCSPDelta = 0;2166 if (MF.getTarget().Options.GuaranteedTailCallOpt &&2167 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {2168 LowerBound = TCSPDelta;2169 }2170 2171 // The Floating-point register save area is right below the back chain word2172 // of the previous stack frame.2173 if (HasFPSaveArea) {2174 for (const CalleeSavedInfo &FPReg : FPRegs) {2175 int FI = FPReg.getFrameIdx();2176 2177 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2178 }2179 2180 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;2181 }2182 2183 // Check whether the frame pointer register is allocated. If so, make sure it2184 // is spilled to the correct offset.2185 if (needsFP(MF)) {2186 int FI = PFI->getFramePointerSaveIndex();2187 assert(FI && "No Frame Pointer Save Slot!");2188 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2189 // FP is R31/X31, so no need to update MinGPR/MinG8R.2190 HasGPSaveArea = true;2191 }2192 2193 if (PFI->usesPICBase()) {2194 int FI = PFI->getPICBasePointerSaveIndex();2195 assert(FI && "No PIC Base Pointer Save Slot!");2196 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2197 2198 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);2199 HasGPSaveArea = true;2200 }2201 2202 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();2203 if (RegInfo->hasBasePointer(MF)) {2204 int FI = PFI->getBasePointerSaveIndex();2205 assert(FI && "No Base Pointer Save Slot!");2206 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2207 2208 Register BP = RegInfo->getBaseRegister(MF);2209 if (PPC::G8RCRegClass.contains(BP)) {2210 MinG8R = std::min<unsigned>(MinG8R, BP);2211 HasG8SaveArea = true;2212 } else if (PPC::GPRCRegClass.contains(BP)) {2213 MinGPR = std::min<unsigned>(MinGPR, BP);2214 HasGPSaveArea = true;2215 }2216 }2217 2218 // General register save area starts right below the Floating-point2219 // register save area.2220 if (HasGPSaveArea || HasG8SaveArea) {2221 // Move general register save area spill slots down, taking into account2222 // the size of the Floating-point register save area.2223 for (const CalleeSavedInfo &GPReg : GPRegs) {2224 if (!GPReg.isSpilledToReg()) {2225 int FI = GPReg.getFrameIdx();2226 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2227 }2228 }2229 2230 // Move general register save area spill slots down, taking into account2231 // the size of the Floating-point register save area.2232 for (const CalleeSavedInfo &G8Reg : G8Regs) {2233 if (!G8Reg.isSpilledToReg()) {2234 int FI = G8Reg.getFrameIdx();2235 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2236 }2237 }2238 2239 unsigned MinReg =2240 std::min<unsigned>(TRI->getEncodingValue(MinGPR),2241 TRI->getEncodingValue(MinG8R));2242 2243 const unsigned GPRegSize = Subtarget.isPPC64() ? 8 : 4;2244 LowerBound -= (31 - MinReg + 1) * GPRegSize;2245 }2246 2247 // For 32-bit only, the CR save area is below the general register2248 // save area. For 64-bit SVR4, the CR save area is addressed relative2249 // to the stack pointer and hence does not need an adjustment here.2250 // Only CR2 (the first nonvolatile spilled) has an associated frame2251 // index so that we have a single uniform save area.2252 if (spillsCR(MF) && Subtarget.is32BitELFABI()) {2253 // Adjust the frame index of the CR spill slot.2254 for (const auto &CSInfo : CSI) {2255 if (CSInfo.getReg() == PPC::CR2) {2256 int FI = CSInfo.getFrameIdx();2257 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2258 break;2259 }2260 }2261 2262 LowerBound -= 4; // The CR save area is always 4 bytes long.2263 }2264 2265 // Both Altivec and SPE have the same alignment and padding requirements2266 // within the stack frame.2267 if (HasVRSaveArea) {2268 // Insert alignment padding, we need 16-byte alignment. Note: for positive2269 // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since2270 // we are using negative number here (the stack grows downward). We should2271 // use formula : y = x & (~(n-1)). Where x is the size before aligning, n2272 // is the alignment size ( n = 16 here) and y is the size after aligning.2273 assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");2274 LowerBound &= ~(15);2275 2276 for (const CalleeSavedInfo &VReg : VRegs) {2277 int FI = VReg.getFrameIdx();2278 2279 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));2280 }2281 }2282 2283 addScavengingSpillSlot(MF, RS);2284}2285 2286void2287PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,2288 RegScavenger *RS) const {2289 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or2290 // a large stack, which will require scavenging a register to materialize a2291 // large offset.2292 2293 // We need to have a scavenger spill slot for spills if the frame size is2294 // large. In case there is no free register for large-offset addressing,2295 // this slot is used for the necessary emergency spill. Also, we need the2296 // slot for dynamic stack allocations.2297 2298 // The scavenger might be invoked if the frame offset does not fit into2299 // the 16-bit immediate in case of not SPE and 8-bit in case of SPE.2300 // We don't know the complete frame size here because we've not yet computed2301 // callee-saved register spills or the needed alignment padding.2302 unsigned StackSize = determineFrameLayout(MF, true);2303 MachineFrameInfo &MFI = MF.getFrameInfo();2304 bool NeedSpills = Subtarget.hasSPE() ? !isInt<8>(StackSize) : !isInt<16>(StackSize);2305 2306 if (MFI.hasVarSizedObjects() || spillsCR(MF) || hasNonRISpills(MF) ||2307 (hasSpills(MF) && NeedSpills)) {2308 const TargetRegisterClass &GPRC = PPC::GPRCRegClass;2309 const TargetRegisterClass &G8RC = PPC::G8RCRegClass;2310 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;2311 const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();2312 unsigned Size = TRI.getSpillSize(RC);2313 Align Alignment = TRI.getSpillAlign(RC);2314 RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));2315 2316 // Might we have over-aligned allocas?2317 bool HasAlVars =2318 MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();2319 2320 // These kinds of spills might need two registers.2321 if (spillsCR(MF) || HasAlVars)2322 RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));2323 }2324}2325 2326// This function checks if a callee saved gpr can be spilled to a volatile2327// vector register. This occurs for leaf functions when the option2328// ppc-enable-pe-vector-spills is enabled. If there are any remaining registers2329// which were not spilled to vectors, return false so the target independent2330// code can handle them by assigning a FrameIdx to a stack slot.2331bool PPCFrameLowering::assignCalleeSavedSpillSlots(2332 MachineFunction &MF, const TargetRegisterInfo *TRI,2333 std::vector<CalleeSavedInfo> &CSI) const {2334 2335 if (CSI.empty())2336 return true; // Early exit if no callee saved registers are modified!2337 2338 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();2339 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);2340 const MachineRegisterInfo &MRI = MF.getRegInfo();2341 2342 if (Subtarget.hasSPE()) {2343 // In case of SPE we only have SuperRegs and CRs2344 // in our CalleSaveInfo vector.2345 2346 for (auto &CalleeSaveReg : CSI) {2347 MCRegister Reg = CalleeSaveReg.getReg();2348 MCRegister Lower = RegInfo->getSubReg(Reg, PPC::sub_32);2349 MCRegister Higher = RegInfo->getSubReg(Reg, PPC::sub_32_hi_phony);2350 2351 if ( // Check only for SuperRegs.2352 Lower &&2353 // Replace Reg if only lower-32 bits modified2354 !MRI.isPhysRegModified(Higher))2355 CalleeSaveReg = CalleeSavedInfo(Lower);2356 }2357 }2358 2359 // Early exit if cannot spill gprs to volatile vector registers.2360 MachineFrameInfo &MFI = MF.getFrameInfo();2361 if (!EnablePEVectorSpills || MFI.hasCalls() || !Subtarget.hasP9Vector())2362 return false;2363 2364 // Build a BitVector of VSRs that can be used for spilling GPRs.2365 BitVector BVAllocatable = TRI->getAllocatableSet(MF);2366 BitVector BVCalleeSaved(TRI->getNumRegs());2367 for (unsigned i = 0; CSRegs[i]; ++i)2368 BVCalleeSaved.set(CSRegs[i]);2369 2370 for (unsigned Reg : BVAllocatable.set_bits()) {2371 // Set to 0 if the register is not a volatile VSX register, or if it is2372 // used in the function.2373 if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.contains(Reg) ||2374 MRI.isPhysRegUsed(Reg))2375 BVAllocatable.reset(Reg);2376 }2377 2378 bool AllSpilledToReg = true;2379 unsigned LastVSRUsedForSpill = 0;2380 for (auto &CS : CSI) {2381 if (BVAllocatable.none())2382 return false;2383 2384 MCRegister Reg = CS.getReg();2385 2386 if (!PPC::G8RCRegClass.contains(Reg)) {2387 AllSpilledToReg = false;2388 continue;2389 }2390 2391 // For P9, we can reuse LastVSRUsedForSpill to spill two GPRs2392 // into one VSR using the mtvsrdd instruction.2393 if (LastVSRUsedForSpill != 0) {2394 CS.setDstReg(LastVSRUsedForSpill);2395 BVAllocatable.reset(LastVSRUsedForSpill);2396 LastVSRUsedForSpill = 0;2397 continue;2398 }2399 2400 unsigned VolatileVFReg = BVAllocatable.find_first();2401 if (VolatileVFReg < BVAllocatable.size()) {2402 CS.setDstReg(VolatileVFReg);2403 LastVSRUsedForSpill = VolatileVFReg;2404 } else {2405 AllSpilledToReg = false;2406 }2407 }2408 return AllSpilledToReg;2409}2410 2411bool PPCFrameLowering::spillCalleeSavedRegisters(2412 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,2413 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {2414 2415 MachineFunction *MF = MBB.getParent();2416 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();2417 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();2418 bool MustSaveTOC = FI->mustSaveTOC();2419 DebugLoc DL;2420 bool CRSpilled = false;2421 MachineInstrBuilder CRMIB;2422 BitVector Spilled(TRI->getNumRegs());2423 2424 VSRContainingGPRs.clear();2425 2426 // Map each VSR to GPRs to be spilled with into it. Single VSR can contain one2427 // or two GPRs, so we need table to record information for later save/restore.2428 for (const CalleeSavedInfo &Info : CSI) {2429 if (Info.isSpilledToReg()) {2430 auto &SpilledVSR = VSRContainingGPRs[Info.getDstReg()];2431 assert(SpilledVSR.second == 0 &&2432 "Can't spill more than two GPRs into VSR!");2433 if (SpilledVSR.first == 0)2434 SpilledVSR.first = Info.getReg();2435 else2436 SpilledVSR.second = Info.getReg();2437 }2438 }2439 2440 for (const CalleeSavedInfo &I : CSI) {2441 MCRegister Reg = I.getReg();2442 2443 // CR2 through CR4 are the nonvolatile CR fields.2444 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;2445 2446 // Add the callee-saved register as live-in; it's killed at the spill.2447 // Do not do this for callee-saved registers that are live-in to the2448 // function because they will already be marked live-in and this will be2449 // adding it for a second time. It is an error to add the same register2450 // to the set more than once.2451 const MachineRegisterInfo &MRI = MF->getRegInfo();2452 bool IsLiveIn = MRI.isLiveIn(Reg);2453 if (!IsLiveIn)2454 MBB.addLiveIn(Reg);2455 2456 if (CRSpilled && IsCRField) {2457 CRMIB.addReg(Reg, RegState::ImplicitKill);2458 continue;2459 }2460 2461 // The actual spill will happen in the prologue.2462 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)2463 continue;2464 2465 // Insert the spill to the stack frame.2466 if (IsCRField) {2467 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();2468 if (!Subtarget.is32BitELFABI()) {2469 // The actual spill will happen at the start of the prologue.2470 FuncInfo->addMustSaveCR(Reg);2471 } else {2472 CRSpilled = true;2473 FuncInfo->setSpillsCR();2474 2475 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have2476 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.2477 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)2478 .addReg(Reg, RegState::ImplicitKill);2479 2480 MBB.insert(MI, CRMIB);2481 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))2482 .addReg(PPC::R12,2483 getKillRegState(true)),2484 I.getFrameIdx()));2485 }2486 } else {2487 if (I.isSpilledToReg()) {2488 unsigned Dst = I.getDstReg();2489 2490 if (Spilled[Dst])2491 continue;2492 2493 const auto &VSR = VSRContainingGPRs[Dst];2494 if (VSR.second != 0) {2495 assert(Subtarget.hasP9Vector() &&2496 "mtvsrdd is unavailable on pre-P9 targets.");2497 2498 NumPESpillVSR += 2;2499 BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRDD), Dst)2500 .addReg(VSR.first, getKillRegState(true))2501 .addReg(VSR.second, getKillRegState(true));2502 } else if (VSR.second == 0) {2503 assert(Subtarget.hasP8Vector() &&2504 "Can't move GPR to VSR on pre-P8 targets.");2505 2506 ++NumPESpillVSR;2507 BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD),2508 TRI->getSubReg(Dst, PPC::sub_64))2509 .addReg(VSR.first, getKillRegState(true));2510 } else {2511 llvm_unreachable("More than two GPRs spilled to a VSR!");2512 }2513 Spilled.set(Dst);2514 } else {2515 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);2516 // Use !IsLiveIn for the kill flag.2517 // We do not want to kill registers that are live in this function2518 // before their use because they will become undefined registers.2519 // Functions without NoUnwind need to preserve the order of elements in2520 // saved vector registers.2521 if (Subtarget.needsSwapsForVSXMemOps() &&2522 !MF->getFunction().hasFnAttribute(Attribute::NoUnwind))2523 TII.storeRegToStackSlotNoUpd(MBB, MI, Reg, !IsLiveIn, I.getFrameIdx(),2524 RC);2525 else2526 TII.storeRegToStackSlot(MBB, MI, Reg, !IsLiveIn, I.getFrameIdx(), RC,2527 Register());2528 }2529 }2530 }2531 return true;2532}2533 2534static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled,2535 bool CR4Spilled, MachineBasicBlock &MBB,2536 MachineBasicBlock::iterator MI,2537 ArrayRef<CalleeSavedInfo> CSI, unsigned CSIIndex) {2538 2539 MachineFunction *MF = MBB.getParent();2540 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();2541 DebugLoc DL;2542 unsigned MoveReg = PPC::R12;2543 2544 // 32-bit: FP-relative2545 MBB.insert(MI,2546 addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), MoveReg),2547 CSI[CSIIndex].getFrameIdx()));2548 2549 unsigned RestoreOp = PPC::MTOCRF;2550 if (CR2Spilled)2551 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)2552 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));2553 2554 if (CR3Spilled)2555 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)2556 .addReg(MoveReg, getKillRegState(!CR4Spilled)));2557 2558 if (CR4Spilled)2559 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)2560 .addReg(MoveReg, getKillRegState(true)));2561}2562 2563MachineBasicBlock::iterator PPCFrameLowering::2564eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,2565 MachineBasicBlock::iterator I) const {2566 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();2567 if (MF.getTarget().Options.GuaranteedTailCallOpt &&2568 I->getOpcode() == PPC::ADJCALLSTACKUP) {2569 // Add (actually subtract) back the amount the callee popped on return.2570 if (int CalleeAmt = I->getOperand(1).getImm()) {2571 bool is64Bit = Subtarget.isPPC64();2572 CalleeAmt *= -1;2573 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;2574 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;2575 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;2576 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;2577 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;2578 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;2579 const DebugLoc &dl = I->getDebugLoc();2580 2581 if (isInt<16>(CalleeAmt)) {2582 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)2583 .addReg(StackReg, RegState::Kill)2584 .addImm(CalleeAmt);2585 } else {2586 MachineBasicBlock::iterator MBBI = I;2587 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)2588 .addImm(CalleeAmt >> 16);2589 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)2590 .addReg(TmpReg, RegState::Kill)2591 .addImm(CalleeAmt & 0xFFFF);2592 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)2593 .addReg(StackReg, RegState::Kill)2594 .addReg(TmpReg);2595 }2596 }2597 }2598 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.2599 return MBB.erase(I);2600}2601 2602static bool isCalleeSavedCR(unsigned Reg) {2603 return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;2604}2605 2606bool PPCFrameLowering::restoreCalleeSavedRegisters(2607 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,2608 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {2609 MachineFunction *MF = MBB.getParent();2610 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();2611 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();2612 bool MustSaveTOC = FI->mustSaveTOC();2613 bool CR2Spilled = false;2614 bool CR3Spilled = false;2615 bool CR4Spilled = false;2616 unsigned CSIIndex = 0;2617 BitVector Restored(TRI->getNumRegs());2618 2619 // Initialize insertion-point logic; we will be restoring in reverse2620 // order of spill.2621 MachineBasicBlock::iterator I = MI, BeforeI = I;2622 bool AtStart = I == MBB.begin();2623 2624 if (!AtStart)2625 --BeforeI;2626 2627 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {2628 MCRegister Reg = CSI[i].getReg();2629 2630 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)2631 continue;2632 2633 // Restore of callee saved condition register field is handled during2634 // epilogue insertion.2635 if (isCalleeSavedCR(Reg) && !Subtarget.is32BitELFABI())2636 continue;2637 2638 if (Reg == PPC::CR2) {2639 CR2Spilled = true;2640 // The spill slot is associated only with CR2, which is the2641 // first nonvolatile spilled. Save it here.2642 CSIIndex = i;2643 continue;2644 } else if (Reg == PPC::CR3) {2645 CR3Spilled = true;2646 continue;2647 } else if (Reg == PPC::CR4) {2648 CR4Spilled = true;2649 continue;2650 } else {2651 // On 32-bit ELF when we first encounter a non-CR register after seeing at2652 // least one CR register, restore all spilled CRs together.2653 if (CR2Spilled || CR3Spilled || CR4Spilled) {2654 bool is31 = needsFP(*MF);2655 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled, MBB, I, CSI,2656 CSIIndex);2657 CR2Spilled = CR3Spilled = CR4Spilled = false;2658 }2659 2660 if (CSI[i].isSpilledToReg()) {2661 DebugLoc DL;2662 unsigned Dst = CSI[i].getDstReg();2663 2664 if (Restored[Dst])2665 continue;2666 2667 const auto &VSR = VSRContainingGPRs[Dst];2668 if (VSR.second != 0) {2669 assert(Subtarget.hasP9Vector());2670 NumPEReloadVSR += 2;2671 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRLD), VSR.second).addReg(Dst);2672 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), VSR.first)2673 .addReg(TRI->getSubReg(Dst, PPC::sub_64), getKillRegState(true));2674 } else if (VSR.second == 0) {2675 assert(Subtarget.hasP8Vector());2676 ++NumPEReloadVSR;2677 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), VSR.first)2678 .addReg(TRI->getSubReg(Dst, PPC::sub_64), getKillRegState(true));2679 } else {2680 llvm_unreachable("More than two GPRs spilled to a VSR!");2681 }2682 2683 Restored.set(Dst);2684 2685 } else {2686 // Default behavior for non-CR saves.2687 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);2688 2689 // Functions without NoUnwind need to preserve the order of elements in2690 // saved vector registers.2691 if (Subtarget.needsSwapsForVSXMemOps() &&2692 !MF->getFunction().hasFnAttribute(Attribute::NoUnwind))2693 TII.loadRegFromStackSlotNoUpd(MBB, I, Reg, CSI[i].getFrameIdx(), RC);2694 else2695 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), RC,2696 Register());2697 2698 assert(I != MBB.begin() &&2699 "loadRegFromStackSlot didn't insert any code!");2700 }2701 }2702 2703 // Insert in reverse order.2704 if (AtStart)2705 I = MBB.begin();2706 else {2707 I = BeforeI;2708 ++I;2709 }2710 }2711 2712 // If we haven't yet spilled the CRs, do so now.2713 if (CR2Spilled || CR3Spilled || CR4Spilled) {2714 assert(Subtarget.is32BitELFABI() &&2715 "Only set CR[2|3|4]Spilled on 32-bit SVR4.");2716 bool is31 = needsFP(*MF);2717 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled, MBB, I, CSI, CSIIndex);2718 }2719 2720 return true;2721}2722 2723uint64_t PPCFrameLowering::getTOCSaveOffset() const {2724 return TOCSaveOffset;2725}2726 2727uint64_t PPCFrameLowering::getFramePointerSaveOffset() const {2728 return FramePointerSaveOffset;2729}2730 2731uint64_t PPCFrameLowering::getBasePointerSaveOffset() const {2732 return BasePointerSaveOffset;2733}2734 2735bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {2736 if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())2737 return false;2738 return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();2739}2740 2741void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,2742 BitVector &SavedRegs) const {2743 // The AIX ABI uses traceback tables for EH which require that if callee-saved2744 // register N is used, all registers N-31 must be saved/restored.2745 // NOTE: The check for AIX is not actually what is relevant. Traceback tables2746 // on Linux have the same requirements. It is just that AIX is the only ABI2747 // for which we actually use traceback tables. If another ABI needs to be2748 // supported that also uses them, we can add a check such as2749 // Subtarget.usesTraceBackTables().2750 assert(Subtarget.isAIXABI() &&2751 "Function updateCalleeSaves should only be called for AIX.");2752 2753 // If there are no callee saves then there is nothing to do.2754 if (SavedRegs.none())2755 return;2756 2757 const MCPhysReg *CSRegs =2758 Subtarget.getRegisterInfo()->getCalleeSavedRegs(&MF);2759 MCPhysReg LowestGPR = PPC::R31;2760 MCPhysReg LowestG8R = PPC::X31;2761 MCPhysReg LowestFPR = PPC::F31;2762 MCPhysReg LowestVR = PPC::V31;2763 2764 // Traverse the CSRs twice so as not to rely on ascending ordering of2765 // registers in the array. The first pass finds the lowest numbered2766 // register and the second pass marks all higher numbered registers2767 // for spilling.2768 for (int i = 0; CSRegs[i]; i++) {2769 // Get the lowest numbered register for each class that actually needs2770 // to be saved.2771 MCPhysReg Cand = CSRegs[i];2772 if (!SavedRegs.test(Cand))2773 continue;2774 // When R2/X2 is a CSR and not used for passing arguments, it is allocated2775 // earlier than other volatile registers. R2/X2 is not contiguous with2776 // R13/X13 to R31/X31.2777 if (Cand == PPC::X2 || Cand == PPC::R2) {2778 SavedRegs.set(Cand);2779 continue;2780 }2781 2782 if (PPC::GPRCRegClass.contains(Cand) && Cand < LowestGPR)2783 LowestGPR = Cand;2784 else if (PPC::G8RCRegClass.contains(Cand) && Cand < LowestG8R)2785 LowestG8R = Cand;2786 else if ((PPC::F4RCRegClass.contains(Cand) ||2787 PPC::F8RCRegClass.contains(Cand)) &&2788 Cand < LowestFPR)2789 LowestFPR = Cand;2790 else if (PPC::VRRCRegClass.contains(Cand) && Cand < LowestVR)2791 LowestVR = Cand;2792 }2793 2794 for (int i = 0; CSRegs[i]; i++) {2795 MCPhysReg Cand = CSRegs[i];2796 if ((PPC::GPRCRegClass.contains(Cand) && Cand > LowestGPR) ||2797 (PPC::G8RCRegClass.contains(Cand) && Cand > LowestG8R) ||2798 ((PPC::F4RCRegClass.contains(Cand) ||2799 PPC::F8RCRegClass.contains(Cand)) &&2800 Cand > LowestFPR) ||2801 (PPC::VRRCRegClass.contains(Cand) && Cand > LowestVR))2802 SavedRegs.set(Cand);2803 }2804}2805 2806uint64_t PPCFrameLowering::getStackThreshold() const {2807 // On PPC64, we use `stux r1, r1, <scratch_reg>` to extend the stack;2808 // use `add r1, r1, <scratch_reg>` to release the stack frame.2809 // Scratch register contains a signed 64-bit number, which is negative2810 // when extending the stack and is positive when releasing the stack frame.2811 // To make `stux` and `add` paired, the absolute value of the number contained2812 // in the scratch register should be the same. Thus the maximum stack size2813 // is (2^63)-1, i.e., LONG_MAX.2814 if (Subtarget.isPPC64())2815 return LONG_MAX;2816 2817 return TargetFrameLowering::getStackThreshold();2818}2819