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1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the PowerPC 64-bit instructions. These patterns are used10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// 64-bit operands.16//17def tocentry : Operand<iPTR> {18 let MIOperandInfo = (ops i64imm:$imm);19}20def tlsreg : Operand<i64> {21 let EncoderMethod = "getTLSRegEncoding";22 let ParserMatchClass = PPCTLSRegOperand;23}24def tlsgd : Operand<i64> {}25def tlscall : Operand<i64> {26 let PrintMethod = "printTLSCall";27 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);28 let EncoderMethod = "getTLSCallEncoding";29}30 31//===----------------------------------------------------------------------===//32// 64-bit transformation functions.33//34 35def SHL64 : SDNodeXForm<imm, [{36 // Transformation function: 63 - imm37 return getI32Imm(63 - N->getZExtValue(), SDLoc(N));38}]>;39 40def SRL64 : SDNodeXForm<imm, [{41 // Transformation function: 64 - imm42 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))43 : getI32Imm(0, SDLoc(N));44}]>;45 46 47//===----------------------------------------------------------------------===//48// Calls.49//50 51let Interpretation64Bit = 1, isCodeGenOnly = 1 in {52let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {53 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in54 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,55 [(PPCretglue)]>, Requires<[IsPPC64]>;56 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {57 let isPredicable = 1 in58 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,59 []>,60 Requires<[IsPPC64]>;61 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),62 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,63 []>,64 Requires<[IsPPC64]>;65 66 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),67 "bcctr 12, $BI, 0", IIC_BrB, []>,68 Requires<[IsPPC64]>;69 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),70 "bcctr 4, $BI, 0", IIC_BrB, []>,71 Requires<[IsPPC64]>;72 }73}74 75let Defs = [LR8] in76 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,77 PPC970_Unit_BRU;78 79let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in {80 let Defs = [CTR8], Uses = [CTR8] in {81 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),82 "bdz $BD">;83 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),84 "bdnz $BD">;85 }86 87 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {88 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),89 "bdzlr", IIC_BrB, []>;90 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),91 "bdnzlr", IIC_BrB, []>;92 }93}94 95 96 97let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {98 // Convenient aliases for call instructions99 let Uses = [RM] in {100 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$LI),101 "bl $LI", IIC_BrB, []>; // See Pat patterns below.102 103 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$LI),104 "bl $LI", IIC_BrB, []>;105 106 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),107 "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>;108 }109 let Uses = [RM], isCodeGenOnly = 1 in {110 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,111 (outs), (ins calltarget:$LI),112 "bl $LI\n\tnop", IIC_BrB, []>;113 114 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,115 (outs), (ins tlscall:$LI),116 "bl $LI\n\tnop", IIC_BrB, []>;117 118 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,119 (outs), (ins abscalltarget:$LI),120 "bla $LI\n\tnop", IIC_BrB,121 [(PPCcall_nop (i64 imm:$LI))]>;122 let Predicates = [PCRelativeMemops] in {123 // BL8_NOTOC means that the caller does not use the TOC pointer and if124 // it does use R2 then it is just a caller saved register. Therefore it is125 // safe to emit only the bl and not the nop for this instruction. The126 // linker will not try to restore R2 after the call.127 def BL8_NOTOC : IForm<18, 0, 1, (outs),128 (ins calltarget:$LI),129 "bl $LI", IIC_BrB, []>;130 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs),131 (ins tlscall:$LI),132 "bl $LI", IIC_BrB, []>;133 }134 }135 let Uses = [CTR8, RM] in {136 let isPredicable = 1 in137 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),138 "bctrl", IIC_BrB, [(PPCbctrl)]>,139 Requires<[IsPPC64]>;140 141 let isCodeGenOnly = 1 in {142 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),143 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,144 []>,145 Requires<[IsPPC64]>;146 147 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),148 "bcctrl 12, $BI, 0", IIC_BrB, []>,149 Requires<[IsPPC64]>;150 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),151 "bcctrl 4, $BI, 0", IIC_BrB, []>,152 Requires<[IsPPC64]>;153 }154 }155}156 157let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,158 isCodeGenOnly = 1, Uses = [RM] in {159 // Convenient aliases for call instructions160 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI),161 "bl $LI", IIC_BrB, []>; // See Pat patterns below.162 163 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),164 "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>;165 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24,166 (outs), (ins calltarget:$LI),167 "bl $LI\n\tnop", IIC_BrB, []>;168 169 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24,170 (outs), (ins abscalltarget:$LI),171 "bla $LI\n\tnop", IIC_BrB,172 [(PPCcall_nop_rm (i64 imm:$LI))]>;173 let Predicates = [PCRelativeMemops] in {174 // BL8_NOTOC means that the caller does not use the TOC pointer and if175 // it does use R2 then it is just a caller saved register. Therefore it is176 // safe to emit only the bl and not the nop for this instruction. The177 // linker will not try to restore R2 after the call.178 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs),179 (ins calltarget:$LI),180 "bl $LI", IIC_BrB, []>;181 }182 let Uses = [CTR8, RM] in {183 let isPredicable = 1 in184 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),185 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>,186 Requires<[IsPPC64]>;187 }188}189 190let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,191 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {192 def BCTRL8_LDinto_toc :193 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),194 (ins (memrix $D, $RA):$src),195 "bctrl\n\tld 2, $src", IIC_BrB,196 [(PPCbctrl_load_toc iaddrX4:$src)]>,197 Requires<[IsPPC64]>;198}199 200let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,201 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in {202 def BCTRL8_LDinto_toc_RM :203 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),204 (ins (memrix $D, $RA):$src),205 "bctrl\n\tld 2, $src", IIC_BrB,206 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>,207 Requires<[IsPPC64]>;208}209 210} // Interpretation64Bit211 212// FIXME: Duplicating this for the asm parser should be unnecessary, but the213// previous definition must be marked as CodeGen only to prevent decoding214// conflicts.215let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in216let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in217def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI),218 "bl $LI", IIC_BrB, []>;219 220// Calls221def : Pat<(PPCcall (i64 tglobaladdr:$dst)),222 (BL8 tglobaladdr:$dst)>;223def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),224 (BL8_NOP tglobaladdr:$dst)>;225 226def : Pat<(PPCcall (i64 texternalsym:$dst)),227 (BL8 texternalsym:$dst)>;228def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),229 (BL8_NOP texternalsym:$dst)>;230 231def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)),232 (BL8_NOTOC tglobaladdr:$dst)>;233def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)),234 (BL8_NOTOC texternalsym:$dst)>;235 236def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)),237 (BL8_RM tglobaladdr:$dst)>;238def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)),239 (BL8_NOP_RM tglobaladdr:$dst)>;240 241def : Pat<(PPCcall_rm (i64 texternalsym:$dst)),242 (BL8_RM texternalsym:$dst)>;243def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)),244 (BL8_NOP_RM texternalsym:$dst)>;245 246def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)),247 (BL8_NOTOC_RM tglobaladdr:$dst)>;248def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)),249 (BL8_NOTOC_RM texternalsym:$dst)>;250 251// Calls for AIX252def : Pat<(PPCcall (i64 mcsym:$dst)),253 (BL8 mcsym:$dst)>;254def : Pat<(PPCcall_nop (i64 mcsym:$dst)),255 (BL8_NOP mcsym:$dst)>;256 257def : Pat<(PPCcall_rm (i64 mcsym:$dst)),258 (BL8_RM mcsym:$dst)>;259def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)),260 (BL8_NOP_RM mcsym:$dst)>;261 262// Atomic operations263// FIXME: some of these might be used with constant operands. This will result264// in constant materialization instructions that may be redundant. We currently265// clean this up in PPCMIPeephole with calls to266// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them267// in the first place.268let Defs = [CR0] in {269 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo<270 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",271 [(set i64:$dst, (atomic_load_add_i64 ForceXForm:$ptr, i64:$incr))]>;272 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo<273 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",274 [(set i64:$dst, (atomic_load_sub_i64 ForceXForm:$ptr, i64:$incr))]>;275 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo<276 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",277 [(set i64:$dst, (atomic_load_or_i64 ForceXForm:$ptr, i64:$incr))]>;278 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo<279 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",280 [(set i64:$dst, (atomic_load_xor_i64 ForceXForm:$ptr, i64:$incr))]>;281 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo<282 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",283 [(set i64:$dst, (atomic_load_and_i64 ForceXForm:$ptr, i64:$incr))]>;284 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo<285 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",286 [(set i64:$dst, (atomic_load_nand_i64 ForceXForm:$ptr, i64:$incr))]>;287 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo<288 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",289 [(set i64:$dst, (atomic_load_min_i64 ForceXForm:$ptr, i64:$incr))]>;290 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo<291 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",292 [(set i64:$dst, (atomic_load_max_i64 ForceXForm:$ptr, i64:$incr))]>;293 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo<294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",295 [(set i64:$dst, (atomic_load_umin_i64 ForceXForm:$ptr, i64:$incr))]>;296 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo<297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",298 [(set i64:$dst, (atomic_load_umax_i64 ForceXForm:$ptr, i64:$incr))]>;299 300 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo<301 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",302 [(set i64:$dst, (atomic_cmp_swap_i64 ForceXForm:$ptr, i64:$old, i64:$new))]>;303 304 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo<305 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",306 [(set i64:$dst, (atomic_swap_i64 ForceXForm:$ptr, i64:$new))]>;307}308 309// Instructions to support atomic operations310let mayLoad = 1, hasSideEffects = 0 in {311def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),312 "ldarx $RST, $addr", IIC_LdStLDARX, []>;313// TODO: Add scheduling info.314let hasNoSchedulingInfo = 1 in315def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),316 "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64;317 318// Instruction to support lock versions of atomics319// (EH=1 - see Power ISA 2.07 Book II 4.4.2)320def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),321 "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm;322// TODO: Add scheduling info.323let hasNoSchedulingInfo = 1 in324// FIXME: We have to seek a way to remove isRecordForm since325// LQARXL is not really altering CR0.326def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),327 "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>,328 isPPC64, isRecordForm;329 330let hasExtraDefRegAllocReq = 1 in331def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB),332 "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64,333 Requires<[IsISA3_0]>;334}335 336let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {337def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),338 "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm;339// TODO: Add scheduling info.340let hasNoSchedulingInfo = 1 in341def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr),342 "stqcx. $RST, $addr", IIC_LdStSTQCX, []>,343 isPPC64, isRecordForm;344}345 346def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi),347 (ins g8prc:$src),348 "#SPLIT_QUADWORD", []>;349class AtomicRMW128<string asmstr>350 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch),351 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi),352 asmstr, []>;353// We have to keep values in MI's uses during LL/SC looping as they are,354// so set both $RTp and $scratch earlyclobber.355let mayStore = 1, mayLoad = 1,356 Defs = [CR0],357 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in {358// Atomic pseudo instructions expanded post-ra.359def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">;360def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">;361def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">;362def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">;363def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">;364def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">;365def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">;366 367def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo<368 (outs g8prc:$RTp, g8prc:$scratch),369 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi,370 g8rc:$new_lo, g8rc:$new_hi),371 "#ATOMIC_CMP_SWAP_I128", []>;372}373 374class PatAtomicRMWI128<SDPatternOperator OpNode, AtomicRMW128 Inst> :375 Pat<(OpNode ForceXForm:$ptr,376 i64:$incr_lo,377 i64:$incr_hi),378 (SPLIT_QUADWORD (Inst memrr:$ptr,379 g8rc:$incr_lo,380 g8rc:$incr_hi))>;381 382def : PatAtomicRMWI128<int_ppc_atomicrmw_add_i128, ATOMIC_LOAD_ADD_I128>;383def : PatAtomicRMWI128<int_ppc_atomicrmw_sub_i128, ATOMIC_LOAD_SUB_I128>;384def : PatAtomicRMWI128<int_ppc_atomicrmw_xor_i128, ATOMIC_LOAD_XOR_I128>;385def : PatAtomicRMWI128<int_ppc_atomicrmw_and_i128, ATOMIC_LOAD_AND_I128>;386def : PatAtomicRMWI128<int_ppc_atomicrmw_nand_i128, ATOMIC_LOAD_NAND_I128>;387def : PatAtomicRMWI128<int_ppc_atomicrmw_or_i128, ATOMIC_LOAD_OR_I128>;388def : PatAtomicRMWI128<int_ppc_atomicrmw_xchg_i128, ATOMIC_SWAP_I128>;389def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr,390 i64:$cmp_lo,391 i64:$cmp_hi,392 i64:$new_lo,393 i64:$new_hi),394 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128395 memrr:$ptr,396 g8rc:$cmp_lo,397 g8rc:$cmp_hi,398 g8rc:$new_lo,399 g8rc:$new_hi))>;400 401let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in402def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB),403 "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64,404 Requires<[IsISA3_0]>;405 406let Interpretation64Bit = 1, isCodeGenOnly = 1 in {407let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in408def TCRETURNdi8 :PPCEmitTimePseudo< (outs),409 (ins calltarget:$dst, i32imm:$offset),410 "#TC_RETURNd8 $dst $offset",411 []>;412 413let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in414def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),415 "#TC_RETURNa8 $func $offset",416 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;417 418let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in419def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),420 "#TC_RETURNr8 $dst $offset",421 []>;422 423let hasSideEffects = 0 in {424let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,425 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in426def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,427 []>,428 Requires<[IsPPC64]>;429 430let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,431 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in432def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$LI),433 "b $LI", IIC_BrB,434 []>;435 436let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,437 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in438def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI),439 "ba $LI", IIC_BrB,440 []>;441}442} // Interpretation64Bit443 444def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),445 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;446 447def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),448 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;449 450def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),451 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;452 453 454// 64-bit CR instructions455let Interpretation64Bit = 1, isCodeGenOnly = 1 in {456let hasSideEffects = 0 in {457// mtocrf's input needs to be prepared by shifting by an amount dependent458// on the cr register selected. Thus, post-ra anti-dep breaking must not459// later change that register assignment.460let hasExtraDefRegAllocReq = 1 in {461def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST),462 "mtocrf $FXM, $RST", IIC_BrMCRX>,463 PPC970_DGroup_First, PPC970_Unit_CRU;464 465// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that466// is dependent on the cr fields being set.467def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST),468 "mtcrf $FXM, $RST", IIC_BrMCRX>,469 PPC970_MicroCode, PPC970_Unit_CRU;470} // hasExtraDefRegAllocReq = 1471 472// mfocrf's input needs to be prepared by shifting by an amount dependent473// on the cr register selected. Thus, post-ra anti-dep breaking must not474// later change that register assignment.475let hasExtraSrcRegAllocReq = 1 in {476def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM),477 "mfocrf $RST, $FXM", IIC_SprMFCRF>,478 PPC970_DGroup_First, PPC970_Unit_CRU;479 480// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that481// is dependent on the cr fields being copied.482def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins),483 "mfcr $RT", IIC_SprMFCR>,484 PPC970_MicroCode, PPC970_Unit_CRU;485} // hasExtraSrcRegAllocReq = 1486} // hasSideEffects = 0487 488// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp489// is not.490let hasSideEffects = 1 in {491 let Defs = [CTR8] in492 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),493 "#EH_SJLJ_SETJMP64",494 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,495 Requires<[IsPPC64]>;496}497 498let hasSideEffects = 1, isBarrier = 1 in {499 let isTerminator = 1 in500 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),501 "#EH_SJLJ_LONGJMP64",502 [(PPCeh_sjlj_longjmp addr:$buf)]>,503 Requires<[IsPPC64]>;504}505 506def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),507 "mfspr $RST, $SPR", IIC_SprMFSPR>;508def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST),509 "mtspr $SPR, $RST", IIC_SprMTSPR>;510 511 512//===----------------------------------------------------------------------===//513// 64-bit SPR manipulation instrs.514 515let Uses = [CTR8] in {516def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins),517 "mfctr $RST", IIC_SprMFSPR>,518 PPC970_DGroup_First, PPC970_Unit_FXU;519}520let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in {521def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),522 "mtctr $RST", IIC_SprMTSPR>,523 PPC970_DGroup_First, PPC970_Unit_FXU;524}525// MTCTR[8|]loop must be inside a loop-preheader, duplicating526// the loop-preheader block will break this assumption.527let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in {528let Pattern = [(int_set_loop_iterations i64:$RST)] in529def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),530 "mtctr $RST", IIC_SprMTSPR>,531 PPC970_DGroup_First, PPC970_Unit_FXU;532}533 534let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in535def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride),536 "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>;537 538let Pattern = [(set i64:$RST, readcyclecounter)] in539def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins),540 "mfspr $RST, 268", IIC_SprMFTB>,541 PPC970_DGroup_First, PPC970_Unit_FXU;542// Note that encoding mftb using mfspr is now the preferred form,543// and has been since at least ISA v2.03. The mftb instruction has544// now been phased out. Using mfspr, however, is known not to work on545// the POWER3.546 547let Defs = [X1], Uses = [X1] in548def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",549 [(set i64:$result,550 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;551def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",552 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;553// Probed alloca to support stack clash protection.554let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in {555def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result),556 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64",557 [(set i64:$result,558 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>;559def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs560 g8rc:$fp, g8rc:$actual_negsize),561 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>;562def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs563 g8rc:$fp, g8rc:$actual_negsize),564 (ins g8rc:$negsize, memri:$fpsi),565 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>,566 RegConstraint<"$actual_negsize = $negsize">;567def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp),568 (ins i64imm:$stacksize),569 "#PROBED_STACKALLOC_64", []>;570}571 572let hasSideEffects = 0 in {573let Defs = [LR8] in {574def MTLR8 : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST),575 "mtlr $RST", IIC_SprMTSPR>,576 PPC970_DGroup_First, PPC970_Unit_FXU;577}578let Uses = [LR8] in {579def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins),580 "mflr $RST", IIC_SprMFSPR>,581 PPC970_DGroup_First, PPC970_Unit_FXU;582}583} // Interpretation64Bit584}585 586//===----------------------------------------------------------------------===//587// Fixed point instructions.588//589 590let PPC970_Unit = 1 in { // FXU Operations.591let Interpretation64Bit = 1 in {592let hasSideEffects = 0 in {593let isCodeGenOnly = 1 in {594 595let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {596def LI8 : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D),597 "li $RST, $D", IIC_IntSimple,598 [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64;599def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D),600 "lis $RST, $D", IIC_IntSimple,601 [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64;602}603 604// Logical ops.605let isCommutable = 1 in {606defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),607 "nand", "$RA, $RST, $RB", IIC_IntSimple,608 [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>;609defm AND8 : XForm_6r<31, 28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),610 "and", "$RA, $RST, $RB", IIC_IntSimple,611 [(set i64:$RA, (and i64:$RST, i64:$RB))]>;612} // isCommutable613defm ANDC8: XForm_6r<31, 60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),614 "andc", "$RA, $RST, $RB", IIC_IntSimple,615 [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>;616let isCommutable = 1 in {617defm OR8 : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),618 "or", "$RA, $RST, $RB", IIC_IntSimple,619 [(set i64:$RA, (or i64:$RST, i64:$RB))]>;620defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),621 "nor", "$RA, $RST, $RB", IIC_IntSimple,622 [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>;623} // isCommutable624defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),625 "orc", "$RA, $RST, $RB", IIC_IntSimple,626 [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>;627let isCommutable = 1 in {628defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),629 "eqv", "$RA, $RST, $RB", IIC_IntSimple,630 [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>;631defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),632 "xor", "$RA, $RST, $RB", IIC_IntSimple,633 [(set i64:$RA, (xor i64:$RST, i64:$RB))]>;634} // let isCommutable = 1635 636// Logical ops with immediate.637let Defs = [CR0] in {638def ANDI8_rec : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),639 "andi. $RA, $RST, $D", IIC_IntGeneral,640 [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>,641 isRecordForm, SExt32To64, ZExt32To64;642def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),643 "andis. $RA, $RST, $D", IIC_IntGeneral,644 [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>,645 isRecordForm, ZExt32To64;646}647def ORI8 : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),648 "ori $RA, $RST, $D", IIC_IntSimple,649 [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>;650def ORIS8 : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),651 "oris $RA, $RST, $D", IIC_IntSimple,652 [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>;653def XORI8 : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),654 "xori $RA, $RST, $D", IIC_IntSimple,655 [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>;656def XORIS8 : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),657 "xoris $RA, $RST, $D", IIC_IntSimple,658 [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>;659 660let isCommutable = 1 in661defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),662 "add", "$RT, $RA, $RB", IIC_IntSimple,663 [(set i64:$RT, (add i64:$RA, i64:$RB))]>;664// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the665// initial-exec thread-local storage model. We need to forbid r0 here -666// while it works for add just fine, the linker can relax this to local-exec667// addi, which won't work for r0.668def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB),669 "add $RT, $RA, $RB", IIC_IntSimple,670 [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>;671let mayLoad = 1 in {672def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),673 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;674def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),675 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;676def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),677 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;678def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),679 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;680def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),681 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;682def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),683 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;684def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),685 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;686def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),687 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;688def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),689 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;690def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),691 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;692def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),693 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;694 695}696let mayLoad = 1, Predicates = [HasFPU] in {697def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),698 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;699def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),700 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;701}702 703let mayStore = 1 in {704def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),705 "stbx $RST, $RA, $RB", IIC_LdStStore, []>,706 PPC970_DGroup_Cracked;707def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),708 "sthx $RST, $RA, $RB", IIC_LdStStore, []>,709 PPC970_DGroup_Cracked;710def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),711 "stwx $RST, $RA, $RB", IIC_LdStStore, []>,712 PPC970_DGroup_Cracked;713def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),714 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,715 PPC970_DGroup_Cracked;716def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),717 "stbx $RST, $RA, $RB", IIC_LdStStore, []>,718 PPC970_DGroup_Cracked;719def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),720 "sthx $RST, $RA, $RB", IIC_LdStStore, []>,721 PPC970_DGroup_Cracked;722def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),723 "stwx $RST, $RA, $RB", IIC_LdStStore, []>,724 PPC970_DGroup_Cracked;725 726}727let mayStore = 1, Predicates = [HasFPU] in {728def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),729 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,730 PPC970_DGroup_Cracked;731def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),732 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,733 PPC970_DGroup_Cracked;734}735 736let isCommutable = 1 in737defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),738 "addc", "$RT, $RA, $RB", IIC_IntGeneral,739 [(set i64:$RT, (PPCaddc i64:$RA, i64:$RB))]>,740 PPC970_DGroup_Cracked;741 742let Defs = [CARRY] in743def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),744 "addic $RST, $RA, $D", IIC_IntGeneral,745 [(set i64:$RST, (PPCaddc i64:$RA, imm64SExt16:$D))]>;746def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),747 "addi $RST, $RA, $D", IIC_IntSimple,748 [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>;749def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D),750 "addis $RST, $RA, $D", IIC_IntSimple,751 [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>;752 753def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),754 "la $RST, $D($RA)", IIC_IntGeneral,755 [(set i64:$RST, (add i64:$RA,756 (PPClo tglobaladdr:$D, 0)))]>, MemriOp;757 758let Defs = [CARRY] in {759def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),760 "subfic $RST, $RA, $D", IIC_IntGeneral,761 [(set i64:$RST, (PPCsubc imm64SExt16:$D, i64:$RA))]>;762}763defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),764 "subfc", "$RT, $RA, $RB", IIC_IntGeneral,765 [(set i64:$RT, (PPCsubc i64:$RB, i64:$RA))]>,766 PPC970_DGroup_Cracked;767defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),768 "subf", "$RT, $RA, $RB", IIC_IntGeneral,769 [(set i64:$RT, (sub i64:$RB, i64:$RA))]>;770defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA),771 "neg", "$RT, $RA", IIC_IntSimple,772 [(set i64:$RT, (ineg i64:$RA))]>;773let Uses = [CARRY] in {774let isCommutable = 1 in775defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),776 "adde", "$RT, $RA, $RB", IIC_IntGeneral,777 [(set i64:$RT, (PPCadde i64:$RA, i64:$RB, CARRY))]>;778defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),779 "addme", "$RT, $RA", IIC_IntGeneral,780 [(set i64:$RT, (PPCadde i64:$RA, -1, CARRY))]>;781defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),782 "addze", "$RT, $RA", IIC_IntGeneral,783 [(set i64:$RT, (PPCadde i64:$RA, 0, CARRY))]>;784defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),785 "subfe", "$RT, $RA, $RB", IIC_IntGeneral,786 [(set i64:$RT, (PPCsube i64:$RB, i64:$RA, CARRY))]>;787defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),788 "subfme", "$RT, $RA", IIC_IntGeneral,789 [(set i64:$RT, (PPCsube -1, i64:$RA, CARRY))]>;790defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),791 "subfze", "$RT, $RA", IIC_IntGeneral,792 [(set i64:$RT, (PPCsube 0, i64:$RA, CARRY))]>;793}794} // isCodeGenOnly795 796// FIXME: Duplicating this for the asm parser should be unnecessary, but the797// previous definition must be marked as CodeGen only to prevent decoding798// conflicts.799let isAsmParserOnly = 1 in {800def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB),801 "add $RT, $RA, $RB", IIC_IntSimple, []>;802 803let mayLoad = 1 in {804def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),805 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;806def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),807 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;808def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),809 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;810def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),811 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;812def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),813 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;814def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),815 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;816}817 818let mayLoad = 1, Predicates = [HasFPU] in {819def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),820 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;821def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),822 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;823}824 825let mayStore = 1 in {826def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),827 "stbx $RST, $RA, $RB", IIC_LdStStore, []>,828 PPC970_DGroup_Cracked;829def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),830 "sthx $RST, $RA, $RB", IIC_LdStStore, []>,831 PPC970_DGroup_Cracked;832def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),833 "stwx $RST, $RA, $RB", IIC_LdStStore, []>,834 PPC970_DGroup_Cracked;835def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),836 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,837 PPC970_DGroup_Cracked;838}839 840let mayStore = 1, Predicates = [HasFPU] in {841def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),842 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,843 PPC970_DGroup_Cracked;844def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),845 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,846 PPC970_DGroup_Cracked;847}848}849 850let isCommutable = 1 in {851defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),852 "mulhd", "$RT, $RA, $RB", IIC_IntMulHW,853 [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>;854defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),855 "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU,856 [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>;857} // isCommutable858}859} // Interpretation64Bit860 861let isCompare = 1, hasSideEffects = 0 in {862 def CMPD : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),863 "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64;864 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),865 "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64;866 def CMPDI : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D),867 "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64;868 def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D),869 "cmpldi $BF, $RA, $D",870 IIC_IntCompare>, isPPC64;871 let Interpretation64Bit = 1, isCodeGenOnly = 1 in872 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF),873 (ins u1imm:$L, g8rc:$RA, g8rc:$RB),874 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>,875 Requires<[IsISA3_0]>;876 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF),877 (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB",878 IIC_IntCompare, []>, Requires<[IsISA3_0]>;879}880 881let hasSideEffects = 0 in {882defm SLD : XForm_6r<31, 27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),883 "sld", "$RA, $RST, $RB", IIC_IntRotateD,884 [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64;885defm SRD : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),886 "srd", "$RA, $RST, $RB", IIC_IntRotateD,887 [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64;888defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),889 "srad", "$RA, $RST, $RB", IIC_IntRotateD,890 [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64;891 892let Interpretation64Bit = 1, isCodeGenOnly = 1 in {893defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$RA), (ins g8rc:$RST),894 "cntlzw", "$RA, $RST", IIC_IntGeneral, []>,895 ZExt32To64, SExt32To64;896defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST),897 "cnttzw", "$RA, $RST", IIC_IntGeneral, []>,898 Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;899 900defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST),901 "extsb", "$RA, $RST", IIC_IntSimple,902 [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64;903defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST),904 "extsh", "$RA, $RST", IIC_IntSimple,905 [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64;906 907defm SLW8 : XForm_6r<31, 24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),908 "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;909defm SRW8 : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),910 "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;911 912defm SRAW8 : XForm_6rc<31, 792, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),913 "sraw", "$RA, $RST, $RB", IIC_IntShift,914 []>, SExt32To64;915 916defm SRAWI8 : XForm_10rc<31, 824, (outs g8rc:$RA), (ins g8rc:$RST, u5imm:$RB),917 "srawi", "$RA, $RST, $RB", IIC_IntShift, []>, SExt32To64;918 919} // Interpretation64Bit920 921// For fast-isel:922let isCodeGenOnly = 1 in {923def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST),924 "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64,925 SExt32To64;926def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST),927 "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64,928 SExt32To64;929} // isCodeGenOnly for fast-isel930 931defm EXTSW : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST),932 "extsw", "$RA, $RST", IIC_IntSimple,933 [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64,934 SExt32To64;935let Interpretation64Bit = 1, isCodeGenOnly = 1 in936defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST),937 "extsw", "$RA, $RST", IIC_IntSimple,938 [(set i64:$RA, (sext i32:$RST))]>, isPPC64,939 SExt32To64;940let isCodeGenOnly = 1 in941def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST),942 "extsw $RA, $RST", IIC_IntSimple,943 []>, isPPC64;944 945defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),946 "sradi", "$RA, $RS, $SH", IIC_IntRotateDI,947 [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64;948 949let Interpretation64Bit = 1, isCodeGenOnly = 1 in950defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA),951 (ins gprc:$RS, u6imm:$SH),952 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,953 [(set i64:$RA,954 (PPCextswsli i32:$RS, (i32 imm:$SH)))]>,955 isPPC64, Requires<[IsISA3_0]>;956 957defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),958 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,959 []>, isPPC64, Requires<[IsISA3_0]>;960 961// For fast-isel:962let isCodeGenOnly = 1, Defs = [CARRY] in963def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH),964 "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64;965 966defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$RA), (ins g8rc:$RST),967 "cntlzd", "$RA, $RST", IIC_IntGeneral,968 [(set i64:$RA, (ctlz i64:$RST))]>,969 ZExt32To64, SExt32To64;970defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST),971 "cnttzd", "$RA, $RST", IIC_IntGeneral,972 [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>,973 ZExt32To64, SExt32To64;974def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST),975 "popcntd $RA, $RST", IIC_IntGeneral,976 [(set i64:$RA, (ctpop i64:$RST))]>,977 ZExt32To64, SExt32To64;978def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),979 "bpermd $RA, $RST, $RB", IIC_IntGeneral,980 [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>,981 isPPC64, Requires<[HasBPERMD]>;982 983let isCodeGenOnly = 1, isCommutable = 1 in984def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),985 "cmpb $RA, $RST, $RB", IIC_IntGeneral,986 [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>;987 988// popcntw also does a population count on the high 32 bits (storing the989// results in the high 32-bits of the output). We'll ignore that here (which is990// safe because we never separately use the high part of the 64-bit registers).991def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST),992 "popcntw $RA, $RST", IIC_IntGeneral,993 [(set i32:$RA, (ctpop i32:$RST))]>;994 995let isCodeGenOnly = 1 in {996def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),997 "popcntb $RA, $RST", IIC_IntGeneral,998 [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;999 1000def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST),1001 "cdtbcd $RA, $RST", IIC_IntGeneral,1002 [(set i64:$RA, (int_ppc_cdtbcdd i64:$RST))]>;1003def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST),1004 "cbcdtd $RA, $RST", IIC_IntGeneral,1005 [(set i64:$RA, (int_ppc_cbcdtdd i64:$RST))]>;1006def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1007 "addg6s $RT, $RA, $RB", IIC_IntGeneral,1008 [(set i64:$RT, (int_ppc_addg6sd i64:$RA, i64:$RB))]>;1009}1010 1011defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1012 "divd", "$RT, $RA, $RB", IIC_IntDivD,1013 [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64;1014defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1015 "divdu", "$RT, $RA, $RB", IIC_IntDivD,1016 [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64;1017defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1018 "divde", "$RT, $RA, $RB", IIC_IntDivD,1019 [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>,1020 isPPC64, Requires<[HasExtDiv]>;1021 1022let Predicates = [IsISA3_0] in {1023def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),1024 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;1025def MADDHDU : VAForm_1a<49,1026 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),1027 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;1028def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),1029 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,1030 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>,1031 isPPC64;1032let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1033 def MADDLD8 : VAForm_1a<51,1034 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),1035 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,1036 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,1037 isPPC64;1038 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),1039 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;1040}1041def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),1042 "addpcis $RT, $D", IIC_BrB, []>, isPPC64;1043def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),1044 "modsd $RST, $RA, $RB", IIC_IntDivW,1045 [(set i64:$RST, (srem i64:$RA, i64:$RB))]>;1046def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),1047 "modud $RST, $RA, $RB", IIC_IntDivW,1048 [(set i64:$RST, (urem i64:$RA, i64:$RB))]>;1049}1050 1051defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1052 "divdeu", "$RT, $RA, $RB", IIC_IntDivD,1053 [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>,1054 isPPC64, Requires<[HasExtDiv]>;1055let isCommutable = 1 in1056defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),1057 "mulld", "$RT, $RA, $RB", IIC_IntMulHD,1058 [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64;1059let Interpretation64Bit = 1, isCodeGenOnly = 1 in1060def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),1061 "mulli $RST, $RA, $D", IIC_IntMulLI,1062 [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>;1063}1064 1065let hasSideEffects = 1 in {1066def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),1067 "darn $RT, $L", IIC_LdStLD>, isPPC64;1068}1069 1070let hasSideEffects = 0 in {1071defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA),1072 (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE),1073 "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,1074 []>, isPPC64, RegConstraint<"$RAi = $RA">;1075 1076// Rotate instructions.1077defm RLDCL : MDSForm_1r<30, 8,1078 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),1079 "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,1080 []>, isPPC64;1081defm RLDCR : MDSForm_1r<30, 9,1082 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),1083 "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,1084 []>, isPPC64;1085defm RLDICL : MDForm_1r<30, 0,1086 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),1087 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,1088 []>, isPPC64;1089// For fast-isel:1090let isCodeGenOnly = 1 in1091def RLDICL_32_64 : MDForm_1<30, 0,1092 (outs g8rc:$RA),1093 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),1094 "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI,1095 []>, isPPC64;1096// End fast-isel.1097let Interpretation64Bit = 1, isCodeGenOnly = 1 in1098defm RLDICL_32 : MDForm_1r<30, 0,1099 (outs gprc:$RA),1100 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),1101 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,1102 []>, isPPC64;1103defm RLDICR : MDForm_1r<30, 1,1104 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),1105 "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,1106 []>, isPPC64;1107let isCodeGenOnly = 1 in1108def RLDICR_32 : MDForm_1<30, 1,1109 (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),1110 "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI,1111 []>, isPPC64;1112defm RLDIC : MDForm_1r<30, 2,1113 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),1114 "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,1115 []>, isPPC64;1116 1117let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1118defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA),1119 (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),1120 "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,1121 []>;1122 1123defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA),1124 (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME),1125 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral,1126 []>;1127 1128// RLWIMI can be commuted if the rotate amount is zero.1129let Interpretation64Bit = 1, isCodeGenOnly = 1 in1130defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA),1131 (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB,1132 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",1133 IIC_IntRotate, []>, PPC970_DGroup_Cracked,1134 RegConstraint<"$RAi = $RA">;1135 1136let isSelect = 1 in1137def ISEL8 : AForm_4<31, 15,1138 (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND),1139 "isel $RT, $RA, $RB, $COND", IIC_IntISEL,1140 []>;1141} // Interpretation64Bit1142} // hasSideEffects = 01143} // End FXU Operations.1144 1145def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;1146def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;1147 1148def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;1149def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;1150 1151def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;1152def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;1153 1154def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;1155 1156def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;1157def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;1158def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;1159def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;1160 1161def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;1162def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;1163def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;1164def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;1165def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;1166def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;1167 1168def : InstAlias<"isellt $rT, $rA, $rB",1169 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;1170def : InstAlias<"iselgt $rT, $rA, $rB",1171 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;1172def : InstAlias<"iseleq $rT, $rA, $rB",1173 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;1174 1175def : InstAlias<"nop", (ORI8 X0, X0, 0)>;1176def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;1177 1178def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;1179def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;1180 1181def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>;1182def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>;1183 1184//Disable this alias on AIX for now because as does not support them.1185let Predicates = [ModernAs] in {1186 1187def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>;1188def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>;1189 1190def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>;1191def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>;1192 1193def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>;1194def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>;1195 1196def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>;1197def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>;1198 1199def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>;1200def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>;1201 1202def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>;1203def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>;1204 1205def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>;1206def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>;1207 1208def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>;1209def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>;1210 1211def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>;1212def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>;1213 1214def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>;1215def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>;1216 1217def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>;1218def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>;1219 1220def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>;1221def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>;1222 1223def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>;1224def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>;1225 1226def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>;1227def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>;1228 1229foreach SPRG = 0-3 in {1230 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>;1231 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>;1232 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>;1233 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>;1234}1235 1236def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>;1237def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>;1238 1239def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>;1240def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>;1241 1242def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>;1243 1244def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>;1245def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>;1246 1247}1248 1249//===----------------------------------------------------------------------===//1250// Load/Store instructions.1251//1252 1253 1254// Sign extending loads.1255let PPC970_Unit = 2 in {1256let Interpretation64Bit = 1, isCodeGenOnly = 1 in1257def LHA8: DForm_1<42, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),1258 "lha $RST, $addr", IIC_LdStLHA,1259 [(set i64:$RST, (sextloadi16 DForm:$addr))]>,1260 PPC970_DGroup_Cracked, SExt32To64;1261def LWA : DSForm_1<58, 2, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),1262 "lwa $RST, $addr", IIC_LdStLWA,1263 [(set i64:$RST,1264 (sextloadi32 DSForm:$addr))]>, isPPC64,1265 PPC970_DGroup_Cracked, SExt32To64;1266let Interpretation64Bit = 1, isCodeGenOnly = 1 in1267def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1268 "lhax $RST, $addr", IIC_LdStLHA,1269 [(set i64:$RST, (sextloadi16 XForm:$addr))]>,1270 PPC970_DGroup_Cracked, SExt32To64;1271def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1272 "lwax $RST, $addr", IIC_LdStLHA,1273 [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64,1274 PPC970_DGroup_Cracked, SExt32To64;1275// For fast-isel:1276let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {1277def LWA_32 : DSForm_1<58, 2, (outs gprc:$RST), (ins (memrix $D, $RA):$addr),1278 "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64,1279 PPC970_DGroup_Cracked, SExt32To64;1280def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),1281 "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64,1282 PPC970_DGroup_Cracked, SExt32To64;1283} // end fast-isel isCodeGenOnly1284 1285// Update forms.1286let mayLoad = 1, hasSideEffects = 0 in {1287let Interpretation64Bit = 1, isCodeGenOnly = 1 in1288def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1289 (ins (memri $D, $RA):$addr),1290 "lhau $RST, $addr", IIC_LdStLHAU,1291 []>, RegConstraint<"$addr.reg = $ea_result">;1292// NO LWAU!1293 1294let Interpretation64Bit = 1, isCodeGenOnly = 1 in1295def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1296 (ins (memrr $RA, $RB):$addr),1297 "lhaux $RST, $addr", IIC_LdStLHAUX,1298 []>, RegConstraint<"$addr.ptrreg = $ea_result">;1299def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1300 (ins (memrr $RA, $RB):$addr),1301 "lwaux $RST, $addr", IIC_LdStLHAUX,1302 []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64;1303}1304}1305 1306let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1307// Zero extending loads.1308let PPC970_Unit = 2 in {1309def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),1310 "lbz $RST, $addr", IIC_LdStLoad,1311 [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,1312 SExt32To64;1313def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),1314 "lhz $RST, $addr", IIC_LdStLoad,1315 [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,1316 SExt32To64;1317def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),1318 "lwz $RST, $addr", IIC_LdStLoad,1319 [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64,1320 ZExt32To64;1321 1322def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1323 "lbzx $RST, $addr", IIC_LdStLoad,1324 [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,1325 SExt32To64;1326def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1327 "lhzx $RST, $addr", IIC_LdStLoad,1328 [(set i64:$RST, (zextloadi16 XForm:$addr))]>,1329 ZExt32To64, SExt32To64;1330def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1331 "lwzx $RST, $addr", IIC_LdStLoad,1332 [(set i64:$RST, (zextloadi32 XForm:$addr))]>,1333 ZExt32To64;1334 1335 1336// Update forms.1337let mayLoad = 1, hasSideEffects = 0 in {1338def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1339 (ins (memri $D, $RA):$addr),1340 "lbzu $RST, $addr", IIC_LdStLoadUpd,1341 []>, RegConstraint<"$addr.reg = $ea_result">;1342def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1343 (ins (memri $D, $RA):$addr),1344 "lhzu $RST, $addr", IIC_LdStLoadUpd,1345 []>, RegConstraint<"$addr.reg = $ea_result">;1346def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1347 (ins (memri $D, $RA):$addr),1348 "lwzu $RST, $addr", IIC_LdStLoadUpd,1349 []>, RegConstraint<"$addr.reg = $ea_result">;1350 1351def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1352 (ins (memrr $RA, $RB):$addr),1353 "lbzux $RST, $addr", IIC_LdStLoadUpdX,1354 []>, RegConstraint<"$addr.ptrreg = $ea_result">;1355def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1356 (ins (memrr $RA, $RB):$addr),1357 "lhzux $RST, $addr", IIC_LdStLoadUpdX,1358 []>, RegConstraint<"$addr.ptrreg = $ea_result">;1359def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1360 (ins (memrr $RA, $RB):$addr),1361 "lwzux $RST, $addr", IIC_LdStLoadUpdX,1362 []>, RegConstraint<"$addr.ptrreg = $ea_result">;1363}1364}1365} // Interpretation64Bit1366 1367 1368// Full 8-byte loads.1369let PPC970_Unit = 2 in {1370def LD : DSForm_1<58, 0, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),1371 "ld $RST, $addr", IIC_LdStLD,1372 [(set i64:$RST, (load DSForm:$addr))]>, isPPC64;1373// The following four definitions are selected for small code model only.1374// Otherwise, we need to create two instructions to form a 32-bit offset,1375// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().1376def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),1377 "#LDtoc",1378 [(set i64:$rD,1379 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;1380def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),1381 "#LDtocJTI",1382 [(set i64:$rD,1383 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;1384def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),1385 "#LDtocCPT",1386 [(set i64:$rD,1387 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;1388def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),1389 "#LDtocCPT",1390 [(set i64:$rD,1391 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;1392 1393def LDX : XForm_1_memOp<31, 21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1394 "ldx $RST, $addr", IIC_LdStLD,1395 [(set i64:$RST, (load XForm:$addr))]>, isPPC64;1396 1397let Predicates = [IsISA2_06] in {1398def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1399 "ldbrx $RST, $addr", IIC_LdStLoad,1400 [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64;1401}1402 1403let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {1404def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1405 "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;1406def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),1407 "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;1408}1409 1410let mayLoad = 1, hasSideEffects = 0 in {1411def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1412 (ins (memrix $D, $RA):$addr),1413 "ldu $RST, $addr", IIC_LdStLDU,1414 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64;1415 1416def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),1417 (ins (memrr $RA, $RB):$addr),1418 "ldux $RST, $addr", IIC_LdStLDUX,1419 []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64;1420}1421 1422let mayLoad = 1, hasNoSchedulingInfo = 1 in {1423// Full 16-byte load.1424// Early clobber $RTp to avoid assigned to the same register as RA.1425// TODO: Add scheduling info.1426def LQ : DQForm_RTp5_RA17_MEM<56, 0,1427 (outs g8prc:$RTp),1428 (ins (memrix16 $DQ, $RA):$addr),1429 "lq $RTp, $addr", IIC_LdStLQ,1430 []>,1431 RegConstraint<"@earlyclobber $RTp">,1432 isPPC64;1433// We don't really have LQX in the ISA, make a pseudo one so that we can1434// handle x-form during isel. Make it pre-ra may expose1435// oppotunities to some opts(CSE, LICM and etc.) for the result of adding1436// RA and RB.1437def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp),1438 (ins memrr:$src), "#LQX_PSEUDO", []>;1439 1440def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src),1441 "#RESTORE_QUADWORD", []>;1442}1443 1444}1445 1446def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src),1447 (SPLIT_QUADWORD (LQ memrix16:$src))>;1448 1449def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src),1450 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>;1451 1452// Support for medium and large code model.1453let hasSideEffects = 0 in {1454let isReMaterializable = 1 in {1455def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),1456 "#ADDIStocHA8", []>, isPPC64;1457def ADDItocL8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),1458 "#ADDItocL8", []>, isPPC64;1459}1460 1461// Local Data Transform1462def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),1463 "#ADDItoc8",1464 []>, isPPC64;1465let mayLoad = 1 in1466def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),1467 "#LDtocL", []>, isPPC64;1468}1469 1470// Support for thread-local storage.1471def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1472 "#ADDISgotTprelHA",1473 [(set i64:$rD,1474 (PPCaddisGotTprelHA i64:$reg,1475 tglobaltlsaddr:$disp))]>,1476 isPPC64;1477def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),1478 "#LDgotTprelL",1479 [(set i64:$rD,1480 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,1481 isPPC64;1482 1483let Defs = [CR7], Itinerary = IIC_LdStSync in1484def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;1485 1486def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),1487 (ADD8TLS $in, tglobaltlsaddr:$g)>;1488def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1489 "#ADDIStlsgdHA",1490 [(set i64:$rD,1491 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,1492 isPPC64;1493def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1494 "#ADDItlsgdL",1495 [(set i64:$rD,1496 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,1497 isPPC64;1498 1499class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),1500 asmstr,1501 [(set i64:$rD,1502 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,1503 isPPC64;1504class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),1505 asmstr,1506 [(set i64:$rD,1507 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,1508 isPPC64;1509 1510let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in {1511// LR8 is a true define, while the rest of the Defs are clobbers. X3 is1512// explicitly defined when this op is created, so not mentioned here.1513// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be1514// correct because the branch select pass is relying on it.1515let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in1516def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">;1517let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in1518def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">;1519 1520// LR8 is a true define, while the rest of the Defs are clobbers. X3 is1521// explicitly defined when this op is created, so not mentioned here.1522let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in1523def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">;1524let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in1525def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">;1526 1527// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the1528// offset and region handle respectively. The call is not followed by a nop1529// so we don't need to mark it with a size of 8 bytes. Finally, the assembly1530// manual mentions this exact set of registers as the clobbered set, others1531// are guaranteed not to be clobbered.1532let Defs = [X0,X4,X5,X11,LR8,CR0] in {1533def GETtlsADDR64AIX :1534 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle),1535 "GETtlsADDR64AIX",1536 [(set i64:$rD,1537 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64;1538// On AIX, the call to .__tls_get_mod needs one input in X3 for the module handle.1539def GETtlsMOD64AIX :1540 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$handle),1541 "GETtlsMOD64AIX",1542 [(set i64:$rD,1543 (PPCgetTlsMod i64:$handle))]>, isPPC64;1544}1545}1546 1547// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR81548// are true defines while the rest of the Defs are clobbers.1549let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,1550 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]1551 in1552def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),1553 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),1554 "#ADDItlsgdLADDR",1555 [(set i64:$rD,1556 (PPCaddiTlsgdLAddr i64:$reg,1557 tglobaltlsaddr:$disp,1558 tglobaltlsaddr:$sym))]>,1559 isPPC64;1560def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1561 "#ADDIStlsldHA",1562 [(set i64:$rD,1563 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,1564 isPPC64;1565def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1566 "#ADDItlsldL",1567 [(set i64:$rD,1568 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,1569 isPPC64;1570// This pseudo is expanded to two copies to put the variable offset in R4 and1571// the region handle in R3 and GETtlsADDR64AIX.1572def TLSGDAIX8 :1573 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle),1574 "#TLSGDAIX8",1575 [(set i64:$rD,1576 (PPCTlsgdAIX i64:$offset, i64:$handle))]>;1577// This pseudo is expanded to the call to GETtlsMOD64AIX.1578def TLSLDAIX8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$handle),1579 "#TLSLDAIX8", [(set i64:$rD, (PPCTlsldAIX i64:$handle))]>;1580// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR81581// are true defines, while the rest of the Defs are clobbers.1582let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,1583 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]1584 in1585def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),1586 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),1587 "#ADDItlsldLADDR",1588 [(set i64:$rD,1589 (PPCaddiTlsldLAddr i64:$reg,1590 tglobaltlsaddr:$disp,1591 tglobaltlsaddr:$sym))]>,1592 isPPC64;1593def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1594 "#ADDISdtprelHA",1595 [(set i64:$rD,1596 (PPCaddisDtprelHA i64:$reg,1597 tglobaltlsaddr:$disp))]>,1598 isPPC64;1599def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1600 "#ADDIdtprelL",1601 [(set i64:$rD,1602 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,1603 isPPC64;1604def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),1605 "#PADDIdtprel",1606 [(set i64:$rD,1607 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>,1608 isPPC64;1609 1610let PPC970_Unit = 2 in {1611let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1612// Truncating stores.1613def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),1614 "stb $RST, $addr", IIC_LdStStore,1615 [(truncstorei8 i64:$RST, DForm:$addr)]>;1616def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),1617 "sth $RST, $addr", IIC_LdStStore,1618 [(truncstorei16 i64:$RST, DForm:$addr)]>;1619def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),1620 "stw $RST, $addr", IIC_LdStStore,1621 [(truncstorei32 i64:$RST, DForm:$addr)]>;1622def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),1623 "stbx $RST, $addr", IIC_LdStStore,1624 [(truncstorei8 i64:$RST, XForm:$addr)]>,1625 PPC970_DGroup_Cracked;1626def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),1627 "sthx $RST, $addr", IIC_LdStStore,1628 [(truncstorei16 i64:$RST, XForm:$addr)]>,1629 PPC970_DGroup_Cracked;1630def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),1631 "stwx $RST, $addr", IIC_LdStStore,1632 [(truncstorei32 i64:$RST, XForm:$addr)]>,1633 PPC970_DGroup_Cracked;1634} // Interpretation64Bit1635 1636// Normal 8-byte stores.1637def STD : DSForm_1<62, 0, (outs), (ins g8rc:$RST, (memrix $D, $RA):$addr),1638 "std $RST, $addr", IIC_LdStSTD,1639 [(store i64:$RST, DSForm:$addr)]>, isPPC64;1640def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),1641 "stdx $RST, $addr", IIC_LdStSTD,1642 [(store i64:$RST, XForm:$addr)]>, isPPC64,1643 PPC970_DGroup_Cracked;1644 1645let Predicates = [IsISA2_06] in {1646def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),1647 "stdbrx $RST, $addr", IIC_LdStStore,1648 [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64,1649 PPC970_DGroup_Cracked;1650}1651 1652let mayStore = 1, hasNoSchedulingInfo = 1 in {1653// Normal 16-byte stores.1654// TODO: Add scheduling info.1655def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, (memrix $D, $RA):$addr),1656 "stq $RST, $addr", IIC_LdStSTQ,1657 []>, isPPC64;1658 1659def STQX_PSEUDO : PPCCustomInserterPseudo<(outs),1660 (ins g8prc:$RSp, memrr:$dst),1661 "#STQX_PSEUDO", []>;1662 1663def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst),1664 "#SPILL_QUADWORD", []>;1665}1666 1667}1668 1669def BUILD_QUADWORD : PPCPostRAExpPseudo<1670 (outs g8prc:$RTp),1671 (ins g8rc:$lo, g8rc:$hi),1672 "#BUILD_QUADWORD", []>;1673 1674def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst),1675 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>;1676 1677def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst),1678 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>;1679 1680// Stores with Update (pre-inc).1681let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {1682let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1683def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),1684 "stbu $RST, $addr", IIC_LdStSTU, []>,1685 RegConstraint<"$addr.reg = $ea_res">;1686def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),1687 "sthu $RST, $addr", IIC_LdStSTU, []>,1688 RegConstraint<"$addr.reg = $ea_res">;1689def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),1690 "stwu $RST, $addr", IIC_LdStSTU, []>,1691 RegConstraint<"$addr.reg = $ea_res">;1692 1693def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),1694 (ins g8rc:$RST, (memrr $RA, $RB):$addr),1695 "stbux $RST, $addr", IIC_LdStSTUX, []>,1696 RegConstraint<"$addr.ptrreg = $ea_res">,1697 PPC970_DGroup_Cracked;1698def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),1699 (ins g8rc:$RST, (memrr $RA, $RB):$addr),1700 "sthux $RST, $addr", IIC_LdStSTUX, []>,1701 RegConstraint<"$addr.ptrreg = $ea_res">,1702 PPC970_DGroup_Cracked;1703def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),1704 (ins g8rc:$RST, (memrr $RA, $RB):$addr),1705 "stwux $RST, $addr", IIC_LdStSTUX, []>,1706 RegConstraint<"$addr.ptrreg = $ea_res">,1707 PPC970_DGroup_Cracked;1708} // Interpretation64Bit1709 1710def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),1711 (ins g8rc:$RST, (memrix $D, $RA):$addr),1712 "stdu $RST, $addr", IIC_LdStSTU, []>,1713 RegConstraint<"$addr.reg = $ea_res">,1714 isPPC64;1715 1716def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),1717 (ins g8rc:$RST, (memrr $RA, $RB):$addr),1718 "stdux $RST, $addr", IIC_LdStSTUX, []>,1719 RegConstraint<"$addr.ptrreg = $ea_res">,1720 PPC970_DGroup_Cracked, isPPC64;1721}1722 1723// Patterns to match the pre-inc stores. We can't put the patterns on1724// the instruction definitions directly as ISel wants the address base1725// and offset to be separate operands, not a single complex operand.1726def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),1727 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;1728def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),1729 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;1730def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),1731 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;1732def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),1733 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;1734 1735def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),1736 (STBUX8 $rS, $ptrreg, $ptroff)>;1737def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),1738 (STHUX8 $rS, $ptrreg, $ptroff)>;1739def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),1740 (STWUX8 $rS, $ptrreg, $ptroff)>;1741def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),1742 (STDUX $rS, $ptrreg, $ptroff)>;1743 1744 1745//===----------------------------------------------------------------------===//1746// Floating point instructions.1747//1748 1749 1750let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,1751 Uses = [RM] in { // FPU Operations.1752defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),1753 "fcfid", "$RST, $RB", IIC_FPGeneral,1754 [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;1755defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),1756 "fctid", "$RST, $RB", IIC_FPGeneral,1757 []>, isPPC64;1758defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),1759 "fctidu", "$RST, $RB", IIC_FPGeneral,1760 []>, isPPC64;1761defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),1762 "fctidz", "$RST, $RB", IIC_FPGeneral,1763 [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;1764 1765defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),1766 "fcfidu", "$RST, $RB", IIC_FPGeneral,1767 [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;1768defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),1769 "fcfids", "$RST, $RB", IIC_FPGeneral,1770 [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;1771defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),1772 "fcfidus", "$RST, $RB", IIC_FPGeneral,1773 [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;1774defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),1775 "fctiduz", "$RST, $RB", IIC_FPGeneral,1776 [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;1777defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),1778 "fctiwuz", "$RST, $RB", IIC_FPGeneral,1779 [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;1780}1781 1782// These instructions store a hash computed from the value of the link register1783// and the value of the stack pointer.1784let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in {1785def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs),1786 (ins g8rc:$RB, (memrihash $D, $RA):$addr),1787 "hashst $RB, $addr", IIC_IntGeneral, []>;1788def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs),1789 (ins g8rc:$RB, (memrihash $D, $RA):$addr),1790 "hashstp $RB, $addr", IIC_IntGeneral, []>;1791}1792 1793// These instructions check a hash computed from the value of the link register1794// and the value of the stack pointer. The hasSideEffects flag is needed as the1795// instruction may TRAP if the hash does not match the hash stored at the1796// specified address.1797let mayLoad = 1, hasSideEffects = 1,1798 Interpretation64Bit = 1, isCodeGenOnly = 1 in {1799def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs),1800 (ins g8rc:$RB, (memrihash $D, $RA):$addr),1801 "hashchk $RB, $addr", IIC_IntGeneral, []>;1802def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs),1803 (ins g8rc:$RB, (memrihash $D, $RA):$addr),1804 "hashchkp $RB, $addr", IIC_IntGeneral, []>;1805}1806 1807let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in1808def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),1809 (ins g8rc:$RA, g8rc:$RB, u2imm:$CY),1810 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral,1811 [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,1812 timm:$CY))]>;1813 1814//===----------------------------------------------------------------------===//1815// Instruction Patterns1816//1817 1818// Extensions and truncates to/from 32-bit regs.1819def : Pat<(i64 (zext i32:$in)),1820 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),1821 0, 32)>;1822def : Pat<(i64 (anyext i32:$in)),1823 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;1824def : Pat<(i32 (trunc i64:$in)),1825 (EXTRACT_SUBREG $in, sub_32)>;1826 1827// Implement the 'not' operation with the NOR instruction.1828// (we could use the default xori pattern, but nor has lower latency on some1829// cores (such as the A2)).1830def i64not : OutPatFrag<(ops node:$in),1831 (NOR8 $in, $in)>;1832def : Pat<(not i64:$in),1833 (i64not $in)>;1834 1835// Extending loads with i64 targets.1836def : Pat<(zextloadi1 DForm:$src),1837 (LBZ8 DForm:$src)>;1838def : Pat<(zextloadi1 XForm:$src),1839 (LBZX8 XForm:$src)>;1840def : Pat<(extloadi1 DForm:$src),1841 (LBZ8 DForm:$src)>;1842def : Pat<(extloadi1 XForm:$src),1843 (LBZX8 XForm:$src)>;1844def : Pat<(extloadi8 DForm:$src),1845 (LBZ8 DForm:$src)>;1846def : Pat<(extloadi8 XForm:$src),1847 (LBZX8 XForm:$src)>;1848def : Pat<(extloadi16 DForm:$src),1849 (LHZ8 DForm:$src)>;1850def : Pat<(extloadi16 XForm:$src),1851 (LHZX8 XForm:$src)>;1852def : Pat<(extloadi32 DForm:$src),1853 (LWZ8 DForm:$src)>;1854def : Pat<(extloadi32 XForm:$src),1855 (LWZX8 XForm:$src)>;1856 1857// Standard shifts. These are represented separately from the real shifts above1858// so that we can distinguish between shifts that allow 6-bit and 7-bit shift1859// amounts.1860def : Pat<(sra i64:$rS, i32:$rB),1861 (SRAD $rS, $rB)>;1862def : Pat<(srl i64:$rS, i32:$rB),1863 (SRD $rS, $rB)>;1864def : Pat<(shl i64:$rS, i32:$rB),1865 (SLD $rS, $rB)>;1866 1867// SUBFIC1868def : Pat<(sub imm64SExt16:$imm, i64:$in),1869 (SUBFIC8 $in, imm:$imm)>;1870 1871// SHL/SRL1872def : Pat<(shl i64:$in, (i32 imm:$imm)),1873 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;1874def : Pat<(srl i64:$in, (i32 imm:$imm)),1875 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;1876 1877// ROTL1878def : Pat<(rotl i64:$in, i32:$sh),1879 (RLDCL $in, $sh, 0)>;1880def : Pat<(rotl i64:$in, (i32 imm:$imm)),1881 (RLDICL $in, imm:$imm, 0)>;1882 1883// Hi and Lo for Darwin Global Addresses.1884def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;1885def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;1886def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;1887def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;1888def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;1889def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;1890def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;1891def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;1892def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),1893 (ADDIS8 $in, tglobaltlsaddr:$g)>;1894def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),1895 (ADDI8 $in, tglobaltlsaddr:$g)>;1896def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),1897 (ADDIS8 $in, tglobaladdr:$g)>;1898def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),1899 (ADDIS8 $in, tconstpool:$g)>;1900def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),1901 (ADDIS8 $in, tjumptable:$g)>;1902def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),1903 (ADDIS8 $in, tblockaddress:$g)>;1904 1905// AIX 64-bit small code model TLS access.1906// This is used for global dynamic accesses when loading the region handle and1907// variable offset, and also for local-exec accesses to load the offset of a1908// TLS variable from the TOC, prior to adding it to r13.1909def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)),1910 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>;1911 1912// The following pattern matches 64-bit local- and initial-exec TLS accesses on AIX.1913// PPCaddTls is used in local- and initial-exec accesses in order to:1914// - Get the address of a variable (adding the variable offset to the thread1915// pointer in r13).1916// - Create an opportunity to optimize the user of the loaded address.1917def : Pat<(PPCaddTls i64:$in, i64:$addr),1918 (ADD8TLS $in, $addr)>;1919 1920// 64-bits atomic loads and stores1921def : Pat<(atomic_load_nonext_64 DSForm:$src), (LD memrix:$src)>;1922def : Pat<(atomic_load_nonext_64 XForm:$src), (LDX memrr:$src)>;1923 1924def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>;1925def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>;1926 1927let Predicates = [IsISA3_0, IsPPC64] in {1928def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),1929 (i64 (SETB8 (CMPEQB $a, $b)))>;1930def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)),1931 (i64 (SETB8 (CMPD $a, $b)))>;1932def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)),1933 (i64 (MADDHD $a, $b, $c))>;1934def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)),1935 (i64 (MADDHDU $a, $b, $c))>;1936def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)),1937 (i64 (MADDLD8 $a, $b, $c))>;1938}1939 1940let Predicates = [IsPPC64] in {1941def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),1942 (i64 (MULHD $a, $b))>;1943def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),1944 (i64 (MULHDU $a, $b))>;1945def : Pat<(int_ppc_load8r ForceXForm:$ptr),1946 (LDBRX ForceXForm:$ptr)>;1947def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr),1948 (STDBRX g8rc:$a, ForceXForm:$ptr)>;1949}1950 1951def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),1952 (i64 (CMPB8 $a, $b))>;1953 1954let Predicates = [IsISA3_0] in {1955// DARN (deliver random number)1956// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random1957def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;1958def : Pat<(int_ppc_darn), (DARN 1)>;1959def : Pat<(int_ppc_darnraw), (DARN 2)>;1960 1961class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,1962 InstrItinClass itin, list<dag> pattern>1963 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB),1964 !strconcat(opc, " $RA, $RB"), itin, pattern>{1965 let L = 1;1966}1967 1968class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,1969 InstrItinClass itin, list<dag> pattern>1970 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),1971 !strconcat(opc, " $RA, $RB, $L"), itin, pattern>;1972 1973let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1974def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;1975def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;1976}1977 1978// SLB Invalidate Entry Global1979def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB),1980 "slbieg $RST, $RB", IIC_SprSLBIEG, []>;1981// SLB Synchronize1982def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;1983 1984} // IsISA3_01985 1986def : Pat<(int_ppc_ldarx ForceXForm:$ptr),1987 (LDARX ForceXForm:$ptr)>;1988def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),1989 (RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>;1990def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8),1991 (RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>;1992 1993def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),1994 (MFSPR8 $SPR)>;1995def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),1996 (MTSPR8 $SPR, $RT)>;1997