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1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Altivec extension to the PowerPC instruction set.10//11//===----------------------------------------------------------------------===//12 13// *********************************** NOTE ***********************************14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **15// ** which VMX and VSX instructions are lane-sensitive and which are not. **16// ** A lane-sensitive instruction relies, implicitly or explicitly, on **17// ** whether lanes are numbered from left to right. An instruction like **18// ** VADDFP is not lane-sensitive, because each lane of the result vector **19// ** relies only on the corresponding lane of the source vectors. However, **20// ** an instruction like VMULESB is lane-sensitive, because "even" and **21// ** "odd" lanes are different for big-endian and little-endian numbering. **22// ** **23// ** When adding new VMX and VSX instructions, please consider whether they **24// ** are lane-sensitive. If so, they must be added to a switch statement **25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **26// ****************************************************************************27 28 29//===----------------------------------------------------------------------===//30// Altivec transformation functions and pattern fragments.31//32 33// fneg is not legal, and desugared as an xor.34def desugared_fneg : PatFrag<(ops node:$x), (v4f32 (bitconvert (xor (bitconvert $x), 35 (int_ppc_altivec_vslw (bitconvert (v16i8 immAllOnesV)), 36 (bitconvert (v16i8 immAllOnesV))))))>; 37 38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),39 (vector_shuffle node:$lhs, node:$rhs), [{40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);41}]>;42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),43 (vector_shuffle node:$lhs, node:$rhs), [{44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);45}]>;46def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),47 (vector_shuffle node:$lhs, node:$rhs), [{48 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);49}]>;50def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),51 (vector_shuffle node:$lhs, node:$rhs), [{52 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);53}]>;54def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),55 (vector_shuffle node:$lhs, node:$rhs), [{56 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);57}]>;58def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),59 (vector_shuffle node:$lhs, node:$rhs), [{60 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);61}]>;62 63// These fragments are provided for little-endian, where the inputs must be64// swapped for correct semantics.65def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),66 (vector_shuffle node:$lhs, node:$rhs), [{67 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);68}]>;69def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),70 (vector_shuffle node:$lhs, node:$rhs), [{71 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);72}]>;73def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),74 (vector_shuffle node:$lhs, node:$rhs), [{75 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);76}]>;77 78def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{80 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);81}]>;82def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);85}]>;86def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{88 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);89}]>;90def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{92 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);93}]>;94def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{96 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);97}]>;98def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{100 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);101}]>;102 103 104def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{106 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);107}]>;108def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),109 (vector_shuffle node:$lhs, node:$rhs), [{110 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);111}]>;112def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),113 (vector_shuffle node:$lhs, node:$rhs), [{114 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);115}]>;116def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),117 (vector_shuffle node:$lhs, node:$rhs), [{118 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);119}]>;120def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),121 (vector_shuffle node:$lhs, node:$rhs), [{122 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);123}]>;124def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),125 (vector_shuffle node:$lhs, node:$rhs), [{126 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);127}]>;128 129 130// These fragments are provided for little-endian, where the inputs must be131// swapped for correct semantics.132def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{134 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);135}]>;136def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),137 (vector_shuffle node:$lhs, node:$rhs), [{138 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);139}]>;140def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),141 (vector_shuffle node:$lhs, node:$rhs), [{142 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);143}]>;144def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),145 (vector_shuffle node:$lhs, node:$rhs), [{146 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);147}]>;148def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),149 (vector_shuffle node:$lhs, node:$rhs), [{150 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);151}]>;152def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),153 (vector_shuffle node:$lhs, node:$rhs), [{154 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);155}]>;156 157 158def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs),159 (vector_shuffle node:$lhs, node:$rhs), [{160 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG);161}]>;162def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs),163 (vector_shuffle node:$lhs, node:$rhs), [{164 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG);165}]>;166def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),167 (vector_shuffle node:$lhs, node:$rhs), [{168 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG);169}]>;170def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),171 (vector_shuffle node:$lhs, node:$rhs), [{172 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG);173}]>;174def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),175 (vector_shuffle node:$lhs, node:$rhs), [{176 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG);177}]>;178def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),179 (vector_shuffle node:$lhs, node:$rhs), [{180 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG);181}]>;182 183 184 185def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{186 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));187}]>;188def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),189 (vector_shuffle node:$lhs, node:$rhs), [{190 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;191}], VSLDOI_get_imm>;192 193 194/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into195/// vector_shuffle(X,undef,mask) by the dag combiner.196def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{197 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N));198}]>;199def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),200 (vector_shuffle node:$lhs, node:$rhs), [{201 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;202}], VSLDOI_unary_get_imm>;203 204 205/// VSLDOI_swapped* - These fragments are provided for little-endian, where206/// the inputs must be swapped for correct semantics.207def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{208 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N));209}]>;210def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),211 (vector_shuffle node:$lhs, node:$rhs), [{212 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;213}], VSLDOI_get_imm>;214 215 216// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.217def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{218 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 1, *CurDAG), SDLoc(N));219}]>;220def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),221 (vector_shuffle node:$lhs, node:$rhs), [{222 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);223}], VSPLTB_get_imm>;224def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{225 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 2, *CurDAG), SDLoc(N));226}]>;227def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),228 (vector_shuffle node:$lhs, node:$rhs), [{229 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);230}], VSPLTH_get_imm>;231def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{232 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 4, *CurDAG), SDLoc(N));233}]>;234def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),235 (vector_shuffle node:$lhs, node:$rhs), [{236 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);237}], VSPLTW_get_imm>;238 239 240// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.241def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{242 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);243}]>;244def vecspltisb : PatLeaf<(build_vector), [{245 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr;246}], VSPLTISB_get_imm>;247 248// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.249def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{250 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);251}]>;252def vecspltish : PatLeaf<(build_vector), [{253 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr;254}], VSPLTISH_get_imm>;255 256// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.257def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{258 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);259}]>;260def vecspltisw : PatLeaf<(build_vector), [{261 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;262}], VSPLTISW_get_imm>;263 264def immEQOneV : PatLeaf<(build_vector), [{265 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())266 return C->isOne();267 return false;268}]>;269 270def VSRVSRO : PatFrag<(ops node:$input, node:$shift), 271 (int_ppc_altivec_vsr 272 (int_ppc_altivec_vsro node:$input, node:$shift), 273 node:$shift), 274 [{ return N->getOperand(1).hasOneUse(); }]>;275 276//===----------------------------------------------------------------------===//277// Helpers for defining instructions that directly correspond to intrinsics.278 279// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.280class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>281 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),282 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,283 [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;284 285// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the286// inputs doesn't match the type of the output.287class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,288 ValueType InTy>289 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),290 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,291 [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;292 293// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two294// input types and an output type.295class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,296 ValueType In1Ty, ValueType In2Ty>297 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),298 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,299 [(set OutTy:$RT,300 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;301 302// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.303class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>304 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),305 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,306 [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;307 308// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the309// inputs doesn't match the type of the output.310class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,311 ValueType InTy>312 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),313 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,314 [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;315 316// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two317// input types and an output type.318class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,319 ValueType In1Ty, ValueType In2Ty>320 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),321 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,322 [(set OutTy:$VD, (IntID In1Ty:$VA, In2Ty:$VB))]>;323 324// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.325class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>326 : VXForm_2<xo, (outs vrrc:$VD), (ins vrrc:$VB),327 !strconcat(opc, " $VD, $VB"), IIC_VecFP,328 [(set v4f32:$VD, (IntID v4f32:$VB))]>;329 330// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the331// inputs doesn't match the type of the output.332class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,333 ValueType InTy>334 : VXForm_2<xo, (outs vrrc:$VD), (ins vrrc:$VB),335 !strconcat(opc, " $VD, $VB"), IIC_VecFP,336 [(set OutTy:$VD, (IntID InTy:$VB))]>;337 338class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>339 : VXForm_BX<xo, (outs vrrc:$VD), (ins vrrc:$VA),340 !strconcat(opc, " $VD, $VA"), IIC_VecFP,341 [(set Ty:$VD, (IntID Ty:$VA))]>;342 343class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>344 : VXForm_CR<xo, (outs vrrc:$VD), (ins vrrc:$VA, u1imm:$ST, u4imm:$SIX),345 !strconcat(opc, " $VD, $VA, $ST, $SIX"), IIC_VecFP,346 [(set Ty:$VD, (IntID Ty:$VA, timm:$ST, timm:$SIX))]>;347 348//===----------------------------------------------------------------------===//349// Instruction Definitions.350 351let Predicates = [HasAltivec] in {352 353def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),354 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,355 Deprecated<DeprecatedDST> {356 let RA = 0;357 let RB = 0;358}359 360def DSSALL : DSS_Form<1, 822, (outs), (ins),361 "dssall", IIC_LdStLoad /*FIXME*/, []>,362 Deprecated<DeprecatedDST> {363 let STRM = 0;364 let RA = 0;365 let RB = 0;366}367 368def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),369 "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,370 [(int_ppc_altivec_dst i32:$RA, i32:$RB, imm:$STRM)]>,371 Deprecated<DeprecatedDST>;372 373def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),374 "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,375 [(int_ppc_altivec_dstt i32:$RA, i32:$RB, imm:$STRM)]>,376 Deprecated<DeprecatedDST>;377 378def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),379 "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,380 [(int_ppc_altivec_dstst i32:$RA, i32:$RB, imm:$STRM)]>,381 Deprecated<DeprecatedDST>;382 383def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),384 "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,385 [(int_ppc_altivec_dststt i32:$RA, i32:$RB, imm:$STRM)]>,386 Deprecated<DeprecatedDST>;387 388let isCodeGenOnly = 1 in {389 // The very same instructions as above, but formally matching 64bit registers.390 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),391 "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,392 [(int_ppc_altivec_dst i64:$RA, i32:$RB, imm:$STRM)]>,393 Deprecated<DeprecatedDST>;394 395 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),396 "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,397 [(int_ppc_altivec_dstt i64:$RA, i32:$RB, imm:$STRM)]>,398 Deprecated<DeprecatedDST>;399 400 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),401 "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,402 [(int_ppc_altivec_dstst i64:$RA, i32:$RB,403 imm:$STRM)]>,404 Deprecated<DeprecatedDST>;405 406 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),407 "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,408 [(int_ppc_altivec_dststt i64:$RA, i32:$RB,409 imm:$STRM)]>,410 Deprecated<DeprecatedDST>;411}412 413let hasSideEffects = 1 in {414 def MFVSCR : VXForm_4<1540, (outs vrrc:$VD), (ins),415 "mfvscr $VD", IIC_LdStStore,416 [(set v8i16:$VD, (int_ppc_altivec_mfvscr))]>;417 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$VB),418 "mtvscr $VB", IIC_LdStLoad,419 [(int_ppc_altivec_mtvscr v4i32:$VB)]>;420}421 422let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.423def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),424 "lvebx $RST, $addr", IIC_LdStLoad,425 [(set v16i8:$RST, (int_ppc_altivec_lvebx ForceXForm:$addr))]>;426def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),427 "lvehx $RST, $addr", IIC_LdStLoad,428 [(set v8i16:$RST, (int_ppc_altivec_lvehx ForceXForm:$addr))]>;429def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),430 "lvewx $RST, $addr", IIC_LdStLoad,431 [(set v4i32:$RST, (int_ppc_altivec_lvewx ForceXForm:$addr))]>;432def LVX : XForm_1_memOp<31, 103, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),433 "lvx $RST, $addr", IIC_LdStLoad,434 [(set v4i32:$RST, (int_ppc_altivec_lvx ForceXForm:$addr))]>;435def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),436 "lvxl $RST, $addr", IIC_LdStLoad,437 [(set v4i32:$RST, (int_ppc_altivec_lvxl ForceXForm:$addr))]>;438}439 440def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),441 "lvsl $RST, $addr", IIC_LdStLoad,442 [(set v16i8:$RST, (int_ppc_altivec_lvsl ForceXForm:$addr))]>,443 PPC970_Unit_LSU;444def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),445 "lvsr $RST, $addr", IIC_LdStLoad,446 [(set v16i8:$RST, (int_ppc_altivec_lvsr ForceXForm:$addr))]>,447 PPC970_Unit_LSU;448 449let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.450def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),451 "stvebx $RST, $addr", IIC_LdStStore,452 [(int_ppc_altivec_stvebx v16i8:$RST, ForceXForm:$addr)]>;453def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),454 "stvehx $RST, $addr", IIC_LdStStore,455 [(int_ppc_altivec_stvehx v8i16:$RST, ForceXForm:$addr)]>;456def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),457 "stvewx $RST, $addr", IIC_LdStStore,458 [(int_ppc_altivec_stvewx v4i32:$RST, ForceXForm:$addr)]>;459def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),460 "stvx $RST, $addr", IIC_LdStStore,461 [(int_ppc_altivec_stvx v4i32:$RST, ForceXForm:$addr)]>;462def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),463 "stvxl $RST, $addr", IIC_LdStStore,464 [(int_ppc_altivec_stvxl v4i32:$RST, ForceXForm:$addr)]>;465}466 467let PPC970_Unit = 5 in { // VALU Operations.468// VA-Form instructions. 3-input AltiVec ops.469let isCommutable = 1 in {470def VMADDFP : VAForm_1<46, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB),471 "vmaddfp $RT, $RA, $RC, $RB", IIC_VecFP,472 [(set v4f32:$RT,473 (fma v4f32:$RA, v4f32:$RC, v4f32:$RB))]>;474 475// fneg is not legal, hence we have to match on the desugared version. 476def VNMSUBFP: VAForm_1<47, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB),477 "vnmsubfp $RT, $RA, $RC, $RB", IIC_VecFP,478 [(set v4f32:$RT, (desugared_fneg (fma v4f32:$RA, v4f32:$RC,479 (desugared_fneg v4f32:$RB))))]>;480 481let hasSideEffects = 1 in {482 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;483 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,484 v8i16>;485}486def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;487} // isCommutable488 489def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,490 v4i32, v4i32, v16i8>;491def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;492 493// Shuffles.494def VSLDOI : VAForm_2<44, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, u4imm:$SH),495 "vsldoi $RT, $RA, $RB, $SH", IIC_VecFP,496 [(set v16i8:$RT,497 (PPCvecshl v16i8:$RA, v16i8:$RB, imm32SExt16:$SH))]>;498 499// VX-Form instructions. AltiVec arithmetic ops.500let isCommutable = 1 in {501def VADDFP : VXForm_1<10, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),502 "vaddfp $VD, $VA, $VB", IIC_VecFP,503 [(set v4f32:$VD, (fadd v4f32:$VA, v4f32:$VB))]>;504 505def VADDUBM : VXForm_1<0, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),506 "vaddubm $VD, $VA, $VB", IIC_VecGeneral,507 [(set v16i8:$VD, (add v16i8:$VA, v16i8:$VB))]>;508def VADDUHM : VXForm_1<64, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),509 "vadduhm $VD, $VA, $VB", IIC_VecGeneral,510 [(set v8i16:$VD, (add v8i16:$VA, v8i16:$VB))]>;511def VADDUWM : VXForm_1<128, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),512 "vadduwm $VD, $VA, $VB", IIC_VecGeneral,513 [(set v4i32:$VD, (add v4i32:$VA, v4i32:$VB))]>;514 515def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;516def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;517def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;518def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;519def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;520def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;521def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;522} // isCommutable523 524let isCommutable = 1 in525def VAND : VXForm_1<1028, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),526 "vand $VD, $VA, $VB", IIC_VecFP,527 [(set v4i32:$VD, (and v4i32:$VA, v4i32:$VB))]>;528def VANDC : VXForm_1<1092, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),529 "vandc $VD, $VA, $VB", IIC_VecFP,530 [(set v4i32:$VD, (and v4i32:$VA,531 (vnot v4i32:$VB)))]>;532 533def VCFSX : VXForm_1<842, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),534 "vcfsx $VD, $VB, $VA", IIC_VecFP,535 [(set v4f32:$VD,536 (int_ppc_altivec_vcfsx v4i32:$VB, timm:$VA))]>;537def VCFUX : VXForm_1<778, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),538 "vcfux $VD, $VB, $VA", IIC_VecFP,539 [(set v4f32:$VD,540 (int_ppc_altivec_vcfux v4i32:$VB, timm:$VA))]>;541def VCTSXS : VXForm_1<970, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),542 "vctsxs $VD, $VB, $VA", IIC_VecFP,543 [(set v4i32:$VD,544 (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>;545def VCTUXS : VXForm_1<906, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),546 "vctuxs $VD, $VB, $VA", IIC_VecFP,547 [(set v4i32:$VD,548 (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>;549 550// Defines with the UIM field set to 0 for floating-point551// to integer (fp_to_sint/fp_to_uint) conversions and integer552// to floating-point (sint_to_fp/uint_to_fp) conversions.553let isCodeGenOnly = 1, VA = 0 in {554def VCFSX_0 : VXForm_1<842, (outs vrrc:$VD), (ins vrrc:$VB),555 "vcfsx $VD, $VB, 0", IIC_VecFP,556 [(set v4f32:$VD,557 (int_ppc_altivec_vcfsx v4i32:$VB, 0))]>;558def VCTUXS_0 : VXForm_1<906, (outs vrrc:$VD), (ins vrrc:$VB),559 "vctuxs $VD, $VB, 0", IIC_VecFP,560 [(set v4i32:$VD,561 (int_ppc_altivec_vctuxs v4f32:$VB, 0))]>;562def VCFUX_0 : VXForm_1<778, (outs vrrc:$VD), (ins vrrc:$VB),563 "vcfux $VD, $VB, 0", IIC_VecFP,564 [(set v4f32:$VD,565 (int_ppc_altivec_vcfux v4i32:$VB, 0))]>;566def VCTSXS_0 : VXForm_1<970, (outs vrrc:$VD), (ins vrrc:$VB),567 "vctsxs $VD, $VB, 0", IIC_VecFP,568 [(set v4i32:$VD,569 (int_ppc_altivec_vctsxs v4f32:$VB, 0))]>;570}571def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;572def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;573 574let isCommutable = 1 in {575def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;576def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;577def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;578def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;579def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;580def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;581 582def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;583def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;584def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;585def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;586def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;587def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;588def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;589def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;590def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;591def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;592def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;593def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;594def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;595def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;596} // isCommutable597 598def VMRGHB : VXForm_1< 12, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),599 "vmrghb $VD, $VA, $VB", IIC_VecFP,600 [(set v16i8:$VD, (vmrghb_shuffle v16i8:$VA, v16i8:$VB))]>;601def VMRGHH : VXForm_1< 76, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),602 "vmrghh $VD, $VA, $VB", IIC_VecFP,603 [(set v16i8:$VD, (vmrghh_shuffle v16i8:$VA, v16i8:$VB))]>;604def VMRGHW : VXForm_1<140, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),605 "vmrghw $VD, $VA, $VB", IIC_VecFP,606 [(set v16i8:$VD, (vmrghw_shuffle v16i8:$VA, v16i8:$VB))]>;607def VMRGLB : VXForm_1<268, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),608 "vmrglb $VD, $VA, $VB", IIC_VecFP,609 [(set v16i8:$VD, (vmrglb_shuffle v16i8:$VA, v16i8:$VB))]>;610def VMRGLH : VXForm_1<332, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),611 "vmrglh $VD, $VA, $VB", IIC_VecFP,612 [(set v16i8:$VD, (vmrglh_shuffle v16i8:$VA, v16i8:$VB))]>;613def VMRGLW : VXForm_1<396, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),614 "vmrglw $VD, $VA, $VB", IIC_VecFP,615 [(set v16i8:$VD, (vmrglw_shuffle v16i8:$VA, v16i8:$VB))]>;616 617def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,618 v4i32, v16i8, v4i32>;619def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,620 v4i32, v8i16, v4i32>;621def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,622 v4i32, v16i8, v4i32>;623def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,624 v4i32, v8i16, v4i32>;625let hasSideEffects = 1 in {626 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,627 v4i32, v8i16, v4i32>;628 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,629 v4i32, v8i16, v4i32>;630}631 632let isCommutable = 1 in {633def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,634 v8i16, v16i8>;635def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,636 v4i32, v8i16>;637def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,638 v8i16, v16i8>;639def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,640 v4i32, v8i16>;641def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,642 v8i16, v16i8>;643def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,644 v4i32, v8i16>;645def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,646 v8i16, v16i8>;647def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,648 v4i32, v8i16>;649} // isCommutable650 651def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;652def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;653def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;654def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;655def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;656def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;657 658def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;659 660def VSUBFP : VXForm_1<74, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),661 "vsubfp $VD, $VA, $VB", IIC_VecGeneral,662 [(set v4f32:$VD, (fsub v4f32:$VA, v4f32:$VB))]>;663def VSUBUBM : VXForm_1<1024, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),664 "vsububm $VD, $VA, $VB", IIC_VecGeneral,665 [(set v16i8:$VD, (sub v16i8:$VA, v16i8:$VB))]>;666def VSUBUHM : VXForm_1<1088, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),667 "vsubuhm $VD, $VA, $VB", IIC_VecGeneral,668 [(set v8i16:$VD, (sub v8i16:$VA, v8i16:$VB))]>;669def VSUBUWM : VXForm_1<1152, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),670 "vsubuwm $VD, $VA, $VB", IIC_VecGeneral,671 [(set v4i32:$VD, (sub v4i32:$VA, v4i32:$VB))]>;672 673def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;674def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;675def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;676def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;677def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;678def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;679 680let hasSideEffects = 1 in {681 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;682 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;683 684 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,685 v4i32, v16i8, v4i32>;686 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,687 v4i32, v8i16, v4i32>;688 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,689 v4i32, v16i8, v4i32>;690}691 692def VNOR : VXForm_1<1284, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),693 "vnor $VD, $VA, $VB", IIC_VecFP,694 [(set v4i32:$VD, (vnot (or v4i32:$VA,695 v4i32:$VB)))]>;696let isCommutable = 1 in {697def VOR : VXForm_1<1156, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),698 "vor $VD, $VA, $VB", IIC_VecFP,699 [(set v4i32:$VD, (or v4i32:$VA, v4i32:$VB))]>;700def VXOR : VXForm_1<1220, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),701 "vxor $VD, $VA, $VB", IIC_VecFP,702 [(set v4i32:$VD, (xor v4i32:$VA, v4i32:$VB))]>;703} // isCommutable704 705def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;706def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;707def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;708 709def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;710def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;711 712def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;713def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;714def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;715 716def VSPLTB : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),717 "vspltb $VD, $VB, $VA", IIC_VecPerm,718 [(set v16i8:$VD,719 (vspltb_shuffle:$VA v16i8:$VB, (undef)))]>;720def VSPLTH : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),721 "vsplth $VD, $VB, $VA", IIC_VecPerm,722 [(set v16i8:$VD,723 (vsplth_shuffle:$VA v16i8:$VB, (undef)))]>;724def VSPLTW : VXForm_1<652, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),725 "vspltw $VD, $VB, $VA", IIC_VecPerm,726 [(set v16i8:$VD,727 (vspltw_shuffle:$VA v16i8:$VB, (undef)))]>;728let isCodeGenOnly = 1, hasSideEffects = 0 in {729 def VSPLTBs : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB),730 "vspltb $VD, $VB, $VA", IIC_VecPerm, []>;731 def VSPLTHs : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB),732 "vsplth $VD, $VB, $VA", IIC_VecPerm, []>;733}734 735def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;736def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;737 738def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;739def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;740def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;741def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;742def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;743def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;744 745 746def VSPLTISB : VXForm_3<780, (outs vrrc:$VD), (ins s5imm:$IMM),747 "vspltisb $VD, $IMM", IIC_VecPerm,748 [(set v16i8:$VD, (v16i8 vecspltisb:$IMM))]>;749def VSPLTISH : VXForm_3<844, (outs vrrc:$VD), (ins s5imm:$IMM),750 "vspltish $VD, $IMM", IIC_VecPerm,751 [(set v8i16:$VD, (v8i16 vecspltish:$IMM))]>;752def VSPLTISW : VXForm_3<908, (outs vrrc:$VD), (ins s5imm:$IMM),753 "vspltisw $VD, $IMM", IIC_VecPerm,754 [(set v4i32:$VD, (v4i32 vecspltisw:$IMM))]>;755 756// Vector Pack.757def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,758 v8i16, v4i32>;759let hasSideEffects = 1 in {760 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,761 v16i8, v8i16>;762 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,763 v16i8, v8i16>;764 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,765 v8i16, v4i32>;766 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,767 v8i16, v4i32>;768 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,769 v16i8, v8i16>;770 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,771 v8i16, v4i32>;772}773def VPKUHUM : VXForm_1<14, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),774 "vpkuhum $VD, $VA, $VB", IIC_VecFP,775 [(set v16i8:$VD,776 (vpkuhum_shuffle v16i8:$VA, v16i8:$VB))]>;777def VPKUWUM : VXForm_1<78, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),778 "vpkuwum $VD, $VA, $VB", IIC_VecFP,779 [(set v16i8:$VD,780 (vpkuwum_shuffle v16i8:$VA, v16i8:$VB))]>;781 782// Vector Unpack.783def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,784 v4i32, v8i16>;785def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,786 v8i16, v16i8>;787def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,788 v4i32, v8i16>;789def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,790 v4i32, v8i16>;791def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,792 v8i16, v16i8>;793def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,794 v4i32, v8i16>;795 796 797// Altivec Comparisons.798 799class VCMP<bits<10> xo, string asmstr, ValueType Ty>800 : VXRForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), asmstr,801 IIC_VecFPCompare,802 [(set Ty:$VD, (Ty (PPCvcmp Ty:$VA, Ty:$VB, xo)))]>;803class VCMP_rec<bits<10> xo, string asmstr, ValueType Ty>804 : VXRForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), asmstr,805 IIC_VecFPCompare,806 [(set Ty:$VD, (Ty (PPCvcmp_rec Ty:$VA, Ty:$VB, xo)))]> {807 let Defs = [CR6];808 let RC = 1;809}810 811// f32 element comparisons.0812def VCMPBFP : VCMP <966, "vcmpbfp $VD, $VA, $VB" , v4f32>;813def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $VD, $VA, $VB" , v4f32>;814def VCMPEQFP : VCMP <198, "vcmpeqfp $VD, $VA, $VB" , v4f32>;815def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $VD, $VA, $VB", v4f32>;816def VCMPGEFP : VCMP <454, "vcmpgefp $VD, $VA, $VB" , v4f32>;817def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $VD, $VA, $VB", v4f32>;818def VCMPGTFP : VCMP <710, "vcmpgtfp $VD, $VA, $VB" , v4f32>;819def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $VD, $VA, $VB", v4f32>;820 821// i8 element comparisons.822def VCMPEQUB : VCMP < 6, "vcmpequb $VD, $VA, $VB" , v16i8>;823def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $VD, $VA, $VB", v16i8>;824def VCMPGTSB : VCMP <774, "vcmpgtsb $VD, $VA, $VB" , v16i8>;825def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $VD, $VA, $VB", v16i8>;826def VCMPGTUB : VCMP <518, "vcmpgtub $VD, $VA, $VB" , v16i8>;827def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $VD, $VA, $VB", v16i8>;828 829// i16 element comparisons.830def VCMPEQUH : VCMP < 70, "vcmpequh $VD, $VA, $VB" , v8i16>;831def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $VD, $VA, $VB", v8i16>;832def VCMPGTSH : VCMP <838, "vcmpgtsh $VD, $VA, $VB" , v8i16>;833def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $VD, $VA, $VB", v8i16>;834def VCMPGTUH : VCMP <582, "vcmpgtuh $VD, $VA, $VB" , v8i16>;835def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $VD, $VA, $VB", v8i16>;836 837// i32 element comparisons.838def VCMPEQUW : VCMP <134, "vcmpequw $VD, $VA, $VB" , v4i32>;839def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $VD, $VA, $VB", v4i32>;840def VCMPGTSW : VCMP <902, "vcmpgtsw $VD, $VA, $VB" , v4i32>;841def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $VD, $VA, $VB", v4i32>;842def VCMPGTUW : VCMP <646, "vcmpgtuw $VD, $VA, $VB" , v4i32>;843def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $VD, $VA, $VB", v4i32>;844 845let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,846 isReMaterializable = 1 in {847 848def V_SET0B : VXForm_setzero<1220, (outs vrrc:$VD), (ins),849 "vxor $VD, $VD, $VD", IIC_VecFP,850 [(set v16i8:$VD, (v16i8 immAllZerosV))]>;851def V_SET0H : VXForm_setzero<1220, (outs vrrc:$VD), (ins),852 "vxor $VD, $VD, $VD", IIC_VecFP,853 [(set v8i16:$VD, (v8i16 immAllZerosV))]>;854def V_SET0 : VXForm_setzero<1220, (outs vrrc:$VD), (ins),855 "vxor $VD, $VD, $VD", IIC_VecFP,856 [(set v4i32:$VD, (v4i32 immAllZerosV))]>;857 858let IMM=-1 in {859def V_SETALLONESB : VXForm_3<908, (outs vrrc:$VD), (ins),860 "vspltisw $VD, -1", IIC_VecFP,861 [(set v16i8:$VD, (v16i8 immAllOnesV))]>;862def V_SETALLONESH : VXForm_3<908, (outs vrrc:$VD), (ins),863 "vspltisw $VD, -1", IIC_VecFP,864 [(set v8i16:$VD, (v8i16 immAllOnesV))]>;865def V_SETALLONES : VXForm_3<908, (outs vrrc:$VD), (ins),866 "vspltisw $VD, -1", IIC_VecFP,867 [(set v4i32:$VD, (v4i32 immAllOnesV))]>;868}869}870} // VALU Operations.871 872//===----------------------------------------------------------------------===//873// Additional Altivec Patterns874//875 876// Extended mnemonics877def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;878def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;879 880// This is a nop on all supported architectures and the AIX assembler881// doesn't support it (and will not be updated to support it).882let Predicates = [IsAIX] in883def : Pat<(int_ppc_altivec_dssall), (NOP)>;884let Predicates = [NotAIX] in885def : Pat<(int_ppc_altivec_dssall), (DSSALL)>;886 887// Rotates.888def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)),889 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>;890def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)),891 (v8i16 (VRLH v8i16:$vA, v8i16:$vB))>;892let Predicates = [IsNotISAFuture] in893def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)),894 (v4i32 (VRLW v4i32:$vA, v4i32:$vB))>;895 896// Multiply897def : Pat<(mul v8i16:$vA, v8i16:$vB), (VMLADDUHM $vA, $vB, (v8i16(V_SET0H)))>;898 899// Add900def : Pat<(add (mul v8i16:$vA, v8i16:$vB), v8i16:$vC), (VMLADDUHM $vA, $vB, $vC)>;901 902 903// Fused negated multiply-subtract904def : Pat<(v4f32 (desugared_fneg905 (int_ppc_altivec_vmaddfp v4f32:$RA, v4f32:$RC,906 (desugared_fneg v4f32:$RB)))),907 (VNMSUBFP $RA, $RC, $RB)>;908 909// Saturating adds/subtracts.910def : Pat<(v16i8 (saddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDSBS $vA, $vB))>;911def : Pat<(v16i8 (uaddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDUBS $vA, $vB))>;912def : Pat<(v8i16 (saddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDSHS $vA, $vB))>;913def : Pat<(v8i16 (uaddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDUHS $vA, $vB))>;914def : Pat<(v4i32 (saddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDSWS $vA, $vB))>;915def : Pat<(v4i32 (uaddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDUWS $vA, $vB))>;916def : Pat<(v16i8 (ssubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBSBS $vA, $vB))>;917def : Pat<(v16i8 (usubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBUBS $vA, $vB))>;918def : Pat<(v8i16 (ssubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBSHS $vA, $vB))>;919def : Pat<(v8i16 (usubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBUHS $vA, $vB))>;920def : Pat<(v4i32 (ssubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBSWS $vA, $vB))>;921def : Pat<(v4i32 (usubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBUWS $vA, $vB))>;922 923// Loads.924def : Pat<(v4i32 (load ForceXForm:$src)), (LVX ForceXForm:$src)>;925 926// Stores.927def : Pat<(store v4i32:$rS, ForceXForm:$dst),928 (STVX $rS, ForceXForm:$dst)>;929 930// Bit conversions.931def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;932def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;933def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;934def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;935def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;936 937def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;938def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;939def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;940def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;941def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;942 943def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;944def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;945def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;946def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;947def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;948 949def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;950def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;951def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;952def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;953def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;954 955def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;956def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;957def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;958def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;959def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;960 961def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;962def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;963def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;964def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;965def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;966 967def : Pat<(f128 (bitconvert (v16i8 VRRC:$src))), (f128 VRRC:$src)>;968def : Pat<(f128 (bitconvert (v8i16 VRRC:$src))), (f128 VRRC:$src)>;969def : Pat<(f128 (bitconvert (v4i32 VRRC:$src))), (f128 VRRC:$src)>;970def : Pat<(f128 (bitconvert (v4f32 VRRC:$src))), (f128 VRRC:$src)>;971def : Pat<(f128 (bitconvert (v2f64 VRRC:$src))), (f128 VRRC:$src)>;972 973def : Pat<(v16i8 (bitconvert (f128 VRRC:$src))), (v16i8 VRRC:$src)>;974def : Pat<(v8i16 (bitconvert (f128 VRRC:$src))), (v8i16 VRRC:$src)>;975def : Pat<(v4i32 (bitconvert (f128 VRRC:$src))), (v4i32 VRRC:$src)>;976def : Pat<(v4f32 (bitconvert (f128 VRRC:$src))), (v4f32 VRRC:$src)>;977def : Pat<(v2f64 (bitconvert (f128 VRRC:$src))), (v2f64 VRRC:$src)>;978 979// Max/Min980def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)),981 (v16i8 (VMAXUB $src1, $src2))>;982def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)),983 (v16i8 (VMAXSB $src1, $src2))>;984def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)),985 (v8i16 (VMAXUH $src1, $src2))>;986def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)),987 (v8i16 (VMAXSH $src1, $src2))>;988def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)),989 (v4i32 (VMAXUW $src1, $src2))>;990def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)),991 (v4i32 (VMAXSW $src1, $src2))>;992def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)),993 (v16i8 (VMINUB $src1, $src2))>;994def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)),995 (v16i8 (VMINSB $src1, $src2))>;996def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)),997 (v8i16 (VMINUH $src1, $src2))>;998def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)),999 (v8i16 (VMINSH $src1, $src2))>;1000def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)),1001 (v4i32 (VMINUW $src1, $src2))>;1002def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)),1003 (v4i32 (VMINSW $src1, $src2))>;1004 1005// Shuffles.1006 1007// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)1008def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),1009 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;1010def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),1011 (VPKUWUM $vA, $vA)>;1012def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),1013 (VPKUHUM $vA, $vA)>;1014def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB),1015 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>;1016 1017 1018// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.1019// These fragments are matched for little-endian, where the inputs must1020// be swapped for correct semantics.1021def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),1022 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;1023def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),1024 (VPKUWUM $vB, $vA)>;1025def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),1026 (VPKUHUM $vB, $vA)>;1027 1028// Match vmrg*(x,x)1029def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),1030 (VMRGLB $vA, $vA)>;1031def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),1032 (VMRGLH $vA, $vA)>;1033def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),1034 (VMRGLW $vA, $vA)>;1035def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),1036 (VMRGHB $vA, $vA)>;1037def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),1038 (VMRGHH $vA, $vA)>;1039def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),1040 (VMRGHW $vA, $vA)>;1041 1042// Match vmrg*(y,x), i.e., swapped operands. These fragments1043// are matched for little-endian, where the inputs must be1044// swapped for correct semantics.1045def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),1046 (VMRGLB $vB, $vA)>;1047def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),1048 (VMRGLH $vB, $vA)>;1049def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),1050 (VMRGLW $vB, $vA)>;1051def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),1052 (VMRGHB $vB, $vA)>;1053def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),1054 (VMRGHH $vB, $vA)>;1055def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),1056 (VMRGHW $vB, $vA)>;1057 1058// Logical Operations1059def : Pat<(vnot v4i32:$vA), (VNOR $vA, $vA)>;1060 1061def : Pat<(vnot (or v4i32:$A, v4i32:$B)),1062 (VNOR $A, $B)>;1063def : Pat<(and v4i32:$A, (vnot v4i32:$B)),1064 (VANDC $A, $B)>;1065 1066def : Pat<(fmul v4f32:$vA, v4f32:$vB),1067 (VMADDFP $vA, $vB,1068 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>;1069 1070def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),1071 (VNMSUBFP $A, $B, $C)>;1072 1073def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),1074 (VMADDFP $A, $B, $C)>;1075def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),1076 (VNMSUBFP $A, $B, $C)>;1077 1078def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),1079 (VPERM $vA, $vB, $vC)>;1080def : Pat<(PPCvperm v2f64:$vA, v2f64:$vB, v16i8:$vC),1081 (VPERM $vA, $vB, $vC)>;1082 1083def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;1084def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;1085 1086// Vector shifts1087def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),1088 (v16i8 (VSLB $vA, $vB))>;1089def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),1090 (v8i16 (VSLH $vA, $vB))>;1091def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),1092 (v4i32 (VSLW $vA, $vB))>;1093def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)),1094 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;1095def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)),1096 (v16i8 (VSLB $vA, $vB))>;1097def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)),1098 (v8i16 (VSLH $vA, $vB))>;1099def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)),1100 (v4i32 (VSLW $vA, $vB))>;1101def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)),1102 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;1103 1104def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),1105 (v16i8 (VSRB $vA, $vB))>;1106def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),1107 (v8i16 (VSRH $vA, $vB))>;1108def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),1109 (v4i32 (VSRW $vA, $vB))>;1110def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)),1111 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;1112def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)),1113 (v16i8 (VSRB $vA, $vB))>;1114def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)),1115 (v8i16 (VSRH $vA, $vB))>;1116def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)),1117 (v4i32 (VSRW $vA, $vB))>;1118def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)),1119 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;1120 1121def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),1122 (v16i8 (VSRAB $vA, $vB))>;1123def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),1124 (v8i16 (VSRAH $vA, $vB))>;1125def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),1126 (v4i32 (VSRAW $vA, $vB))>;1127def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)),1128 (v16i8 (VSRAB $vA, $vB))>;1129def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)),1130 (v8i16 (VSRAH $vA, $vB))>;1131def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)),1132 (v4i32 (VSRAW $vA, $vB))>;1133 1134// Float to integer and integer to float conversions1135def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),1136 (VCTSXS_0 $vA)>;1137def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),1138 (VCTUXS_0 $vA)>;1139def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),1140 (VCFSX_0 $vA)>;1141def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),1142 (VCFUX_0 $vA)>;1143 1144// Floating-point rounding1145def : Pat<(v4f32 (ffloor v4f32:$vA)),1146 (VRFIM $vA)>;1147def : Pat<(v4f32 (fceil v4f32:$vA)),1148 (VRFIP $vA)>;1149def : Pat<(v4f32 (ftrunc v4f32:$vA)),1150 (VRFIZ $vA)>;1151def : Pat<(v4f32 (fnearbyint v4f32:$vA)),1152 (VRFIN $vA)>;1153 1154// Vector selection1155def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),1156 (VSEL $vC, $vB, $vA)>;1157def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),1158 (VSEL $vC, $vB, $vA)>;1159def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),1160 (VSEL $vC, $vB, $vA)>;1161def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),1162 (VSEL $vC, $vB, $vA)>;1163def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),1164 (VSEL $vC, $vB, $vA)>;1165def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),1166 (VSEL $vC, $vB, $vA)>;1167def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)),1168 (VSEL $vC, $vB, $vA)>;1169 1170// Vector Integer Average Instructions1171def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot v4i32:$vB)),1172 (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>;1173def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))),1174 (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>;1175def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),1176 (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>;1177def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot v4i32:$vB)),1178 (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>;1179def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))),1180 (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>;1181def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),1182 (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;1183 1184def : Pat<(v16i8 (shl v16i8:$vA, (v16i8 (immEQOneV)))),1185 (v16i8 (VADDUBM $vA, $vA))>;1186def : Pat<(v8i16 (shl v8i16:$vA, (v8i16 (immEQOneV)))),1187 (v8i16 (VADDUHM $vA, $vA))>;1188def : Pat<(v4i32 (shl v4i32:$vA, (v4i32 (immEQOneV)))),1189 (v4i32 (VADDUWM $vA, $vA))>;1190 1191} // end HasAltivec1192 1193// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.1194class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>1195 : VX_RD5_RSp5_PS1_XO9<xo,1196 (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, u1imm:$PS),1197 !strconcat(opc, " $VD, $VA, $VB, $PS"), IIC_VecFP, pattern> {1198 let Defs = [CR6];1199}1200 1201// [PO VRT VRA VRB 1 / XO]1202class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>1203 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1204 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP, pattern> {1205 let Defs = [CR6];1206 let PS = 0;1207}1208 1209let Predicates = [HasP8Altivec] in {1210 1211let isCommutable = 1 in {1212def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,1213 v2i64, v4i32>;1214def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,1215 v2i64, v4i32>;1216def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,1217 v2i64, v4i32>;1218def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,1219 v2i64, v4i32>;1220def VMULUWM : VXForm_1<137, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1221 "vmuluwm $VD, $VA, $VB", IIC_VecGeneral,1222 [(set v4i32:$VD, (mul v4i32:$VA, v4i32:$VB))]>;1223def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;1224def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;1225def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;1226def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;1227} // isCommutable1228 1229// Vector merge1230def VMRGEW : VXForm_1<1932, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1231 "vmrgew $VD, $VA, $VB", IIC_VecFP,1232 [(set v16i8:$VD,1233 (v16i8 (vmrgew_shuffle v16i8:$VA, v16i8:$VB)))]>;1234def VMRGOW : VXForm_1<1676, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1235 "vmrgow $VD, $VA, $VB", IIC_VecFP,1236 [(set v16i8:$VD,1237 (v16i8 (vmrgow_shuffle v16i8:$VA, v16i8:$VB)))]>;1238 1239// Match vmrgew(x,x) and vmrgow(x,x)1240def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),1241 (VMRGEW $vA, $vA)>;1242def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),1243 (VMRGOW $vA, $vA)>;1244 1245// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments1246// are matched for little-endian, where the inputs must be swapped for correct1247// semantics.w1248def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),1249 (VMRGEW $vB, $vA)>;1250def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),1251 (VMRGOW $vB, $vA)>;1252 1253// Vector rotates.1254def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;1255 1256def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)),1257 (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>;1258 1259// Vector shifts1260def VSLD : VXForm_1<1476, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1261 "vsld $VD, $VA, $VB", IIC_VecGeneral, []>;1262def VSRD : VXForm_1<1732, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1263 "vsrd $VD, $VA, $VB", IIC_VecGeneral, []>;1264def VSRAD : VXForm_1<964, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1265 "vsrad $VD, $VA, $VB", IIC_VecGeneral, []>;1266 1267def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)),1268 (v2i64 (VSLD $vA, $vB))>;1269def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)),1270 (v2i64 (VSLD $vA, $vB))>;1271def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)),1272 (v2i64 (VSRD $vA, $vB))>;1273def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)),1274 (v2i64 (VSRD $vA, $vB))>;1275def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)),1276 (v2i64 (VSRAD $vA, $vB))>;1277def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)),1278 (v2i64 (VSRAD $vA, $vB))>;1279 1280// Vector Integer Arithmetic Instructions1281let isCommutable = 1 in {1282def VADDUDM : VXForm_1<192, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1283 "vaddudm $VD, $VA, $VB", IIC_VecGeneral,1284 [(set v2i64:$VD, (add v2i64:$VA, v2i64:$VB))]>;1285def VADDUQM : VXForm_1<256, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1286 "vadduqm $VD, $VA, $VB", IIC_VecGeneral,1287 [(set v1i128:$VD, (add v1i128:$VA, v1i128:$VB))]>;1288} // isCommutable1289 1290// Vector Quadword Add1291def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>;1292def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>;1293def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>;1294 1295// Vector Doubleword Subtract1296def VSUBUDM : VXForm_1<1216, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1297 "vsubudm $VD, $VA, $VB", IIC_VecGeneral,1298 [(set v2i64:$VD, (sub v2i64:$VA, v2i64:$VB))]>;1299 1300// Vector Quadword Subtract1301def VSUBUQM : VXForm_1<1280, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1302 "vsubuqm $VD, $VA, $VB", IIC_VecGeneral,1303 [(set v1i128:$VD, (sub v1i128:$VA, v1i128:$VB))]>;1304def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>;1305def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>;1306def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>;1307 1308// Count Leading Zeros1309def VCLZB : VXForm_2<1794, (outs vrrc:$VD), (ins vrrc:$VB),1310 "vclzb $VD, $VB", IIC_VecGeneral,1311 [(set v16i8:$VD, (ctlz v16i8:$VB))]>;1312def VCLZH : VXForm_2<1858, (outs vrrc:$VD), (ins vrrc:$VB),1313 "vclzh $VD, $VB", IIC_VecGeneral,1314 [(set v8i16:$VD, (ctlz v8i16:$VB))]>;1315def VCLZW : VXForm_2<1922, (outs vrrc:$VD), (ins vrrc:$VB),1316 "vclzw $VD, $VB", IIC_VecGeneral,1317 [(set v4i32:$VD, (ctlz v4i32:$VB))]>;1318def VCLZD : VXForm_2<1986, (outs vrrc:$VD), (ins vrrc:$VB),1319 "vclzd $VD, $VB", IIC_VecGeneral,1320 [(set v2i64:$VD, (ctlz v2i64:$VB))]>;1321 1322// Population Count1323def VPOPCNTB : VXForm_2<1795, (outs vrrc:$VD), (ins vrrc:$VB),1324 "vpopcntb $VD, $VB", IIC_VecGeneral,1325 [(set v16i8:$VD, (ctpop v16i8:$VB))]>;1326def VPOPCNTH : VXForm_2<1859, (outs vrrc:$VD), (ins vrrc:$VB),1327 "vpopcnth $VD, $VB", IIC_VecGeneral,1328 [(set v8i16:$VD, (ctpop v8i16:$VB))]>;1329def VPOPCNTW : VXForm_2<1923, (outs vrrc:$VD), (ins vrrc:$VB),1330 "vpopcntw $VD, $VB", IIC_VecGeneral,1331 [(set v4i32:$VD, (ctpop v4i32:$VB))]>;1332def VPOPCNTD : VXForm_2<1987, (outs vrrc:$VD), (ins vrrc:$VB),1333 "vpopcntd $VD, $VB", IIC_VecGeneral,1334 [(set v2i64:$VD, (ctpop v2i64:$VB))]>;1335 1336let isCommutable = 1 in {1337// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the1338// VSX equivalents. We need to fix this up at some point. Two possible1339// solutions for this problem:1340// 1. Disable Altivec patterns that compete with VSX patterns using the1341// !HasVSX predicate. This essentially favours VSX over Altivec, in1342// hopes of reducing register pressure (larger register set using VSX1343// instructions than VMX instructions)1344// 2. Employ a more disciplined use of AddedComplexity, which would provide1345// more fine-grained control than option 1. This would be beneficial1346// if we find situations where Altivec is really preferred over VSX.1347def VEQV : VXForm_1<1668, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1348 "veqv $VD, $VA, $VB", IIC_VecGeneral,1349 [(set v4i32:$VD, (vnot (xor v4i32:$VA, v4i32:$VB)))]>;1350def VNAND : VXForm_1<1412, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1351 "vnand $VD, $VA, $VB", IIC_VecGeneral,1352 [(set v4i32:$VD, (vnot (and v4i32:$VA, v4i32:$VB)))]>;1353} // isCommutable1354 1355def VORC : VXForm_1<1348, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1356 "vorc $VD, $VA, $VB", IIC_VecGeneral,1357 [(set v4i32:$VD, (or v4i32:$VA,1358 (vnot v4i32:$VB)))]>;1359 1360// i64 element comparisons.1361def VCMPEQUD : VCMP <199, "vcmpequd $VD, $VA, $VB" , v2i64>;1362def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $VD, $VA, $VB", v2i64>;1363def VCMPGTSD : VCMP <967, "vcmpgtsd $VD, $VA, $VB" , v2i64>;1364def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $VD, $VA, $VB", v2i64>;1365def VCMPGTUD : VCMP <711, "vcmpgtud $VD, $VA, $VB" , v2i64>;1366def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $VD, $VA, $VB", v2i64>;1367 1368// The cryptography instructions that do not require Category:Vector.Crypto1369def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",1370 int_ppc_altivec_crypto_vpmsumb, v16i8>;1371def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",1372 int_ppc_altivec_crypto_vpmsumh, v8i16>;1373def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",1374 int_ppc_altivec_crypto_vpmsumw, v4i32>;1375def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",1376 int_ppc_altivec_crypto_vpmsumd, v2i64>;1377def VPERMXOR : VAForm_1<45, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),1378 "vpermxor $RT, $RA, $RB, $RC", IIC_VecFP, []>;1379 1380// Vector doubleword integer pack and unpack.1381let hasSideEffects = 1 in {1382 def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,1383 v4i32, v2i64>;1384 def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,1385 v4i32, v2i64>;1386 def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,1387 v4i32, v2i64>;1388}1389def VPKUDUM : VXForm_1<1102, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1390 "vpkudum $VD, $VA, $VB", IIC_VecFP,1391 [(set v16i8:$VD,1392 (vpkudum_shuffle v16i8:$VA, v16i8:$VB))]>;1393def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,1394 v2i64, v4i32>;1395def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,1396 v2i64, v4i32>;1397def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>;1398def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>;1399 1400def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)),1401 (BCDADD_rec $vA, $vB, $PS)>;1402def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, timm:$PS)),1403 (BCDSUB_rec $vA, $vB, $PS)>;1404 1405// Shuffle patterns for unary and swapped (LE) vector pack modulo.1406def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef),1407 (VPKUDUM $vA, $vA)>;1408def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB),1409 (VPKUDUM $vB, $vA)>;1410 1411def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>;1412def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq,1413 v2i64, v16i8>;1414} // end HasP8Altivec1415 1416// Crypto instructions (from builtins)1417let Predicates = [HasP8Crypto] in {1418def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",1419 int_ppc_altivec_crypto_vshasigmaw, v4i32>;1420def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",1421 int_ppc_altivec_crypto_vshasigmad, v2i64>;1422def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,1423 v2i64>;1424def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",1425 int_ppc_altivec_crypto_vcipherlast, v2i64>;1426def VNCIPHER : VX1_Int_Ty<1352, "vncipher",1427 int_ppc_altivec_crypto_vncipher, v2i64>;1428def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",1429 int_ppc_altivec_crypto_vncipherlast, v2i64>;1430def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;1431} // HasP8Crypto1432 1433// The following altivec instructions were introduced in Power ISA 3.01434let Predicates = [HasP9Altivec] in {1435 1436// Vector Multiply-Sum1437def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,1438 v1i128, v2i64, v1i128>;1439 1440// i8 element comparisons.1441def VCMPNEB : VCMP < 7, "vcmpneb $VD, $VA, $VB" , v16i8>;1442def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $VD, $VA, $VB" , v16i8>;1443def VCMPNEZB : VCMP <263, "vcmpnezb $VD, $VA, $VB" , v16i8>;1444def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $VD, $VA, $VB", v16i8>;1445 1446// i16 element comparisons.1447def VCMPNEH : VCMP < 71, "vcmpneh $VD, $VA, $VB" , v8i16>;1448def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $VD, $VA, $VB" , v8i16>;1449def VCMPNEZH : VCMP <327, "vcmpnezh $VD, $VA, $VB" , v8i16>;1450def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $VD, $VA, $VB", v8i16>;1451 1452// i32 element comparisons.1453def VCMPNEW : VCMP <135, "vcmpnew $VD, $VA, $VB" , v4i32>;1454def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $VD, $VA, $VB" , v4i32>;1455def VCMPNEZW : VCMP <391, "vcmpnezw $VD, $VA, $VB" , v4i32>;1456def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $VD, $VA, $VB", v4i32>;1457 1458// VX-Form: [PO VRT / UIM VRB XO].1459// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent1460// "/ UIM" (1 + 4 bit)1461class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>1462 : VXForm_1<xo, (outs vrrc:$VD), (ins u4imm:$VA, vrrc:$VB),1463 !strconcat(opc, " $VD, $VB, $VA"), IIC_VecGeneral, pattern>;1464 1465class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>1466 : VXForm_1<xo, (outs g8rc:$VD), (ins g8rc:$VA, vrrc:$VB),1467 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>;1468 1469// Vector Extract Unsigned1470def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;1471def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;1472def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;1473def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;1474 1475// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed1476let hasSideEffects = 0 in {1477def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64;1478def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64;1479def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64;1480def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64;1481def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64;1482def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64;1483}1484 1485// Vector Insert Element Instructions1486def VINSERTB : VXForm_1<781, (outs vrrc:$VD),1487 (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB),1488 "vinsertb $VD, $VB, $VA", IIC_VecGeneral,1489 [(set v16i8:$VD, (PPCvecinsert v16i8:$VDi, v16i8:$VB,1490 imm32SExt16:$VA))]>,1491 RegConstraint<"$VDi = $VD">;1492def VINSERTH : VXForm_1<845, (outs vrrc:$VD),1493 (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB),1494 "vinserth $VD, $VB, $VA", IIC_VecGeneral,1495 [(set v8i16:$VD, (PPCvecinsert v8i16:$VDi, v8i16:$VB,1496 imm32SExt16:$VA))]>,1497 RegConstraint<"$VDi = $VD">;1498def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;1499def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;1500 1501class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>1502 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$VD), (ins vrrc:$VB),1503 !strconcat(opc, " $VD, $VB"), IIC_VecGeneral, pattern>;1504class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>1505 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$VD), (ins vfrc:$VB),1506 !strconcat(opc, " $VD, $VB"), IIC_VecGeneral, pattern>;1507 1508// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[RD]1509def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$VD), (ins vrrc:$VB),1510 "vclzlsbb $VD, $VB", IIC_VecGeneral,1511 [(set i32:$VD, (int_ppc_altivec_vclzlsbb1512 v16i8:$VB))]>;1513def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$VD), (ins vrrc:$VB),1514 "vctzlsbb $VD, $VB", IIC_VecGeneral,1515 [(set i32:$VD, (int_ppc_altivec_vctzlsbb1516 v16i8:$VB))]>;1517// Vector Count Trailing Zeros1518def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",1519 [(set v16i8:$VD, (cttz v16i8:$VB))]>;1520def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",1521 [(set v8i16:$VD, (cttz v8i16:$VB))]>;1522def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",1523 [(set v4i32:$VD, (cttz v4i32:$VB))]>;1524def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",1525 [(set v2i64:$VD, (cttz v2i64:$VB))]>;1526 1527// Vector Extend Sign1528def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w",1529 [(set v4i32:$VD, (int_ppc_altivec_vextsb2w v16i8:$VB))]>;1530def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w",1531 [(set v4i32:$VD, (int_ppc_altivec_vextsh2w v8i16:$VB))]>;1532def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d",1533 [(set v2i64:$VD, (int_ppc_altivec_vextsb2d v16i8:$VB))]>;1534def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d",1535 [(set v2i64:$VD, (int_ppc_altivec_vextsh2d v8i16:$VB))]>;1536def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d",1537 [(set v2i64:$VD, (int_ppc_altivec_vextsw2d v4i32:$VB))]>;1538let isCodeGenOnly = 1 in {1539 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;1540 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;1541 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;1542 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;1543 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;1544}1545 1546def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>;1547def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>;1548def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>;1549def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>;1550def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>;1551 1552// Vector Integer Negate1553def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",1554 [(set v4i32:$VD,1555 (sub (v4i32 immAllZerosV), v4i32:$VB))]>;1556 1557def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",1558 [(set v2i64:$VD,1559 (sub (v2i64 immAllZerosV), v2i64:$VB))]>;1560 1561// Vector Parity Byte1562def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$VD,1563 (int_ppc_altivec_vprtybw v4i32:$VB))]>;1564def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$VD,1565 (int_ppc_altivec_vprtybd v2i64:$VB))]>;1566def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$VD,1567 (int_ppc_altivec_vprtybq v1i128:$VB))]>;1568 1569// Vector (Bit) Permute (Right-indexed)1570def VBPERMD : VX1_Int_Ty3<1484, "vbpermd", int_ppc_altivec_vbpermd,1571 v2i64, v2i64, v16i8>;1572def VPERMR : VAForm_1a<59, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),1573 "vpermr $RT, $RA, $RB, $RC", IIC_VecFP, []>;1574 1575class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>1576 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1577 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP, pattern>;1578 1579// Vector Rotate Left Mask/Mask-Insert1580def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm",1581 [(set v4i32:$VD,1582 (int_ppc_altivec_vrlwnm v4i32:$VA,1583 v4i32:$VB))]>;1584def VRLWMI : VXForm_1<133, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),1585 "vrlwmi $VD, $VA, $VB", IIC_VecFP,1586 [(set v4i32:$VD,1587 (int_ppc_altivec_vrlwmi v4i32:$VA, v4i32:$VB,1588 v4i32:$VDi))]>,1589 RegConstraint<"$VDi = $VD">;1590def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm",1591 [(set v2i64:$VD,1592 (int_ppc_altivec_vrldnm v2i64:$VA,1593 v2i64:$VB))]>;1594def VRLDMI : VXForm_1<197, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),1595 "vrldmi $VD, $VA, $VB", IIC_VecFP,1596 [(set v2i64:$VD,1597 (int_ppc_altivec_vrldmi v2i64:$VA, v2i64:$VB,1598 v2i64:$VDi))]>,1599 RegConstraint<"$VDi = $VD">;1600 1601// Vector Shift Left/Right1602def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",1603 [(set v16i8 : $VD, (int_ppc_altivec_vslv v16i8 : $VA, v16i8 : $VB))]>;1604def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",1605 [(set v16i8 : $VD, (int_ppc_altivec_vsrv v16i8 : $VA, v16i8 : $VB))]>;1606 1607// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword1608def VMUL10UQ : VXForm_BX<513, (outs vrrc:$VD), (ins vrrc:$VA),1609 "vmul10uq $VD, $VA", IIC_VecFP, []>;1610def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$VD), (ins vrrc:$VA),1611 "vmul10cuq $VD, $VA", IIC_VecFP, []>;1612 1613// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword1614def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;1615def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;1616 1617// Decimal Integer Format Conversion Instructions1618 1619// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.1620class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,1621 list<dag> pattern>1622 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$VD), (ins vrrc:$VB, u1imm:$PS),1623 !strconcat(opc, " $VD, $VB, $PS"), IIC_VecFP, pattern> {1624 let Defs = [CR6];1625}1626 1627// [PO VRT EO VRB 1 / XO]1628class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,1629 list<dag> pattern>1630 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$VD), (ins vrrc:$VB),1631 !strconcat(opc, " $VD, $VB"), IIC_VecFP, pattern> {1632 let Defs = [CR6];1633 let PS = 0;1634}1635 1636// Decimal Convert From/to National/Zoned/Signed-QWord1637def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." ,1638 [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, timm:$PS))]>;1639def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , 1640 [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, timm:$PS))]>;1641def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , 1642 [(set v16i8:$VD, (int_ppc_packed2national v16i8:$VB))]>;1643def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , 1644 [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, timm:$PS))]>;1645def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;1646def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;1647 1648// Decimal Copy-Sign/Set-Sign1649let Defs = [CR6] in1650def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.",1651 [(set v16i8:$VD, (int_ppc_bcdcopysign v16i8:$VA, v16i8:$VB))]>;1652 1653def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.",1654 [(set v16i8:$VD, (int_ppc_bcdsetsign v16i8:$VB, i32:$PS))]>;1655 1656// Decimal Shift/Unsigned-Shift/Shift-and-Round1657def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;1658def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>;1659def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;1660 1661// Decimal (Unsigned) Truncate1662def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;1663def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;1664 1665// Absolute Difference1666def VABSDUB : VXForm_1<1027, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1667 "vabsdub $VD, $VA, $VB", IIC_VecGeneral,1668 [(set v16i8:$VD, (int_ppc_altivec_vabsdub v16i8:$VA, v16i8:$VB))]>;1669def VABSDUH : VXForm_1<1091, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1670 "vabsduh $VD, $VA, $VB", IIC_VecGeneral,1671 [(set v8i16:$VD, (int_ppc_altivec_vabsduh v8i16:$VA, v8i16:$VB))]>;1672def VABSDUW : VXForm_1<1155, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1673 "vabsduw $VD, $VA, $VB", IIC_VecGeneral,1674 [(set v4i32:$VD, (int_ppc_altivec_vabsduw v4i32:$VA, v4i32:$VB))]>;1675 1676} // end HasP9Altivec1677