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1//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//2//3// The LLVM Compiler Infrastructure4//5// This file is distributed under the University of Illinois Open Source6// License. See LICENSE.TXT for details.7//8//===----------------------------------------------------------------------===//9//10// This file describes the instructions introduced for the Future CPU.11//12//===----------------------------------------------------------------------===//13 14class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,15 list<dag> pattern> : I<opcode, OOL, IOL, asmstr, NoItinerary> {16 bits<5> RS;17 18 let Pattern = pattern;19 20 let Inst{6...10} = RS;21 let Inst{11...20} = 0;22 let Inst{21...30} = xo;23 let Inst{31} = 0;24}25 26class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,27 string asmstr, list<dag> pattern>28 : I<opcode, OOL, IOL, asmstr, NoItinerary> {29 bits<5> RT;30 bits<5> RA;31 bits<5> RB;32 bit L;33 34 let Pattern = pattern;35 36 bit RC = 0; // set by isRecordForm37 38 let Inst{6...10} = RT;39 let Inst{11...15} = RA;40 let Inst{16...20} = RB;41 let Inst{21} = L;42 let Inst{22...30} = xo;43 let Inst{31} = RC;44}45 46multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,47 string asmbase, string asmstr, list<dag> pattern> {48 let BaseName = asmbase in {49 def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,50 !strconcat(asmbase, !strconcat(" ", asmstr)),51 pattern>,52 RecFormRel;53 let Defs = [CR0] in def _rec54 : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,55 !strconcat(asmbase, !strconcat(". ", asmstr)), []>,56 isRecordForm, RecFormRel;57 }58}59 60class VXForm_VRTB5_Base<bits<11> xo, dag OOL, dag IOL, string asmstr,61 list<dag> pattern>62 : I<4, OOL, IOL, asmstr, NoItinerary> {63 bits<5> VRT;64 bits<5> VRB;65 66 let Pattern = pattern;67 68 let Inst{6...10} = VRT;69 let Inst{16...20} = VRB;70 let Inst{21...31} = xo;71}72 73class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,74 list<dag> pattern>75 : VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {76 77 let Inst{11...15} = R;78}79 80class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,81 list<dag> pattern>82 : VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {83 bits<2> UIM;84 85 let Inst{11...13} = R;86 let Inst{14...15} = UIM;87}88 89class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,90 list<dag> pattern>91 : VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {92 bits<1> UIM;93 94 let Inst{11...14} = R;95 let Inst{15} = UIM;96}97 98class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,99 list<dag> pattern>100 : VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {101 bits<3> UIM;102 103 let Inst{11...12} = R;104 let Inst{13...15} = UIM;105}106 107class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,108 list<dag> pattern>109 : VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {110 bits<5> VRA;111 112 let Inst{11...15} = VRA;113}114 115class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,116 list<dag> pattern>117 : I<60, OOL, IOL, asmstr, NoItinerary> {118 119 bits<5> XTp;120 bits<5> XBp;121 bits<2> M;122 123 let Pattern = pattern;124 125 let Inst{6...9} = XTp{3...0};126 let Inst {10} = XTp{4};127 let Inst{15} = M{0};128 let Inst{16...19} = XBp{3...0};129 let Inst{20} = M{1};130 let Inst{21...29} = xo;131 let Inst{30} = XBp{4};132}133 134class XX3Form_XTABp5_M2<bits<8> xo, dag OOL, dag IOL, string asmstr,135 list<dag> pattern>136 : I<60, OOL, IOL, asmstr, NoItinerary> {137 138 bits<5> XTp;139 bits<5> XAp;140 bits<5> XBp;141 bits<2> M;142 143 let Pattern = pattern;144 145 let Inst{6...9} = XTp{3...0};146 let Inst{10} = XTp{4};147 let Inst{11...14} = XAp{3...0};148 let Inst{15} = M{0};149 let Inst{16...19} = XBp{3...0};150 let Inst{20} = M{1};151 let Inst{21...28} = xo;152 let Inst{29} = XAp{4};153 let Inst{30} = XBp{4};154}155 156class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,157 list<dag> pattern>158 : I<60, OOL, IOL, asmstr, NoItinerary> {159 160 bits<6> XT;161 bits<6> XA;162 bits<6> XB;163 bits<1> P;164 165 let Pattern = pattern;166 167 let Inst{6...10} = XT{4...0};168 let Inst{11...15} = XA{4...0};169 let Inst{16...20} = XB{4...0};170 let Inst{21...22} = 3;171 let Inst{23} = P;172 let Inst{24...28} = xo;173 let Inst{29} = XA{5};174 let Inst{30} = XB{5};175 let Inst{31} = XT{5};176}177 178class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,179 list<dag> pattern>180 : I<opcode, OOL, IOL, asmstr, NoItinerary> {181 182 bits<6> XT;183 bits<6> XA;184 bits<6> XB;185 186 let Pattern = pattern;187 188 let Inst{6...10} = XT{4...0};189 let Inst{11...15} = XA{4...0};190 let Inst{16...20} = XB{4...0};191 let Inst{21...28} = xo;192 let Inst{29} = XA{5};193 let Inst{30} = XB{5};194 let Inst{31} = XT{5};195}196 197class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,198 InstrItinClass itin, list<dag> pattern>199 : I<opCode, OOL, IOL, asmstr, itin> {200 201 bits<5> RB;202 bits<5> RS;203 204 let Pattern = pattern;205 206 let Inst{6...10} = RS;207 let Inst{11...15} = 0;208 let Inst{16...20} = RB;209 let Inst{21...30} = xo;210 let Inst{31} = 0;211}212 213class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,214 list<dag> pattern>215 : I<59, OOL, IOL, asmstr, NoItinerary> {216 bits<6> XT;217 bits<6> XA;218 bits<6> XB;219 220 let Pattern = pattern;221 222 let Inst{6...10} = XT{4...0};223 let Inst{11...15} = XA{4...0};224 let Inst{16...20} = XB{4...0};225 let Inst{24...28} = xo;226 let Inst{29} = XA{5};227 let Inst{30} = XB{5};228 let Inst{31} = XT{5};229}230 231class XX3Form_XTAB6_S3<bits<5> xo, dag OOL, dag IOL, string asmstr,232 list<dag> pattern>233 : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {234 235 bits<3> S;236 let Inst{21...23} = S;237}238 239class XX3Form_XTAB6_3S1<bits<5> xo, dag OOL, dag IOL, string asmstr,240 list<dag> pattern>241 : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {242 243 bits<1> S0;244 bits<1> S1;245 bits<1> S2;246 247 let Inst{21} = S0;248 let Inst{22} = S1;249 let Inst{23} = S2;250}251 252class XX3Form_XTAB6_2S1<bits<5> xo, dag OOL, dag IOL, string asmstr,253 list<dag> pattern>254 : XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {255 256 bits<1> S1;257 bits<1> S2;258 259 let Inst{21} = 0;260 let Inst{22} = S1;261 let Inst{23} = S2;262}263 264class XX3Form_XTAB6_P<bits<7> xo, dag OOL, dag IOL, string asmstr,265 list<dag> pattern>266 : I<59, OOL, IOL, asmstr, NoItinerary> {267 268 bits<6> XT;269 bits<6> XA;270 bits<6> XB;271 bits<1> P;272 273 let Pattern = pattern;274 275 let Inst{6...10} = XT{4...0};276 let Inst{11...15} = XA{4...0};277 let Inst{16...20} = XB{4...0};278 let Inst{21} = P;279 let Inst{22...28} = xo;280 let Inst{29} = XA{5};281 let Inst{30} = XB{5};282 let Inst{31} = XT{5};283}284 285// Prefix instruction classes.286 287class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr,288 InstrItinClass itin, list<dag> pattern>289 : PI<1, opcode, OOL, IOL, asmstr, itin> {290 bits<6> XT;291 bits<6> XA;292 bits<6> XB;293 bits<6> XC;294 bits<1> P;295 296 let Pattern = pattern;297 298 // The prefix.299 let Inst{6...7} = 1;300 let Inst{8...11} = 0;301 302 // The instruction.303 let Inst{38...42} = XT{4...0};304 let Inst{43...47} = XA{4...0};305 let Inst{48...52} = XB{4...0};306 let Inst{53...57} = XC{4...0};307 let Inst{58} = 1;308 let Inst{59} = P;309 let Inst{60} = XC{5};310 let Inst{61} = XA{5};311 let Inst{62} = XB{5};312 let Inst{63} = XT{5};313}314 315class MLS_DForm_R_SI32_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,316 InstrItinClass itin, list<dag> pattern>317 : PI<1, opcode, OOL, IOL, asmstr, itin> {318 bits<5> RT;319 bits<5> RA;320 bits<32> SI;321 322 let Pattern = pattern;323 324 // The prefix.325 let Inst{6...7} = 2;326 let Inst{8} = 0;327 let Inst{11} = PCRel;328 let Inst{16...31} = SI{31...16};329 330 // The instruction.331 let Inst{38...42} = RT;332 let Inst{43...47} = RA;333 let Inst{48...63} = SI{15...0};334}335 336multiclass MLS_DForm_R_SI32_RTA5_p<bits<6> opcode, dag OOL, dag IOL,337 dag PCRel_IOL, string asmstr,338 InstrItinClass itin> {339 def NAME : MLS_DForm_R_SI32_RTA5<opcode, OOL, IOL, !strconcat(asmstr, ", 0"),340 itin, []>;341 def pc : MLS_DForm_R_SI32_RTA5<opcode, OOL, PCRel_IOL,342 !strconcat(asmstr, ", 1"), itin, []>,343 isPCRel;344}345 346//-------------------------- Instruction definitions -------------------------//347// Predicate combinations available:348// [IsISAFuture]349// [IsISAFuture, PrefixInstrs]350// [HasVSX, IsISAFuture]351// [HasVSX, PrefixInstrs, IsISAFuture]352 353let Predicates = [IsISAFuture] in {354 defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),355 (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",356 "$RT, $L, $RA, $RB", []>;357 def TLBSYNCIO358 : XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;359 def PTESYNCIO360 : XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;361 def TLBIEP : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),362 (ins gprc:$RB, gprc:$RS, u2imm:$RIC,363 u1imm:$PRS, u1imm:$R),364 "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;365 def TLBIEIO366 : XForm_RSB5_UIMM2<31, 18, (outs), (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC),367 "tlbieio $RB, $RS, $RIC", []>;368 def MTLPL : XForm_RBS5<31, 275, (outs), (ins gprc:$RB, gprc:$RS),369 "mtlpl $RB, $RS", IIC_SprMTSPR, []>;370 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {371 def TLBIEP8372 : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),373 (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,374 u1imm:$PRS, u1imm:$R),375 "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;376 def MTLPL8 : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),377 "mtlpl $RB, $RS", IIC_SprMTSPR, []>, isPPC64;378 }379}380 381let Predicates = [IsISAFuture, PrefixInstrs] in {382 defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT),383 (ins gprc_nor0:$RA, s32imm:$SI),384 (ins immZero:$RA, s32imm_pcrel:$SI),385 "paddis $RT, $RA, $SI", IIC_LdStLFD>;386 let Interpretation64Bit = 1, isCodeGenOnly = 1 in387 defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT),388 (ins g8rc_nox0:$RA, s32imm:$SI),389 (ins immZero:$RA, s32imm_pcrel:$SI),390 "paddis $RT, $RA, $SI", IIC_LdStLFD>;391}392 393let Predicates = [HasVSX, IsISAFuture] in {394 let mayLoad = 1 in {395 def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),396 (ins (memr $RA):$addr, g8rc:$RB),397 "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;398 def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT),399 (ins (memr $RA):$addr, g8rc:$RB),400 "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;401 def LXVPRL : XForm_XTp5_RAB5<31, 589, (outs vsrprc:$XTp),402 (ins (memr $RA):$addr, g8rc:$RB),403 "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;404 def LXVPRLL : XForm_XTp5_RAB5<31, 621, (outs vsrprc:$XTp),405 (ins (memr $RA):$addr, g8rc:$RB),406 "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;407 def LXVPB32X408 : XForm_XTp5_RAB5<31, 877, (outs vsrprc:$XTp),409 (ins (memr $RA):$addr, g8rc:$RB),410 "lxvpb32x $XTp, $addr, $RB", IIC_LdStLFD, []>;411 }412 413 let mayStore = 1 in {414 def STXVRL : XX1Form_memOp<31, 653, (outs),415 (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),416 "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;417 def STXVRLL : XX1Form_memOp<31, 685, (outs),418 (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),419 "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;420 def STXVPRL : XForm_XTp5_RAB5<31, 717, (outs),421 (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),422 "stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;423 def STXVPRLL424 : XForm_XTp5_RAB5<31, 749, (outs),425 (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),426 "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;427 def STXVPB32X428 : XForm_XTp5_RAB5<31, 1005, (outs),429 (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),430 "stxvpb32x $XTp, $addr, $RB", IIC_LdStLFD, []>;431 }432 433 def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),434 "vupkhsntob $VRT, $VRB", []>;435 def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB),436 "vupklsntob $VRT, $VRB", []>;437 def VUPKINT4TOBF16438 : VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),439 "vupkint4tobf16 $VRT, $VRB, $UIM", []>;440 def VUPKINT8TOBF16441 : VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM),442 "vupkint8tobf16 $VRT, $VRB, $UIM", []>;443 def VUPKINT8TOFP32444 : VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),445 "vupkint8tofp32 $VRT, $VRB, $UIM", []>;446 def VUPKINT4TOFP32447 : VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),448 "vupkint4tofp32 $VRT, $VRB, $UIM", []>;449 450 def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),451 "vucmprhn $VRT, $VRA, $VRB", []>;452 def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),453 "vucmprln $VRT, $VRA, $VRB", []>;454 def VUCMPRHB455 : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),456 "vucmprhb $VRT, $VRA, $VRB", []>;457 def VUCMPRLB458 : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),459 "vucmprlb $VRT, $VRA, $VRB", []>;460 def VUCMPRHH461 : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),462 "vucmprhh $VRT, $VRA, $VRB", []>;463 def VUCMPRLH464 : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),465 "vucmprlh $VRT, $VRA, $VRB", []>;466 467 def XVRLW : XX3Form_XTAB6<60, 184, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),468 "xvrlw $XT, $XA, $XB",469 [(set v4i32:$XT, (int_ppc_vsx_xvrlw v4i32:$XA,470 v4i32:$XB))]>;471 472 // AES Acceleration Instructions473 def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp),474 (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),475 "xxaesencp $XTp, $XAp, $XBp, $M", []>;476 def XXAESDECP : XX3Form_XTABp5_M2<202, (outs vsrprc:$XTp),477 (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),478 "xxaesdecp $XTp, $XAp, $XBp, $M", []>;479 def XXAESGENLKP : XX3Form_XTBp5_M2<420, (outs vsrprc:$XTp),480 (ins vsrprc:$XBp, u2imm:$M),481 "xxaesgenlkp $XTp, $XBp, $M", []>;482 def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT),483 (ins vsrc:$XA, vsrc:$XB, u1imm:$P),484 "xxgfmul128 $XT, $XA, $XB, $P", []>;485 486 // VSX Vector Integer Arithmetic Instructions487 def XVADDUWM : XX3Form_XTAB6<60, 131, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),488 "xvadduwm $XT, $XA, $XB", []>;489 def XVADDUHM : XX3Form_XTAB6<60, 139, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),490 "xvadduhm $XT, $XA, $XB", []>;491 def XVSUBUWM: XX3Form_XTAB6<60, 147, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),492 "xvsubuwm $XT, $XA, $XB", []>;493 def XVSUBUHM: XX3Form_XTAB6<60, 155, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),494 "xvsubuhm $XT, $XA, $XB", []>;495 def XVMULUWM: XX3Form_XTAB6<60, 163, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),496 "xvmuluwm $XT, $XA, $XB", []>;497 def XVMULUHM: XX3Form_XTAB6<60, 171, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),498 "xvmuluhm $XT, $XA, $XB", []>;499 def XVMULHSW: XX3Form_XTAB6<60, 179, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),500 "xvmulhsw $XT, $XA, $XB", []>;501 def XVMULHSH: XX3Form_XTAB6<60, 187, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),502 "xvmulhsh $XT, $XA, $XB", []>;503 def XVMULHUW: XX3Form_XTAB6<60, 114, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),504 "xvmulhuw $XT, $XA, $XB", []>;505 def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),506 "xvmulhuh $XT, $XA, $XB", []>;507 508 // Elliptic Curve Cryptography Acceleration Instructions.509 def XXMULMUL510 : XX3Form_XTAB6_S3<1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u3imm:$S),511 "xxmulmul $XT, $XA, $XB, $S", []>;512 def XXMULMULHIADD513 : XX3Form_XTAB6_3S1<9, (outs vsrc:$XT),514 (ins vsrc:$XA, vsrc:$XB, u1imm:$S0, u1imm:$S1,515 u1imm:$S2),516 "xxmulmulhiadd $XT, $XA, $XB, $S0, $S1, $S2", []>;517 def XXMULMULLOADD518 : XX3Form_XTAB6_2S1<17, (outs vsrc:$XT),519 (ins vsrc:$XA, vsrc:$XB, u1imm:$S1, u1imm:$S2),520 "xxmulmulloadd $XT, $XA, $XB, $S1, $S2", []>;521 def XXSSUMUDM522 : XX3Form_XTAB6_P<25, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),523 "xxssumudm $XT, $XA, $XB, $P", []>;524 def XXSSUMUDMC525 : XX3Form_XTAB6_P<57, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),526 "xxssumudmc $XT, $XA, $XB, $P", []>;527 def XSADDADDUQM528 : XX3Form_XTAB6<59, 96, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),529 "xsaddadduqm $XT, $XA, $XB", []>;530 def XSADDADDSUQM531 : XX3Form_XTAB6<59, 104, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),532 "xsaddaddsuqm $XT, $XA, $XB", []>;533 def XSADDSUBUQM534 : XX3Form_XTAB6<59, 112, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),535 "xsaddsubuqm $XT, $XA, $XB", []>;536 def XSADDSUBSUQM537 : XX3Form_XTAB6<59, 224, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),538 "xsaddsubsuqm $XT, $XA, $XB", []>;539 def XSMERGE2T1UQM540 : XX3Form_XTAB6<59, 232, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),541 "xsmerge2t1uqm $XT, $XA, $XB", []>;542 def XSMERGE2T2UQM543 : XX3Form_XTAB6<59, 240, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),544 "xsmerge2t2uqm $XT, $XA, $XB", []>;545 def XSMERGE2T3UQM546 : XX3Form_XTAB6<59, 89, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),547 "xsmerge2t3uqm $XT, $XA, $XB", []>;548 def XSMERGE3T1UQM549 : XX3Form_XTAB6<59, 121, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),550 "xsmerge3t1uqm $XT, $XA, $XB", []>;551 def XSREBASE2T1UQM552 : XX3Form_XTAB6<59, 145, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),553 "xsrebase2t1uqm $XT, $XA, $XB", []>;554 def XSREBASE2T2UQM555 : XX3Form_XTAB6<59, 177, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),556 "xsrebase2t2uqm $XT, $XA, $XB", []>;557 def XSREBASE2T3UQM558 : XX3Form_XTAB6<59, 209, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),559 "xsrebase2t3uqm $XT, $XA, $XB", []>;560 def XSREBASE2T4UQM561 : XX3Form_XTAB6<59, 217, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),562 "xsrebase2t4uqm $XT, $XA, $XB", []>;563 def XSREBASE3T1UQM564 : XX3Form_XTAB6<59, 241, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),565 "xsrebase3t1uqm $XT, $XA, $XB", []>;566 def XSREBASE3T2UQM567 : XX3Form_XTAB6<59, 249, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),568 "xsrebase3t2uqm $XT, $XA, $XB", []>;569 def XSREBASE3T3UQM570 : XX3Form_XTAB6<59, 195, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),571 "xsrebase3t3uqm $XT, $XA, $XB", []>;572}573 574let Predicates = [HasVSX, PrefixInstrs, IsISAFuture] in {575 def XXSSUMUDMCEXT576 : 8RR_XX4Form_XTABC6_P<577 34, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u1imm:$P),578 "xxssumudmcext $XT, $XA, $XB, $XC, $P", IIC_VecGeneral, []>;579}580 581//---------------------------- Anonymous Patterns ----------------------------//582// Predicate combinations available:583 584// Load/Store VSX Vector with Right Length (Left-justified).585def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;586def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;587def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,588 $RB)>;589def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,590 $RB)>;591 592// Load/Store VSX Vector pair with Right Length (Left-justified).593def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;594def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;595def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,596 $RA, $RB)>;597def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,598 $RA, $RB)>;599let Predicates = [HasVSX, IsISAFuture] in {600 def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), (v4i32 (XVRLW v4i32:$vA,601 v4i32:$vB))>;602}603 604//---------------------------- Instruction aliases ---------------------------//605// Predicate combinations available:606// [HasVSX, IsISAFuture]607 608let Predicates = [HasVSX, IsISAFuture] in {609 def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp",610 (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;611 def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp",612 (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;613 def : InstAlias<"xxaes256encp $XTp, $XAp, $XBp",614 (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;615 def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp",616 (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;617 def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp",618 (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;619 def : InstAlias<"xxaes256decp $XTp, $XAp, $XBp",620 (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;621 def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,622 vsrprc:$XBp, 0)>;623 def : InstAlias<"xxaes192genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,624 vsrprc:$XBp, 1)>;625 def : InstAlias<"xxaes256genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,626 vsrprc:$XBp, 2)>;627 def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,628 vsrc:$XB, 0)>;629 def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,630 vsrc:$XB, 1)>;631}632