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1//===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Hardware Transactional Memory extension to the10// PowerPC instruction set.11//12//===----------------------------------------------------------------------===//13 14def HTM_get_imm : SDNodeXForm<imm, [{15 return getI32Imm (N->getZExtValue(), SDLoc(N));16}]>;17 18let hasSideEffects = 1 in {19def TCHECK_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>;20def TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>;21}22 23 24let Predicates = [HasHTM] in {25 26let Defs = [CR0] in {27def TBEGIN : XForm_htm0 <31, 654,28 (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>;29 30def TEND : XForm_htm1 <31, 686,31 (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>;32 33def TABORT : XForm_base_r3xo <31, 910,34 (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,35 []>, isRecordForm {36 let RST = 0;37 let RB = 0;38}39 40def TABORTWC : XForm_base_r3xo <31, 782,41 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),42 "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,43 isRecordForm;44 45def TABORTWCI : XForm_base_r3xo <31, 846,46 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),47 "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,48 isRecordForm;49 50def TABORTDC : XForm_base_r3xo <31, 814,51 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),52 "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,53 isRecordForm;54 55def TABORTDCI : XForm_base_r3xo <31, 878,56 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),57 "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,58 isRecordForm;59 60def TSR : XForm_htm2 <31, 750,61 (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>,62 isRecordForm;63 64def TRECLAIM : XForm_base_r3xo <31, 942,65 (outs), (ins gprc:$RA), "treclaim. $RA",66 IIC_SprMTSPR, []>,67 isRecordForm {68 let RST = 0;69 let RB = 0;70}71 72def TRECHKPT : XForm_base_r3xo <31, 1006,73 (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,74 isRecordForm {75 let RST = 0;76 let RA = 0;77 let RB = 0;78}79 80}81 82def TCHECK : XForm_htm3 <31, 718,83 (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>;84// Builtins85 86// All HTM instructions, with the exception of tcheck, set CR0 with the87// value of the MSR Transaction State (TS) bits that exist before the88// instruction is executed. For tbegin., the EQ bit in CR0 can be used89// to determine whether the transaction was successfully started (0) or90// failed (1). We use an XORI pattern to 'flip' the bit to match the91// tbegin builtin API which defines a return value of 1 as success.92 93def : Pat<(int_ppc_tbegin i32:$R),94 (XORI (TBEGIN_RET(HTM_get_imm imm:$R)), 1)>;95 96def : Pat<(int_ppc_tend i32:$R),97 (TEND (HTM_get_imm imm:$R))>;98 99def : Pat<(int_ppc_tabort i32:$R),100 (TABORT $R)>;101 102def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),103 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;104 105def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),106 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;107 108def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),109 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;110 111def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),112 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;113 114def : Pat<(int_ppc_tcheck),115 (TCHECK_RET)>;116 117def : Pat<(int_ppc_treclaim i32:$RA),118 (TRECLAIM $RA)>;119 120def : Pat<(int_ppc_trechkpt),121 (TRECHKPT)>;122 123def : Pat<(int_ppc_tsr i32:$L),124 (TSR (HTM_get_imm imm:$L))>;125 126def : Pat<(int_ppc_get_texasr),127 (MFSPR8 130)>;128 129def : Pat<(int_ppc_get_texasru),130 (MFSPR8 131)>;131 132def : Pat<(int_ppc_get_tfhar),133 (MFSPR8 128)>;134 135def : Pat<(int_ppc_get_tfiar),136 (MFSPR8 129)>;137 138 139def : Pat<(int_ppc_set_texasr i64:$V),140 (MTSPR8 130, $V)>;141 142def : Pat<(int_ppc_set_texasru i64:$V),143 (MTSPR8 131, $V)>;144 145def : Pat<(int_ppc_set_tfhar i64:$V),146 (MTSPR8 128, $V)>;147 148def : Pat<(int_ppc_set_tfiar i64:$V),149 (MTSPR8 129, $V)>;150 151 152// Extended mnemonics153def : Pat<(int_ppc_tendall),154 (TEND 1)>;155 156def : Pat<(int_ppc_tresume),157 (TSR 1)>;158 159def : Pat<(int_ppc_tsuspend),160 (TSR 0)>;161 162def : Pat<(i64 (int_ppc_ttest)),163 (i64 (INSERT_SUBREG164 (i64 (IMPLICIT_DEF)), (TABORTWCI 0, (LI 0), 0), sub_32))>;165 166} // [HasHTM]167 168def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;169def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;170def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;171def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;172