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1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the subset of the 32-bit PowerPC instruction set, as used10// by the PowerPC instruction selector.11//12//===----------------------------------------------------------------------===//13 14include "PPCInstrFormats.td"15 16//===----------------------------------------------------------------------===//17// PowerPC specific type constraints.18//19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx20 SDTCisVT<0, f64>, SDTCisPtrTy<1>21]>;22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x23 SDTCisVT<0, f64>, SDTCisPtrTy<1>24]>;25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>27]>;28def SDT_PPCstxsix : SDTypeProfile<0, 3, [29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>30]>;31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [32 SDTCisFP<0>, SDTCisFP<1>33 ]>;34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>36]>;37def SDT_PPCVexts : SDTypeProfile<1, 2, [38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>39]>;40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,42 SDTCisVT<1, i32> ]>;43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,44 SDTCisVT<1, i32> ]>;45def SDT_PPCvperm : SDTypeProfile<1, 3, [46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>47]>;48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,50 SDTCisVec<1>, SDTCisInt<2>51]>;52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>,54 SDTCisInt<1>55]>;56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>59]>;60 61def SDT_PPCVecShiftQuad : SDTypeProfile<1, 2, [62 SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>63]>;64 65def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>67]>;68 69def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>,70 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>71]>;72 73def SDT_PPCvcmp : SDTypeProfile<1, 3, [74 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>75]>;76 77def SDT_PPCcondbr : SDTypeProfile<0, 3, [78 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>79]>;80 81def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [82 SDTCisVT<0, i32>]>;83 84def SDT_PPClbrx : SDTypeProfile<1, 2, [85 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>86]>;87def SDT_PPCstbrx : SDTypeProfile<0, 3, [88 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>89]>;90def SDT_StoreCond : SDTypeProfile<0, 3, [91 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2>92]>;93 94def SDT_PPCTC_ret : SDTypeProfile<0, 2, [95 SDTCisPtrTy<0>, SDTCisVT<1, i32>96]>;97 98def tocentry32 : Operand<iPTR> {99 let MIOperandInfo = (ops i32imm:$imm);100}101 102def SDT_PPCqvfperm : SDTypeProfile<1, 3, [103 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>104]>;105def SDT_PPCqvgpci : SDTypeProfile<1, 1, [106 SDTCisVec<0>, SDTCisInt<1>107]>;108def SDT_PPCqvaligni : SDTypeProfile<1, 3, [109 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>110]>;111def SDT_PPCqvesplati : SDTypeProfile<1, 2, [112 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>113]>;114 115def SDT_PPCqbflt : SDTypeProfile<1, 1, [116 SDTCisVec<0>, SDTCisVec<1>117]>;118 119def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [120 SDTCisVec<0>, SDTCisPtrTy<1>121]>;122 123def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli124 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2>125]>;126 127def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>129]>;130 131// RES, CARRY = op LHS, RHS132def SDT_PPCBinaryArithWithFlagsOut : SDTypeProfile<2, 2, [133 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,134 SDTCisInt<0>,135 SDTCisVT<1, i32>,136]>;137 138// RES, CARRY = op LHS, RHS, CARRY139def SDT_PPCBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [140 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,141 SDTCisInt<0>,142 SDTCisSameAs<1, 4>,143 SDTCisVT<1, i32>,144]>;145 146//===----------------------------------------------------------------------===//147// PowerPC specific DAG Nodes.148//149 150def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;151def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;152 153// Square root instruction.154def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>;155 156// Test instruction for software square root.157def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>;158 159// FCFID - The FCFID instruction, taking an f64 operand and producing160// and f64 value containing the FP representation of the integer that161// was temporarily in the f64 operand.162def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;163 164// Newer FCFID[US] integer-to-floating-point conversion instructions for165// unsigned integers and single-precision outputs.166def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;167def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;168def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;169 170// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64171// operand, producing an f64 value containing the integer representation172// of that FP value.173def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;174def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;175 176// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for177// unsigned integers with round toward zero.178def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;179def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;180 181// VSRQ - The ISA 3.1 (P10) Vector Shift right quadword instruction182def PPCvsrq: SDNode<"PPCISD::VSRQ", SDT_PPCVecShiftQuad, []>;183 184// Constrained integer-to-floating-point conversion instructions.185let IsStrictFP = true in {186 def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID",187 SDTFPUnaryOp, [SDNPHasChain]>;188 def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU",189 SDTFPUnaryOp, [SDNPHasChain]>;190 def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS",191 SDTFPRoundOp, [SDNPHasChain]>;192 def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS",193 SDTFPRoundOp, [SDNPHasChain]>;194}195 196def PPCany_fcfid : PatFrags<(ops node:$op),197 [(PPCfcfid node:$op),198 (PPCstrict_fcfid node:$op)]>;199def PPCany_fcfidu : PatFrags<(ops node:$op),200 [(PPCfcfidu node:$op),201 (PPCstrict_fcfidu node:$op)]>;202def PPCany_fcfids : PatFrags<(ops node:$op),203 [(PPCfcfids node:$op),204 (PPCstrict_fcfids node:$op)]>;205def PPCany_fcfidus : PatFrags<(ops node:$op),206 [(PPCfcfidus node:$op),207 (PPCstrict_fcfidus node:$op)]>;208 209// Store scalar integers from VSR.210def PPCstore_scal_int_from_vsr:211 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr,212 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;213 214// STFIWX - The STFIWX instruction. The first operand is an input token215// chain, then an f64 value to store, then an address to store it to.216def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,217 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;218 219// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point220// load which sign-extends from a 32-bit integer value into the221// destination 64-bit register.222def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,223 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;224 225// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point226// load which zero-extends from a 32-bit integer value into the227// destination 64-bit register.228def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,229 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;230 231// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an232// integer smaller than 64 bits into a VSR. The integer is zero-extended.233// This can be used for converting loaded integers to floating point.234def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,235 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;236 237// STXSIX - The STXSI[bh]X instruction. The first operand is an input238// chain, then an f64 value to store, then an address to store it to,239// followed by a byte-width for the store.240def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,241 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;242 243// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in244// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.245def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;246 247// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.248def PPCmffs : SDNode<"PPCISD::MFFS",249 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,250 [SDNPHasChain]>;251 252// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding253// towards zero. Used only as part of the long double-to-int254// conversion sequence.255def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;256 257// Constrained floating point add in round-to-zero mode.258let IsStrictFP = true in259def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp,260 [SDNPHasChain]>;261 262def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs),263 [(PPCfaddrtz node:$lhs, node:$rhs),264 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>;265 266// FSEL - Traditional three-operand fsel node.267def PPCfsel : SDNode<"PPCISD::FSEL",268 // Type constraint for fsel.269 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,270 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;271 272// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.273def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>;274def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>;275 276// Hi/Lo - These represent the high and low 16-bit parts of a global277// address respectively. These nodes have two operands, the first of278// which must be a TargetGlobalAddress, and the second of which must be a279// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',280// though these are usually folded into other nodes.281def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;282def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;283 284// GPRC = TOC_ENTRY GA, TOC285// Loads the entry for GA from the TOC, where the TOC base is given by286// the last operand.287def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,288 [SDNPMayLoad, SDNPMemOperand]>;289 290// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS291// for non-position independent code on PPC32.292def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;293 294// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec295// TLS model, produces an ADDIS8 instruction that adds the GOT296// base to sym\@got\@tprel\@ha.297def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;298 299// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec300// TLS model, produces a LD instruction with base register G8RReg301// and offset sym\@got\@tprel\@l. This completes the addition that302// finds the offset of "sym" relative to the thread pointer.303def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,304 [SDNPMayLoad]>;305 306// G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec307// and local-exec TLS models, produces an ADD instruction that adds308// the contents of G8RReg to the thread pointer. Symbol contains a309// relocation sym\@tls which is to be replaced by the thread pointer310// and identifies to the linker that the instruction is part of a311// TLS sequence.312def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;313 314// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS315// model, produces an ADDIS8 instruction that adds the GOT base316// register to sym\@got\@tlsgd\@ha.317def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;318 319// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS320// model, produces an ADDI8 instruction that adds G8RReg to321// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by322// ADDIS_TLSGD_L_ADDR until after register assignment.323def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;324 325// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS326// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by327// ADDIS_TLSGD_L_ADDR until after register assignment.328def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;329 330// %x3 = GET_TLS_MOD_AIX _$TLSML - For the AIX local-dynamic TLS model,331// produces a call to .__tls_get_mod(_$TLSML\@ml).332def PPCgetTlsMod : SDNode<"PPCISD::GET_TLS_MOD_AIX", SDTIntUnaryOp>;333 334// %x3 = GET_TPOINTER - Used for the local- and initial-exec TLS model on335// 32-bit AIX, produces a call to .__get_tpointer to retrieve the thread336// pointer. At the end of the call, the thread pointer is found in R3.337def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>;338 339// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that340// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following341// register assignment.342def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",343 SDTypeProfile<1, 3, [344 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,345 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;346 347// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY348// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY349// Op that combines two register copies of TOC entries350// (region handle into R3 and variable offset into R4) followed by a351// GET_TLS_ADDR node which will be expanded to a call to .__tls_get_addr.352// This node is used in 64-bit mode as well (in which case the result is353// G8RC and inputs are X3/X4).354def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>;355 356// [GP|G8]RC = TLSLD_AIX, TOC_ENTRY(module handle)357// Op that requires a single input of the module handle TOC entry in R3,358// and generates a GET_TLS_MOD_AIX node which will be expanded into a call359// to .__tls_get_mod. This node is used in both 32-bit and 64-bit modes.360// The only difference is the register class.361def PPCTlsldAIX : SDNode<"PPCISD::TLSLD_AIX", SDTIntUnaryOp>;362 363// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS364// model, produces an ADDIS8 instruction that adds the GOT base365// register to sym\@got\@tlsld\@ha.366def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;367 368// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS369// model, produces an ADDI8 instruction that adds G8RReg to370// sym\@got\@tlsld\@l and stores the result in X3. Hidden by371// ADDIS_TLSLD_L_ADDR until after register assignment.372def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;373 374// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS375// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by376// ADDIS_TLSLD_L_ADDR until after register assignment.377def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;378 379// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that380// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion381// following register assignment.382def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",383 SDTypeProfile<1, 3, [384 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,385 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;386 387// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS388// model, produces an ADDIS8 instruction that adds X3 to389// sym\@dtprel\@ha.390def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;391 392// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS393// model, produces an ADDI8 instruction that adds G8RReg to394// sym\@got\@dtprel\@l.395def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;396 397// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS398// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.399def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>;400 401// VPERM - The PPC VPERM Instruction.402def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;403 404// XXSPLT - The PPC VSX splat instructions405def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;406 407// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for408// converting immediate single precision numbers to double precision409// vector or scalar.410def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>;411 412// VECINSERT - The PPC vector insert instruction413def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>;414 415// XXPERMDI - The PPC XXPERMDI instruction416def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;417 418// VECSHL - The PPC vector shift left instruction419def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;420 421// The CMPB instruction (takes two operands of i32 or i64).422def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;423 424// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift425// amounts. These nodes are generated by the multi-precision shift code.426//427// For scalar types, only the last `n + 1` bits of the shift amounts428// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.429// for exact behaviors.430//431// For vector types, only the last n bits are used. See vsld.432def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;433def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;434def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;435 436// FNMSUB - Negated multiply-subtract instruction.437def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>;438 439// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign440// word and shift left immediate.441def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;442 443// Constrained conversion from floating point to int444let IsStrictFP = true in {445 def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ",446 SDTFPUnaryOp, [SDNPHasChain]>;447 def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ",448 SDTFPUnaryOp, [SDNPHasChain]>;449 def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ",450 SDTFPUnaryOp, [SDNPHasChain]>;451 def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ",452 SDTFPUnaryOp, [SDNPHasChain]>;453}454 455def PPCany_fctidz : PatFrags<(ops node:$op),456 [(PPCstrict_fctidz node:$op),457 (PPCfctidz node:$op)]>;458def PPCany_fctiwz : PatFrags<(ops node:$op),459 [(PPCstrict_fctiwz node:$op),460 (PPCfctiwz node:$op)]>;461def PPCany_fctiduz : PatFrags<(ops node:$op),462 [(PPCstrict_fctiduz node:$op),463 (PPCfctiduz node:$op)]>;464def PPCany_fctiwuz : PatFrags<(ops node:$op),465 [(PPCstrict_fctiwuz node:$op),466 (PPCfctiwuz node:$op)]>;467 468// Direct move of 2 consecutive GPR to a VSX register.469def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",470 SDTypeProfile<1, 2,471 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>,472 SDTCisSameAs<1,2>]>,473 []>;474 475// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and476// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is477// unsupported for this target.478// Merge 2 GPRs to a single SPE register.479def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64",480 SDTypeProfile<1, 2,481 [SDTCisVT<0, f64>, SDTCisVT<1,i32>,482 SDTCisVT<1,i32>]>,483 []>;484 485// Extract SPE register component, second argument is high or low.486def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE",487 SDTypeProfile<1, 2,488 [SDTCisVT<0, i32>, SDTCisVT<1, f64>,489 SDTCisPtrTy<2>]>,490 []>;491 492// These are target-independent nodes, but have target-specific formats.493def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,494 [SDNPHasChain, SDNPOutGlue]>;495def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,496 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;497 498def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;499 500// CALL - A direct function call.501// CALL_NOP is a call with the special NOP which follows 64-bit502// CALL_NOTOC the caller does not use the TOC.503// SVR4 calls and 32-bit/64-bit AIX calls.504def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,505 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,506 SDNPVariadic]>;507def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,508 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,509 SDNPVariadic]>;510def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall,511 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,512 SDNPVariadic]>;513 514// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a515// MTCTR instruction.516def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,517 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;518 519// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a520// BCTRL instruction.521def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,522 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,523 SDNPVariadic]>;524 525// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl526// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX527// and 64-bit AIX.528def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",529 SDTypeProfile<0, 1, []>,530 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,531 SDNPVariadic]>;532 533// The variants that implicitly define rounding mode for calls with534// strictfp semantics.535def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall,536 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,537 SDNPVariadic]>;538def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall,539 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,540 SDNPVariadic]>;541def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall,542 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,543 SDNPVariadic]>;544def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone,545 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,546 SDNPVariadic]>;547def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM",548 SDTypeProfile<0, 1, []>,549 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,550 SDNPVariadic]>;551 552// Return with a glue operand, matched by 'blr'553def PPCretglue : SDNode<"PPCISD::RET_GLUE", SDTNone,554 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;555 556// TC_RETURN - A tail call return.557// operand #0 chain558// operand #1 callee (register or absolute)559// operand #2 stack adjustment560// operand #3 optional in flag561def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,562 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;563 564// EH_SJLJ_SETJMP - SjLj exception handling setjmp.565def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",566 SDTypeProfile<1, 1, [SDTCisInt<0>,567 SDTCisPtrTy<1>]>,568 [SDNPHasChain, SDNPSideEffect]>;569 570// EH_SJLJ_LONGJMP - SjLj exception handling longjmp.571def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",572 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,573 [SDNPHasChain, SDNPSideEffect]>;574 575// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*576// instructions. For lack of better number, we use the opcode number577// encoding for the OPC field to identify the compare. For example, 838578// is VCMPGTSH.579def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;580 581// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the582// altivec VCMP*_rec instructions. For lack of better number, we use the583// opcode number encoding for the OPC field to identify the compare. For584// example, 838 is VCMPGTSH.585def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>;586 587// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This588// corresponds to the COND_BRANCH pseudo instruction. CRRC is the589// condition register to branch on, OPC is the branch opcode to use (e.g.590// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is591// an optional input flag argument.592def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,593 [SDNPHasChain, SDNPOptInGlue]>;594 595// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes596// except they ensure that the compare input is zero-extended for597// sub-word versions because the atomic loads zero-extend.598def PPCatomicCmpSwap_8 :599 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3,600 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;601def PPCatomicCmpSwap_16 :602 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3,603 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;604 605// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a606// byte-swapping load instruction. It loads "Type" bits, byte swaps it,607// then puts it in the bottom bits of the GPRC. TYPE can be either i16608// or i32.609def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,610 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;611 612// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a613// byte-swapping store instruction. It byte-swaps the low "Type" bits of614// the GPRC input, then stores it through Ptr. Type can be either i16 or615// i32.616def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,617 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;618 619// CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr620// The store conditional instruction ST[BHWD]ARX that produces a glue621// result to attach it to a conditional branch.622def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond,623 [SDNPHasChain, SDNPMayStore,624 SDNPMemOperand, SDNPOutGlue]>;625 626// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls627def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,628 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;629def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,630 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;631 632// Instructions to support dynamic alloca.633def SDTDynOp : SDTypeProfile<1, 2, []>;634def SDTDynAreaOp : SDTypeProfile<1, 1, []>;635 636// The following two target-specific nodes are used for calls through637// function pointers in the 64-bit SVR4 ABI.638 639// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)640// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to641// compute an allocation on the stack.642def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;643 644// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to645// compute an offset from native SP to the address of the most recent646// dynamic alloca.647def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;648 649// To avoid stack clash, allocation is performed by block and each block is650// probed.651def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>;652 653// PC Relative Specific Nodes654 655// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done656// either through an add like PADDI or through a PC Relative load like657// PLD.658def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>;659 660// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for661// TLS global address when using dynamic access models. This can be done662// through an add like PADDI.663def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR",664 SDTIntUnaryOp, []>;665 666// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address667// when using local exec access models, and when prefixed instructions are668// available. This is used with ADD_TLS to produce an add like PADDI.669def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR",670 SDTIntUnaryOp, []>;671 672// These nodes represent PPC arithmetic operations with carry.673def PPCaddc : SDNode<"PPCISD::ADDC", SDT_PPCBinaryArithWithFlagsOut,674 [SDNPCommutative]>;675def PPCadde : SDNode<"PPCISD::ADDE", SDT_PPCBinaryArithWithFlagsInOut,676 []>;677def PPCsubc : SDNode<"PPCISD::SUBC", SDT_PPCBinaryArithWithFlagsOut,678 []>;679def PPCsube : SDNode<"PPCISD::SUBE", SDT_PPCBinaryArithWithFlagsInOut,680 []>;681 682//===----------------------------------------------------------------------===//683// PowerPC specific transformation functions and pattern fragments.684//685 686// A floating point immediate that is not a positive zero and can be converted687// to a single precision floating point non-denormal immediate without loss of688// information.689def nzFPImmAsi32 : PatLeaf<(fpimm), [{690 APFloat APFloatOfN = N->getValueAPF();691 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0);692}]>;693 694// A floating point immediate that is exactly an integer (for example 3.0, -5.0)695// and can be represented in 5 bits (range of [-16, 15]).696def nzFPImmExactInti5 : PatLeaf<(fpimm), [{697 APFloat FloatValue = N->getValueAPF();698 bool IsExact;699 APSInt IntResult(16, false);700 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact);701 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero();702}]>;703 704def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{705 APFloat FloatValue = N->getValueAPF();706 bool IsExact;707 APSInt IntResult(32, false);708 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact);709 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32);710}]>;711 712// Convert the floating point immediate into a 32 bit floating point immediate713// and get a i32 with the resulting bits.714def getFPAs32BitInt : SDNodeXForm<fpimm, [{715 APFloat APFloatOfN = N->getValueAPF();716 convertToNonDenormSingle(APFloatOfN);717 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(),718 SDLoc(N), MVT::i32);719}]>;720 721// Check if the value can be converted to be single precision immediate, which722// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single723// precision before exploiting with XXSPLTI32DX.724def nzFPImmAsi64 : PatLeaf<(fpimm), [{725 APFloat APFloatOfN = N->getValueAPF();726 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN);727}]>;728 729// Get the Hi bits of a 64 bit immediate.730def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{731 APFloat APFloatOfN = N->getValueAPF();732 bool Unused;733 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,734 &Unused);735 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() &736 0xFFFFFFFF00000000LL) >> 32);737 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32);738}]>;739 740// Get the Lo bits of a 64 bit immediate.741def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{742 APFloat APFloatOfN = N->getValueAPF();743 bool Unused;744 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,745 &Unused);746 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() &747 0xFFFFFFFF);748 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32);749}]>;750 751def imm34 : PatLeaf<(imm), [{752 return isInt<34>(N->getSExtValue());753}]>;754 755def getImmAs64BitInt : SDNodeXForm<imm, [{756 return getI64Imm(N->getSExtValue(), SDLoc(N));757}]>;758 759def SHL32 : SDNodeXForm<imm, [{760 // Transformation function: 31 - imm761 return getI32Imm(31 - N->getZExtValue(), SDLoc(N));762}]>;763 764def SRL32 : SDNodeXForm<imm, [{765 // Transformation function: 32 - imm766 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))767 : getI32Imm(0, SDLoc(N));768}]>;769 770def LO16 : SDNodeXForm<imm, [{771 // Transformation function: get the low 16 bits.772 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));773}]>;774 775def HI16 : SDNodeXForm<imm, [{776 // Transformation function: shift the immediate value down into the low bits.777 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));778}]>;779 780def HA16 : SDNodeXForm<imm, [{781 // Transformation function: shift the immediate value down into the low bits.782 int64_t Val = N->getZExtValue();783 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));784}]>;785def MB : SDNodeXForm<imm, [{786 // Transformation function: get the start bit of a mask787 unsigned mb = 0, me;788 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);789 return getI32Imm(mb, SDLoc(N));790}]>;791 792def ME : SDNodeXForm<imm, [{793 // Transformation function: get the end bit of a mask794 unsigned mb, me = 0;795 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);796 return getI32Imm(me, SDLoc(N));797}]>;798def maskimm32 : PatLeaf<(imm), [{799 // maskImm predicate - True if immediate is a run of ones.800 unsigned mb, me;801 if (N->getValueType(0) == MVT::i32)802 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);803 else804 return false;805}]>;806 807def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{808 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit809 // sign extended field. Used by instructions like 'addi'.810 return (int32_t)Imm == (short)Imm;811}]>;812def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{813 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit814 // sign extended field. Used by instructions like 'addi'.815 return (int64_t)Imm == (short)Imm;816}]>;817def immZExt16 : PatLeaf<(imm), [{818 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended819 // field. Used by instructions like 'ori'.820 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();821}], LO16>;822def immNonAllOneAnyExt8 : ImmLeaf<i32, [{823 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF));824}]>;825def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>;826def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;827 828// imm16Shifted* - These match immediates where the low 16-bits are zero. There829// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are830// identical in 32-bit mode, but in 64-bit mode, they return true if the831// immediate fits into a sign/zero extended 32-bit immediate (with the low bits832// clear).833def imm16ShiftedZExt : PatLeaf<(imm), [{834 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the835 // immediate are set. Used by instructions like 'xoris'.836 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;837}], HI16>;838 839def imm16ShiftedSExt : PatLeaf<(imm), [{840 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the841 // immediate are set. Used by instructions like 'addis'. Identical to842 // imm16ShiftedZExt in 32-bit mode.843 if (N->getZExtValue() & 0xFFFF) return false;844 if (N->getValueType(0) == MVT::i32)845 return true;846 // For 64-bit, make sure it is sext right.847 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();848}], HI16>;849 850def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{851 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit852 // zero extended field.853 return isUInt<32>(Imm);854}]>;855 856// This is a somewhat weaker condition than actually checking for 4-byte857// alignment. It is simply checking that the displacement can be represented858// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form859// instructions).860// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require861// restricted memrix (4-aligned) constants are alignment sensitive. If these862// offsets are hidden behind TOC entries than the values of the lower-order863// bits cannot be checked directly. As a result, we need to also incorporate864// an alignment check into the relevant patterns.865 866def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{867 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4;868}]>;869def DSFormStore : PatFrag<(ops node:$val, node:$ptr),870 (store node:$val, node:$ptr), [{871 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4;872}]>;873def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{874 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4;875}]>;876def DSFormPreStore : PatFrag<877 (ops node:$val, node:$base, node:$offset),878 (pre_store node:$val, node:$base, node:$offset), [{879 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4;880}]>;881 882def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{883 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4);884}]>;885def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr),886 (store node:$val, node:$ptr), [{887 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4);888}]>;889def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{890 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4);891}]>;892 893// This is a somewhat weaker condition than actually checking for 16-byte894// alignment. It is simply checking that the displacement can be represented895// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form896// instructions).897def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{898 return isOffsetMultipleOf(N, 16);899}]>;900def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),901 (store node:$val, node:$ptr), [{902 return isOffsetMultipleOf(N, 16);903}]>;904def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{905 return !isOffsetMultipleOf(N, 16);906}]>;907def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),908 (store node:$val, node:$ptr), [{909 return !isOffsetMultipleOf(N, 16);910}]>;911 912// PatFrag for binary operation whose operands are both non-constant913class BinOpWithoutSImm16Operand<SDNode opcode> :914 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{915 int16_t Imm;916 return !isIntS16Immediate(N->getOperand(0), Imm)917 && !isIntS16Immediate(N->getOperand(1), Imm);918}]>;919 920def add_without_simm16 : BinOpWithoutSImm16Operand<add>;921def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>;922 923//===----------------------------------------------------------------------===//924// PowerPC Flag Definitions.925 926class isPPC64 { bit PPC64 = 1; }927class isRecordForm { bit RC = 1; }928 929class RegConstraint<string C> {930 string Constraints = C;931}932 933 934// Define PowerPC specific addressing mode.935 936// d-form937def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb"938// ds-form939def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"940// dq-form941def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv"942// 8LS:d-form943def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp"944 945// Below forms are all x-form addressing mode, use three different ones so we946// can make a accurate check for x-form instructions in ISEL.947// x-form addressing mode whose associated displacement form is D.948def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx"949// x-form addressing mode whose associated displacement form is DS.950def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx"951// x-form addressing mode whose associated displacement form is DQ.952def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx"953 954def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;955 956// The address in a single register. This is used with the SjLj957// pseudo-instructions.958def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;959 960/// This is just the offset part of iaddr, used for preinc.961def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;962 963// Load and Store Instruction Selection addressing modes.964let WantsParent = true in {965 def DForm : ComplexPattern<iPTR, 2, "SelectDForm">;966 def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm">;967 def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm">;968 def XForm : ComplexPattern<iPTR, 2, "SelectXForm">;969 def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm">;970 def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm">;971 def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">;972}973 974//===----------------------------------------------------------------------===//975// PowerPC Multiclass Definitions.976multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,977 string asmbase, string asmstr, list<dag> pattern> {978 let BaseName = asmbase in {979 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL,980 !strconcat(asmbase, !strconcat(" ", asmstr)),981 NoItinerary, pattern>, RecFormRel;982 let Defs = [CR1] in983 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL,984 !strconcat(asmbase, !strconcat(". ", asmstr)),985 NoItinerary, []>, isRecordForm, RecFormRel;986 }987}988 989multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,990 string asmbase, string asmstr, InstrItinClass itin,991 list<dag> pattern> {992 let BaseName = asmbase in {993 def NAME : XForm_6<opcode, xo, OOL, IOL,994 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,995 pattern>, RecFormRel;996 let Defs = [CR0] in997 def _rec : XForm_6<opcode, xo, OOL, IOL,998 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,999 []>, isRecordForm, RecFormRel;1000 }1001}1002 1003multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1004 string asmbase, string asmstr, InstrItinClass itin,1005 list<dag> pattern> {1006 let BaseName = asmbase in {1007 let Defs = [CARRY] in1008 def NAME : XForm_6<opcode, xo, OOL, IOL,1009 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1010 pattern>, RecFormRel;1011 let Defs = [CARRY, CR0] in1012 def _rec : XForm_6<opcode, xo, OOL, IOL,1013 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1014 []>, isRecordForm, RecFormRel;1015 }1016}1017 1018multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1019 string asmbase, string asmstr, InstrItinClass itin,1020 list<dag> pattern> {1021 let BaseName = asmbase in {1022 let Defs = [CARRY] in1023 def NAME : XForm_10<opcode, xo, OOL, IOL,1024 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1025 pattern>, RecFormRel;1026 let Defs = [CARRY, CR0] in1027 def _rec : XForm_10<opcode, xo, OOL, IOL,1028 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1029 []>, isRecordForm, RecFormRel;1030 }1031}1032 1033multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1034 string asmbase, string asmstr, InstrItinClass itin,1035 list<dag> pattern> {1036 let BaseName = asmbase in {1037 def NAME : XForm_11<opcode, xo, OOL, IOL,1038 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1039 pattern>, RecFormRel;1040 let Defs = [CR0] in1041 def _rec : XForm_11<opcode, xo, OOL, IOL,1042 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1043 []>, isRecordForm, RecFormRel;1044 }1045}1046 1047multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,1048 string asmbase, string asmstr, InstrItinClass itin,1049 list<dag> pattern> {1050 let BaseName = asmbase in {1051 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,1052 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1053 pattern>, RecFormRel;1054 let Defs = [CR0] in1055 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL,1056 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1057 []>, isRecordForm, RecFormRel;1058 }1059}1060 1061// Multiclass for instructions which have a record overflow form as well1062// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.)1063multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,1064 string asmbase, string asmstr, InstrItinClass itin,1065 list<dag> pattern> {1066 let BaseName = asmbase in {1067 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL,1068 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1069 pattern>, RecFormRel;1070 let Defs = [CR0] in1071 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL,1072 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1073 []>, isRecordForm, RecFormRel;1074 }1075 let BaseName = !strconcat(asmbase, "O") in {1076 let Defs = [XER] in1077 def O : XOForm_1<opcode, xo, 1, OOL, IOL,1078 !strconcat(asmbase, !strconcat("o ", asmstr)), itin,1079 []>, RecFormRel;1080 let Defs = [XER, CR0] in1081 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL,1082 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,1083 []>, isRecordForm, RecFormRel;1084 }1085}1086 1087// Multiclass for instructions for which the non record form is not cracked1088// and the record form is cracked (i.e. divw, mullw, etc.)1089multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,1090 string asmbase, string asmstr, InstrItinClass itin,1091 list<dag> pattern> {1092 let BaseName = asmbase in {1093 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,1094 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1095 pattern>, RecFormRel;1096 let Defs = [CR0] in1097 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL,1098 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1099 []>, isRecordForm, RecFormRel, PPC970_DGroup_First,1100 PPC970_DGroup_Cracked;1101 }1102 let BaseName = !strconcat(asmbase, "O") in {1103 let Defs = [XER] in1104 def O : XOForm_1<opcode, xo, 1, OOL, IOL,1105 !strconcat(asmbase, !strconcat("o ", asmstr)), itin,1106 []>, RecFormRel;1107 let Defs = [XER, CR0] in1108 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL,1109 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,1110 []>, isRecordForm, RecFormRel;1111 }1112}1113 1114multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,1115 string asmbase, string asmstr, InstrItinClass itin,1116 list<dag> pattern> {1117 let BaseName = asmbase in {1118 let Defs = [CARRY] in1119 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,1120 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1121 pattern>, RecFormRel;1122 let Defs = [CARRY, CR0] in1123 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL,1124 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1125 []>, isRecordForm, RecFormRel;1126 }1127 let BaseName = !strconcat(asmbase, "O") in {1128 let Defs = [CARRY, XER] in1129 def O : XOForm_1<opcode, xo, 1, OOL, IOL,1130 !strconcat(asmbase, !strconcat("o ", asmstr)), itin,1131 []>, RecFormRel;1132 let Defs = [CARRY, XER, CR0] in1133 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL,1134 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,1135 []>, isRecordForm, RecFormRel;1136 }1137}1138 1139multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,1140 string asmbase, string asmstr, InstrItinClass itin,1141 list<dag> pattern> {1142 let BaseName = asmbase in {1143 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,1144 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1145 pattern>, RecFormRel;1146 let Defs = [CR0] in1147 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL,1148 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1149 []>, isRecordForm, RecFormRel;1150 }1151 let BaseName = !strconcat(asmbase, "O") in {1152 let Defs = [XER] in1153 def O : XOForm_3<opcode, xo, 1, OOL, IOL,1154 !strconcat(asmbase, !strconcat("o ", asmstr)), itin,1155 []>, RecFormRel;1156 let Defs = [XER, CR0] in1157 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL,1158 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,1159 []>, isRecordForm, RecFormRel;1160 }1161}1162 1163multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,1164 string asmbase, string asmstr, InstrItinClass itin,1165 list<dag> pattern> {1166 let BaseName = asmbase in {1167 let Defs = [CARRY] in1168 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,1169 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1170 pattern>, RecFormRel;1171 let Defs = [CARRY, CR0] in1172 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL,1173 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1174 []>, isRecordForm, RecFormRel;1175 }1176 let BaseName = !strconcat(asmbase, "O") in {1177 let Defs = [CARRY, XER] in1178 def O : XOForm_3<opcode, xo, 1, OOL, IOL,1179 !strconcat(asmbase, !strconcat("o ", asmstr)), itin,1180 []>, RecFormRel;1181 let Defs = [CARRY, XER, CR0] in1182 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL,1183 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,1184 []>, isRecordForm, RecFormRel;1185 }1186}1187 1188multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL,1189 string asmbase, string asmstr, InstrItinClass itin,1190 list<dag> pattern> {1191 let BaseName = asmbase in {1192 def NAME : MForm_1<opcode, OOL, IOL,1193 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1194 pattern>, RecFormRel;1195 let Defs = [CR0] in1196 def _rec : MForm_1<opcode, OOL, IOL,1197 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1198 []>, isRecordForm, RecFormRel;1199 }1200}1201 1202multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,1203 string asmbase, string asmstr, InstrItinClass itin,1204 list<dag> pattern> {1205 let BaseName = asmbase in {1206 def NAME : MForm_2<opcode, OOL, IOL,1207 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1208 pattern>, RecFormRel;1209 let Defs = [CR0] in1210 def _rec : MForm_2<opcode, OOL, IOL,1211 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1212 []>, isRecordForm, RecFormRel;1213 }1214}1215 1216multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,1217 string asmbase, string asmstr, InstrItinClass itin,1218 list<dag> pattern> {1219 let BaseName = asmbase in {1220 def NAME : MDForm_1<opcode, xo, OOL, IOL,1221 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1222 pattern>, RecFormRel;1223 let Defs = [CR0] in1224 def _rec : MDForm_1<opcode, xo, OOL, IOL,1225 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1226 []>, isRecordForm, RecFormRel;1227 }1228}1229 1230multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,1231 string asmbase, string asmstr, InstrItinClass itin,1232 list<dag> pattern> {1233 let BaseName = asmbase in {1234 def NAME : MDSForm_1<opcode, xo, OOL, IOL,1235 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1236 pattern>, RecFormRel;1237 let Defs = [CR0] in1238 def _rec : MDSForm_1<opcode, xo, OOL, IOL,1239 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1240 []>, isRecordForm, RecFormRel;1241 }1242}1243 1244multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,1245 string asmbase, string asmstr, InstrItinClass itin,1246 list<dag> pattern> {1247 let BaseName = asmbase in {1248 let Defs = [CARRY] in1249 def NAME : XSForm_1<opcode, xo, OOL, IOL,1250 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1251 pattern>, RecFormRel;1252 let Defs = [CARRY, CR0] in1253 def _rec : XSForm_1<opcode, xo, OOL, IOL,1254 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1255 []>, isRecordForm, RecFormRel;1256 }1257}1258 1259multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,1260 string asmbase, string asmstr, InstrItinClass itin,1261 list<dag> pattern> {1262 let BaseName = asmbase in {1263 def NAME : XSForm_1<opcode, xo, OOL, IOL,1264 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1265 pattern>, RecFormRel;1266 let Defs = [CR0] in1267 def _rec : XSForm_1<opcode, xo, OOL, IOL,1268 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1269 []>, isRecordForm, RecFormRel;1270 }1271}1272 1273multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1274 string asmbase, string asmstr, InstrItinClass itin,1275 list<dag> pattern> {1276 let BaseName = asmbase in {1277 def NAME : XForm_26<opcode, xo, OOL, IOL,1278 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1279 pattern>, RecFormRel;1280 let Defs = [CR1] in1281 def _rec : XForm_26<opcode, xo, OOL, IOL,1282 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1283 []>, isRecordForm, RecFormRel;1284 }1285}1286 1287multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1288 string asmbase, string asmstr, InstrItinClass itin,1289 list<dag> pattern> {1290 let BaseName = asmbase in {1291 def NAME : XForm_28<opcode, xo, OOL, IOL,1292 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1293 pattern>, RecFormRel;1294 let Defs = [CR1] in1295 def _rec : XForm_28<opcode, xo, OOL, IOL,1296 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1297 []>, isRecordForm, RecFormRel;1298 }1299}1300 1301multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1302 string asmbase, string asmstr, list<dag> pattern> {1303 let BaseName = asmbase in {1304 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,1305 !strconcat(asmbase, !strconcat(" ", asmstr)),1306 pattern, NoItinerary>, RecFormRel;1307 let Defs = [CR1] in1308 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,1309 !strconcat(asmbase, !strconcat(". ", asmstr)),1310 [], NoItinerary>, isRecordForm, RecFormRel;1311 }1312}1313 1314multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,1315 string asmbase, string asmstr, list<dag> pattern> {1316 let BaseName = asmbase in {1317 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL,1318 !strconcat(asmbase, !strconcat(" ", asmstr)),1319 pattern, NoItinerary>, RecFormRel;1320 let Defs = [CR1] in1321 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL,1322 !strconcat(asmbase, !strconcat(". ", asmstr)), [],1323 NoItinerary>, isRecordForm, RecFormRel;1324 }1325}1326 1327multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,1328 string asmbase, string asmstr, InstrItinClass itin,1329 list<dag> pattern> {1330 let BaseName = asmbase in {1331 def NAME : AForm_1<opcode, xo, OOL, IOL,1332 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1333 pattern>, RecFormRel;1334 let Defs = [CR1] in1335 def _rec : AForm_1<opcode, xo, OOL, IOL,1336 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1337 []>, isRecordForm, RecFormRel;1338 }1339}1340 1341multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,1342 string asmbase, string asmstr, InstrItinClass itin,1343 list<dag> pattern> {1344 let BaseName = asmbase in {1345 def NAME : AForm_2<opcode, xo, OOL, IOL,1346 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1347 pattern>, RecFormRel;1348 let Defs = [CR1] in1349 def _rec : AForm_2<opcode, xo, OOL, IOL,1350 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1351 []>, isRecordForm, RecFormRel;1352 }1353}1354 1355multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,1356 string asmbase, string asmstr, InstrItinClass itin,1357 list<dag> pattern> {1358 let BaseName = asmbase in {1359 def NAME : AForm_3<opcode, xo, OOL, IOL,1360 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,1361 pattern>, RecFormRel;1362 let Defs = [CR1] in1363 def _rec : AForm_3<opcode, xo, OOL, IOL,1364 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,1365 []>, isRecordForm, RecFormRel;1366 }1367}1368 1369multiclass1370 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1371 string asmbase, string asmstr, list<dag> pattern> {1372 let BaseName = asmbase in {1373 def NAME1374 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,1375 !strconcat(asmbase, !strconcat(" ", asmstr)),1376 pattern>, RecFormRel;1377 let Defs = [CR0] in1378 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,1379 !strconcat(asmbase, !strconcat(". ", asmstr)),1380 []>, isRecordForm, RecFormRel;1381 }1382}1383 1384multiclass1385 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1386 string asmbase, string asmstr, list<dag> pattern> {1387 let BaseName = asmbase in {1388 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,1389 !strconcat(asmbase, !strconcat(" ", asmstr)),1390 pattern>, RecFormRel;1391 let Defs = [CR1] in1392 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,1393 !strconcat(asmbase, !strconcat(". ", asmstr)),1394 []>, isRecordForm, RecFormRel;1395 }1396}1397 1398multiclass1399 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1400 string asmbase, string asmstr, list<dag> pattern> {1401 let BaseName = asmbase in {1402 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,1403 !strconcat(asmbase, !strconcat(" ", asmstr)),1404 pattern>, RecFormRel;1405 let Defs = [CR1] in1406 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,1407 !strconcat(asmbase, !strconcat(". ", asmstr)),1408 []>, isRecordForm, RecFormRel;1409 }1410}1411 1412multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,1413 string asmbase, string asmstr, list<dag> pattern> {1414 let BaseName = asmbase in {1415 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,1416 !strconcat(asmbase, !strconcat(" ", asmstr)),1417 pattern, NoItinerary>, RecFormRel;1418 let Defs = [CR1] in1419 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,1420 !strconcat(asmbase, !strconcat(". ", asmstr)),1421 [], NoItinerary>, isRecordForm, RecFormRel;1422 }1423}1424 1425//===----------------------------------------------------------------------===//1426// END OF MULTICLASS DEFINITIONS1427//===----------------------------------------------------------------------===//1428 1429//===----------------------------------------------------------------------===//1430// PowerPC Instruction Definitions.1431 1432// Pseudo instructions:1433 1434let hasCtrlDep = 1 in {1435let Defs = [R1], Uses = [R1] in {1436def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),1437 "#ADJCALLSTACKDOWN $amt1 $amt2",1438 [(callseq_start timm:$amt1, timm:$amt2)]>;1439def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),1440 "#ADJCALLSTACKUP $amt1 $amt2",1441 [(callseq_end timm:$amt1, timm:$amt2)]>;1442}1443} // hasCtrlDep1444 1445let Defs = [R1], Uses = [R1] in1446def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",1447 [(set i32:$result,1448 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;1449def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",1450 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;1451// Probed alloca to support stack clash protection.1452let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in {1453def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result),1454 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32",1455 [(set i32:$result,1456 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>;1457def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs1458 gprc:$fp, gprc:$actual_negsize),1459 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>;1460def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs1461 gprc:$fp, gprc:$actual_negsize),1462 (ins gprc:$negsize, memri:$fpsi),1463 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>,1464 RegConstraint<"$actual_negsize = $negsize">;1465def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp),1466 (ins i64imm:$stacksize),1467 "#PROBED_STACKALLOC_32", []>;1468}1469 1470// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after1471// instruction selection into a branch sequence.1472let PPC970_Single = 1 in {1473 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes1474 // because either operand might become the first operand in an isel, and1475 // that operand cannot be r0.1476 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond,1477 gprc_nor0:$T, gprc_nor0:$F,1478 i32imm:$BROPC), "#SELECT_CC_I4",1479 []>;1480 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond,1481 g8rc_nox0:$T, g8rc_nox0:$F,1482 i32imm:$BROPC), "#SELECT_CC_I8",1483 []>;1484 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,1485 i32imm:$BROPC), "#SELECT_CC_F4",1486 []>;1487 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,1488 i32imm:$BROPC), "#SELECT_CC_F8",1489 []>;1490 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,1491 i32imm:$BROPC), "#SELECT_CC_F16",1492 []>;1493 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,1494 i32imm:$BROPC), "#SELECT_CC_VRRC",1495 []>;1496 1497 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition1498 // register bit directly.1499 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond,1500 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",1501 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;1502 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond,1503 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",1504 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;1505let Predicates = [HasFPU] in {1506 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond,1507 f4rc:$T, f4rc:$F), "#SELECT_F4",1508 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;1509 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond,1510 f8rc:$T, f8rc:$F), "#SELECT_F8",1511 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;1512 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,1513 vrrc:$T, vrrc:$F), "#SELECT_F16",1514 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;1515}1516 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,1517 vrrc:$T, vrrc:$F), "#SELECT_VRRC",1518 [(set v4i32:$dst,1519 (select i1:$cond, v4i32:$T, v4i32:$F))]>;1520}1521 1522// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to1523// scavenge a register for it.1524let mayStore = 1 in {1525def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F),1526 "#SPILL_CR", []>;1527def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F),1528 "#SPILL_CRBIT", []>;1529}1530 1531// RESTORE_CR - Indicate that we're restoring the CR register (previously1532// spilled), so we'll need to scavenge a register for it.1533let mayLoad = 1 in {1534def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F),1535 "#RESTORE_CR", []>;1536def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),1537 "#RESTORE_CRBIT", []>;1538}1539 1540let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {1541 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in1542 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,1543 [(PPCretglue)]>, Requires<[IsPPC32]>;1544 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {1545 let isPredicable = 1 in1546 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,1547 []>;1548 1549 let isCodeGenOnly = 1 in {1550 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),1551 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,1552 []>;1553 1554 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),1555 "bcctr 12, $BI, 0", IIC_BrB, []>;1556 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),1557 "bcctr 4, $BI, 0", IIC_BrB, []>;1558 }1559 }1560}1561 1562// Set the float rounding mode.1563let Uses = [RM], Defs = [RM] in {1564def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),1565 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;1566 1567def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in),1568 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>;1569 1570def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM),1571 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>;1572}1573 1574let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in1575def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>;1576 1577let Defs = [LR] in1578 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,1579 PPC970_Unit_BRU;1580let Defs = [LR] in1581 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,1582 PPC970_Unit_BRU;1583 1584let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,1585 hasSideEffects = 0 in {1586 let isBarrier = 1 in {1587 let isPredicable = 1 in1588 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI),1589 "b $LI", IIC_BrB,1590 [(br bb:$LI)]>;1591 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI),1592 "ba $LI", IIC_BrB, []>;1593 }1594 1595 // BCC represents an arbitrary conditional branch on a predicate.1596 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use1597 // a two-value operand where a dag node expects two operands. :(1598 let isCodeGenOnly = 1 in {1599 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD),1600 "b${cond:cc}${cond:pm} ${cond:reg}, $BD"1601 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>;1602 def BCC : BCC_class;1603 1604 // The same as BCC, except that it's not a terminator. Used for introducing1605 // control flow dependency without creating new blocks.1606 let isTerminator = 0 in def CTRL_DEP : BCC_class;1607 1608 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD),1609 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">;1610 1611 let isReturn = 1, Uses = [LR, RM] in1612 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond),1613 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;1614 }1615 1616 let isCodeGenOnly = 1 in {1617 let Pattern = [(brcond i1:$BI, bb:$BD)] in1618 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),1619 "bc 12, $BI, $BD">;1620 1621 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in1622 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),1623 "bc 4, $BI, $BD">;1624 1625 let isReturn = 1, Uses = [LR, RM] in {1626 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI),1627 "bclr 12, $BI, 0", IIC_BrB, []>;1628 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI),1629 "bclr 4, $BI, 0", IIC_BrB, []>;1630 }1631 }1632 1633 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {1634 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),1635 "bdzlr", IIC_BrB, []>;1636 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),1637 "bdnzlr", IIC_BrB, []>;1638 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),1639 "bdzlr+", IIC_BrB, []>;1640 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),1641 "bdnzlr+", IIC_BrB, []>;1642 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),1643 "bdzlr-", IIC_BrB, []>;1644 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),1645 "bdnzlr-", IIC_BrB, []>;1646 }1647 1648 let Defs = [CTR], Uses = [CTR] in {1649 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),1650 "bdz $BD">;1651 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),1652 "bdnz $BD">;1653 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD),1654 "bdza $BD">;1655 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD),1656 "bdnza $BD">;1657 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD),1658 "bdz+ $BD">;1659 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD),1660 "bdnz+ $BD">;1661 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD),1662 "bdza+ $BD">;1663 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD),1664 "bdnza+ $BD">;1665 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD),1666 "bdz- $BD">;1667 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD),1668 "bdnz- $BD">;1669 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD),1670 "bdza- $BD">;1671 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD),1672 "bdnza- $BD">;1673 }1674}1675 1676// The unconditional BCL used by the SjLj setjmp code.1677let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7,1678 hasSideEffects = 0 in {1679 let Defs = [LR], Uses = [RM] in {1680 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD),1681 "bcl 20, 31, $BD">;1682 }1683}1684 1685let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {1686 // Convenient aliases for call instructions1687 let Uses = [RM] in {1688 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI),1689 "bl $LI", IIC_BrB, []>; // See Pat patterns below.1690 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),1691 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>;1692 1693 let isCodeGenOnly = 1 in {1694 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI),1695 "bl $LI", IIC_BrB, []>;1696 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD),1697 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">;1698 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD),1699 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">;1700 1701 def BCL : BForm_4<16, 12, 0, 1, (outs),1702 (ins crbitrc:$BI, condbrtarget:$BD),1703 "bcl 12, $BI, $BD">;1704 def BCLn : BForm_4<16, 4, 0, 1, (outs),1705 (ins crbitrc:$BI, condbrtarget:$BD),1706 "bcl 4, $BI, $BD">;1707 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,1708 (outs), (ins calltarget:$LI),1709 "bl $LI\n\tnop", IIC_BrB, []>;1710 }1711 }1712 let Uses = [CTR, RM] in {1713 let isPredicable = 1 in1714 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),1715 "bctrl", IIC_BrB, [(PPCbctrl)]>,1716 Requires<[IsPPC32]>;1717 1718 let isCodeGenOnly = 1 in {1719 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),1720 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,1721 []>;1722 1723 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),1724 "bcctrl 12, $BI, 0", IIC_BrB, []>;1725 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),1726 "bcctrl 4, $BI, 0", IIC_BrB, []>;1727 }1728 }1729 let Uses = [LR, RM] in {1730 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),1731 "blrl", IIC_BrB, []>;1732 1733 let isCodeGenOnly = 1 in {1734 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond),1735 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,1736 []>;1737 1738 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI),1739 "bclrl 12, $BI, 0", IIC_BrB, []>;1740 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI),1741 "bclrl 4, $BI, 0", IIC_BrB, []>;1742 }1743 }1744 let Defs = [CTR], Uses = [CTR, RM] in {1745 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD),1746 "bdzl $BD">;1747 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD),1748 "bdnzl $BD">;1749 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD),1750 "bdzla $BD">;1751 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD),1752 "bdnzla $BD">;1753 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD),1754 "bdzl+ $BD">;1755 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD),1756 "bdnzl+ $BD">;1757 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD),1758 "bdzla+ $BD">;1759 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD),1760 "bdnzla+ $BD">;1761 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD),1762 "bdzl- $BD">;1763 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD),1764 "bdnzl- $BD">;1765 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD),1766 "bdzla- $BD">;1767 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD),1768 "bdnzla- $BD">;1769 }1770 let Defs = [CTR], Uses = [CTR, LR, RM] in {1771 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),1772 "bdzlrl", IIC_BrB, []>;1773 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),1774 "bdnzlrl", IIC_BrB, []>;1775 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),1776 "bdzlrl+", IIC_BrB, []>;1777 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),1778 "bdnzlrl+", IIC_BrB, []>;1779 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),1780 "bdzlrl-", IIC_BrB, []>;1781 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),1782 "bdnzlrl-", IIC_BrB, []>;1783 }1784}1785 1786let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {1787 // Convenient aliases for call instructions1788 let Uses = [RM] in {1789 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI),1790 "bl $LI", IIC_BrB, []>; // See Pat patterns below.1791 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),1792 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>;1793 1794 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24,1795 (outs), (ins calltarget:$LI),1796 "bl $LI\n\tnop", IIC_BrB, []>;1797 }1798 let Uses = [CTR, RM] in {1799 let isPredicable = 1 in1800 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),1801 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>,1802 Requires<[IsPPC32]>;1803 }1804}1805 1806let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in1807def TCRETURNdi :PPCEmitTimePseudo< (outs),1808 (ins calltarget:$dst, i32imm:$offset),1809 "#TC_RETURNd $dst $offset",1810 []>;1811 1812 1813let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in1814def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),1815 "#TC_RETURNa $func $offset",1816 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;1817 1818let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in1819def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),1820 "#TC_RETURNr $dst $offset",1821 []>;1822 1823let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,1824 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in {1825 def BCTRL_LWZinto_toc:1826 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),1827 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,1828 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[IsPPC32]>;1829 1830}1831 1832let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,1833 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in {1834 def BCTRL_LWZinto_toc_RM:1835 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),1836 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,1837 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[IsPPC32]>;1838 1839}1840 1841let isCodeGenOnly = 1, hasSideEffects = 0 in {1842 1843let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,1844 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in1845def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,1846 []>, Requires<[IsPPC32]>;1847 1848let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,1849 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in1850def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI),1851 "b $LI", IIC_BrB,1852 []>;1853 1854let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,1855 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in1856def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI),1857 "ba $LI", IIC_BrB,1858 []>;1859 1860}1861 1862// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp1863// is not.1864let hasSideEffects = 1 in {1865 let Defs = [CTR] in1866 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),1867 "#EH_SJLJ_SETJMP32",1868 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,1869 Requires<[IsPPC32]>;1870}1871 1872let hasSideEffects = 1, isBarrier = 1 in {1873 let isTerminator = 1 in1874 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),1875 "#EH_SJLJ_LONGJMP32",1876 [(PPCeh_sjlj_longjmp addr:$buf)]>,1877 Requires<[IsPPC32]>;1878}1879 1880// This pseudo is never removed from the function, as it serves as1881// a terminator. Size is set to 0 to prevent the builtin assembler1882// from emitting it.1883let isBranch = 1, isTerminator = 1, Size = 0 in {1884 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst),1885 "#EH_SjLj_Setup\t$dst", []>;1886}1887 1888// System call.1889let PPC970_Unit = 7 in {1890 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV),1891 "sc $LEV", IIC_BrB, []>;1892}1893 1894// We mark SCV as having no scheduling model since it is only meant to be used1895// as inline assembly. If we implement a builtin pattern for it we will need to1896// add it to the P9 and P10 scheduling models.1897let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in {1898 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV),1899 "scv $LEV", IIC_BrB, []>;1900}1901 1902// Branch history rolling buffer.1903def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, []>,1904 PPC970_DGroup_Single;1905 1906def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), (ins u10imm:$imm),1907 "mfbhrbe $RT, $imm", IIC_BrB, []>,1908 PPC970_DGroup_First;1909 1910def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", IIC_BrB, []>,1911 PPC970_DGroup_Single;1912 1913def : InstAlias<"rfebb", (RFEBB 1)>;1914 1915// DCB* instructions.1916def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr",1917 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>,1918 PPC970_DGroup_Single;1919def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr",1920 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>,1921 PPC970_DGroup_Single;1922def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr",1923 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>,1924 PPC970_DGroup_Single;1925def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr",1926 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>,1927 PPC970_DGroup_Single;1928def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr",1929 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>,1930 PPC970_DGroup_Single;1931 1932def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr),1933 "dcbf $addr, $TH", IIC_LdStDCBF, []>,1934 PPC970_DGroup_Single;1935 1936let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {1937def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),1938 "dcbt $addr, $TH", IIC_LdStDCBF, []>,1939 PPC970_DGroup_Single;1940def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),1941 "dcbtst $addr, $TH", IIC_LdStDCBF, []>,1942 PPC970_DGroup_Single;1943} // hasSideEffects = 01944 1945def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),1946 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>;1947def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),1948 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;1949def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),1950 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;1951def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),1952 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;1953 1954def : Pat<(int_ppc_dcbt xoaddr:$dst),1955 (DCBT 0, xoaddr:$dst)>;1956def : Pat<(int_ppc_dcbtst xoaddr:$dst),1957 (DCBTST 0, xoaddr:$dst)>;1958def : Pat<(int_ppc_dcbf xoaddr:$dst),1959 (DCBF 0, xoaddr:$dst)>;1960def : Pat<(int_ppc_icbt xoaddr:$dst),1961 (ICBT 0, xoaddr:$dst)>;1962 1963def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)),1964 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads1965def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)),1966 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores1967def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)),1968 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)1969 1970def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH),1971 (DCBT i32:$TH, xoaddr:$dst)>;1972def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH),1973 (DCBTST i32:$TH, xoaddr:$dst)>;1974 1975// Atomic operations1976// FIXME: some of these might be used with constant operands. This will result1977// in constant materialization instructions that may be redundant. We currently1978// clean this up in PPCMIPeephole with calls to1979// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them1980// in the first place.1981let Defs = [CR0] in {1982 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo<1983 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",1984 [(set i32:$dst, (atomic_load_add_i8 ForceXForm:$ptr, i32:$incr))]>;1985 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo<1986 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",1987 [(set i32:$dst, (atomic_load_sub_i8 ForceXForm:$ptr, i32:$incr))]>;1988 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo<1989 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",1990 [(set i32:$dst, (atomic_load_and_i8 ForceXForm:$ptr, i32:$incr))]>;1991 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo<1992 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",1993 [(set i32:$dst, (atomic_load_or_i8 ForceXForm:$ptr, i32:$incr))]>;1994 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo<1995 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",1996 [(set i32:$dst, (atomic_load_xor_i8 ForceXForm:$ptr, i32:$incr))]>;1997 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo<1998 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",1999 [(set i32:$dst, (atomic_load_nand_i8 ForceXForm:$ptr, i32:$incr))]>;2000 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo<2001 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",2002 [(set i32:$dst, (atomic_load_min_i8 ForceXForm:$ptr, i32:$incr))]>;2003 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo<2004 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",2005 [(set i32:$dst, (atomic_load_max_i8 ForceXForm:$ptr, i32:$incr))]>;2006 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo<2007 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",2008 [(set i32:$dst, (atomic_load_umin_i8 ForceXForm:$ptr, i32:$incr))]>;2009 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo<2010 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",2011 [(set i32:$dst, (atomic_load_umax_i8 ForceXForm:$ptr, i32:$incr))]>;2012 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo<2013 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",2014 [(set i32:$dst, (atomic_load_add_i16 ForceXForm:$ptr, i32:$incr))]>;2015 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo<2016 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",2017 [(set i32:$dst, (atomic_load_sub_i16 ForceXForm:$ptr, i32:$incr))]>;2018 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo<2019 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",2020 [(set i32:$dst, (atomic_load_and_i16 ForceXForm:$ptr, i32:$incr))]>;2021 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo<2022 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",2023 [(set i32:$dst, (atomic_load_or_i16 ForceXForm:$ptr, i32:$incr))]>;2024 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo<2025 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",2026 [(set i32:$dst, (atomic_load_xor_i16 ForceXForm:$ptr, i32:$incr))]>;2027 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo<2028 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",2029 [(set i32:$dst, (atomic_load_nand_i16 ForceXForm:$ptr, i32:$incr))]>;2030 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo<2031 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",2032 [(set i32:$dst, (atomic_load_min_i16 ForceXForm:$ptr, i32:$incr))]>;2033 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo<2034 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",2035 [(set i32:$dst, (atomic_load_max_i16 ForceXForm:$ptr, i32:$incr))]>;2036 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo<2037 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",2038 [(set i32:$dst, (atomic_load_umin_i16 ForceXForm:$ptr, i32:$incr))]>;2039 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo<2040 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",2041 [(set i32:$dst, (atomic_load_umax_i16 ForceXForm:$ptr, i32:$incr))]>;2042 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo<2043 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",2044 [(set i32:$dst, (atomic_load_add_i32 ForceXForm:$ptr, i32:$incr))]>;2045 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo<2046 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",2047 [(set i32:$dst, (atomic_load_sub_i32 ForceXForm:$ptr, i32:$incr))]>;2048 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo<2049 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",2050 [(set i32:$dst, (atomic_load_and_i32 ForceXForm:$ptr, i32:$incr))]>;2051 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo<2052 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",2053 [(set i32:$dst, (atomic_load_or_i32 ForceXForm:$ptr, i32:$incr))]>;2054 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo<2055 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",2056 [(set i32:$dst, (atomic_load_xor_i32 ForceXForm:$ptr, i32:$incr))]>;2057 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo<2058 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",2059 [(set i32:$dst, (atomic_load_nand_i32 ForceXForm:$ptr, i32:$incr))]>;2060 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo<2061 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",2062 [(set i32:$dst, (atomic_load_min_i32 ForceXForm:$ptr, i32:$incr))]>;2063 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo<2064 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",2065 [(set i32:$dst, (atomic_load_max_i32 ForceXForm:$ptr, i32:$incr))]>;2066 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo<2067 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",2068 [(set i32:$dst, (atomic_load_umin_i32 ForceXForm:$ptr, i32:$incr))]>;2069 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo<2070 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",2071 [(set i32:$dst, (atomic_load_umax_i32 ForceXForm:$ptr, i32:$incr))]>;2072 2073 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo<2074 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",2075 [(set i32:$dst, (atomic_cmp_swap_i8 ForceXForm:$ptr, i32:$old, i32:$new))]>;2076 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo<2077 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",2078 [(set i32:$dst, (atomic_cmp_swap_i16 ForceXForm:$ptr, i32:$old, i32:$new))]>;2079 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo<2080 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",2081 [(set i32:$dst, (atomic_cmp_swap_i32 ForceXForm:$ptr, i32:$old, i32:$new))]>;2082 2083 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo<2084 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",2085 [(set i32:$dst, (atomic_swap_i8 ForceXForm:$ptr, i32:$new))]>;2086 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo<2087 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",2088 [(set i32:$dst, (atomic_swap_i16 ForceXForm:$ptr, i32:$new))]>;2089 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo<2090 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",2091 [(set i32:$dst, (atomic_swap_i32 ForceXForm:$ptr, i32:$new))]>;2092}2093 2094def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new),2095 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>;2096def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new),2097 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>;2098 2099// Instructions to support atomic operations2100let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {2101def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2102 "lbarx $RST, $addr", IIC_LdStLWARX, []>,2103 Requires<[HasPartwordAtomics]>;2104 2105def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2106 "lharx $RST, $addr", IIC_LdStLWARX, []>,2107 Requires<[HasPartwordAtomics]>;2108 2109def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2110 "lwarx $RST, $addr", IIC_LdStLWARX, []>;2111 2112// Instructions to support lock versions of atomics2113// (EH=1 - see Power ISA 2.07 Book II 4.4.2)2114def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2115 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm,2116 Requires<[HasPartwordAtomics]>;2117 2118def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2119 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm,2120 Requires<[HasPartwordAtomics]>;2121 2122def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2123 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm;2124 2125// The atomic instructions use the destination register as well as the next one2126// or two registers in order (modulo 31).2127let hasExtraSrcRegAllocReq = 1 in2128def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB),2129 "lwat $RST, $RA, $RB", IIC_LdStLoad>,2130 Requires<[IsISA3_0]>;2131}2132 2133let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {2134def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2135 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>,2136 isRecordForm, Requires<[HasPartwordAtomics]>;2137 2138def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2139 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>,2140 isRecordForm, Requires<[HasPartwordAtomics]>;2141 2142def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2143 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm;2144}2145 2146let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in2147def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),2148 "stwat $RST, $RA, $RB", IIC_LdStStore>,2149 Requires<[IsISA3_0]>;2150 2151let isTrap = 1, hasCtrlDep = 1 in2152def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;2153 2154def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),2155 "twi $RST, $RA, $D", IIC_IntTrapW, []>;2156def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops),2157 "tw $RST, $RA, $RB", IIC_IntTrapW, []>;2158def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops),2159 "tdi $RST, $RA, $D", IIC_IntTrapD, []>;2160def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops),2161 "td $RST, $RA, $RB", IIC_IntTrapD, []>;2162 2163def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),2164 "popcntb $RA, $RST", IIC_IntGeneral,2165 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;2166 2167def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST),2168 "cdtbcd $RA, $RST", IIC_IntGeneral,2169 [(set i32:$RA, (int_ppc_cdtbcd i32:$RST))]>;2170def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST),2171 "cbcdtd $RA, $RST", IIC_IntGeneral,2172 [(set i32:$RA, (int_ppc_cbcdtd i32:$RST))]>;2173def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),2174 "addg6s $RT, $RA, $RB", IIC_IntGeneral,2175 [(set i32:$RT, (int_ppc_addg6s i32:$RA, i32:$RB))]>;2176 2177//===----------------------------------------------------------------------===//2178// PPC32 Load Instructions.2179//2180 2181// Unindexed (r+i) Loads.2182let PPC970_Unit = 2 in {2183def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr),2184 "lbz $RST, $addr", IIC_LdStLoad,2185 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,2186 SExt32To64;2187def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr),2188 "lha $RST, $addr", IIC_LdStLHA,2189 [(set i32:$RST, (sextloadi16 DForm:$addr))]>,2190 PPC970_DGroup_Cracked, SExt32To64;2191def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr),2192 "lhz $RST, $addr", IIC_LdStLoad,2193 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,2194 SExt32To64;2195def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr),2196 "lwz $RST, $addr", IIC_LdStLoad,2197 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64;2198 2199let Predicates = [HasFPU] in {2200def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr),2201 "lfs $RST, $addr", IIC_LdStLFD,2202 [(set f32:$RST, (load DForm:$addr))]>;2203def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr),2204 "lfd $RST, $addr", IIC_LdStLFD,2205 [(set f64:$RST, (load DForm:$addr))]>;2206}2207 2208 2209// Unindexed (r+i) Loads with Update (preinc).2210let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {2211def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2212 "lbzu $RST, $addr", IIC_LdStLoadUpd,2213 []>, RegConstraint<"$RA = $ea_result">;2214 2215def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2216 "lhau $RST, $addr", IIC_LdStLHAU,2217 []>, RegConstraint<"$addr.reg = $ea_result">;2218 2219def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2220 "lhzu $RST, $addr", IIC_LdStLoadUpd,2221 []>, RegConstraint<"$addr.reg = $ea_result">;2222 2223def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2224 "lwzu $RST, $addr", IIC_LdStLoadUpd,2225 []>, RegConstraint<"$addr.reg = $ea_result">;2226 2227let Predicates = [HasFPU] in {2228def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2229 "lfsu $RST, $addr", IIC_LdStLFDU,2230 []>, RegConstraint<"$addr.reg = $ea_result">;2231 2232def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),2233 "lfdu $RST, $addr", IIC_LdStLFDU,2234 []>, RegConstraint<"$addr.reg = $ea_result">;2235}2236 2237 2238// Indexed (r+r) Loads with Update (preinc).2239def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result),2240 (ins (memrr $RA, $RB):$addr),2241 "lbzux $RST, $addr", IIC_LdStLoadUpdX,2242 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2243 2244def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result),2245 (ins (memrr $RA, $RB):$addr),2246 "lhaux $RST, $addr", IIC_LdStLHAUX,2247 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2248 2249def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result),2250 (ins (memrr $RA, $RB):$addr),2251 "lhzux $RST, $addr", IIC_LdStLoadUpdX,2252 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2253 2254def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result),2255 (ins (memrr $RA, $RB):$addr),2256 "lwzux $RST, $addr", IIC_LdStLoadUpdX,2257 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2258 2259let Predicates = [HasFPU] in {2260def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result),2261 (ins (memrr $RA, $RB):$addr),2262 "lfsux $RST, $addr", IIC_LdStLFDUX,2263 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2264 2265def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result),2266 (ins (memrr $RA, $RB):$addr),2267 "lfdux $RST, $addr", IIC_LdStLFDUX,2268 []>, RegConstraint<"$addr.ptrreg = $ea_result">;2269}2270}2271}2272 2273// Indexed (r+r) Loads.2274//2275let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {2276def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2277 "lbzx $RST, $addr", IIC_LdStLoad,2278 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,2279 SExt32To64;2280def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2281 "lhax $RST, $addr", IIC_LdStLHA,2282 [(set i32:$RST, (sextloadi16 XForm:$addr))]>,2283 PPC970_DGroup_Cracked, SExt32To64;2284def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2285 "lhzx $RST, $addr", IIC_LdStLoad,2286 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64,2287 SExt32To64;2288def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2289 "lwzx $RST, $addr", IIC_LdStLoad,2290 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64;2291def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2292 "lhbrx $RST, $addr", IIC_LdStLoad,2293 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64;2294def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),2295 "lwbrx $RST, $addr", IIC_LdStLoad,2296 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64;2297 2298let Predicates = [HasFPU] in {2299def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr),2300 "lfsx $RST, $addr", IIC_LdStLFD,2301 [(set f32:$RST, (load XForm:$addr))]>;2302def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),2303 "lfdx $RST, $addr", IIC_LdStLFD,2304 [(set f64:$RST, (load XForm:$addr))]>;2305 2306def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),2307 "lfiwax $RST, $addr", IIC_LdStLFD,2308 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>;2309def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),2310 "lfiwzx $RST, $addr", IIC_LdStLFD,2311 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>;2312}2313}2314 2315// Load Multiple2316let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in2317def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src),2318 "lmw $RST, $src", IIC_LdStLMW, []>;2319 2320//===----------------------------------------------------------------------===//2321// PPC32 Store Instructions.2322//2323 2324// Unindexed (r+i) Stores.2325let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {2326def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),2327 "stb $RST, $dst", IIC_LdStStore,2328 [(truncstorei8 i32:$RST, DForm:$dst)]>;2329def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),2330 "sth $RST, $dst", IIC_LdStStore,2331 [(truncstorei16 i32:$RST, DForm:$dst)]>;2332def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),2333 "stw $RST, $dst", IIC_LdStStore,2334 [(store i32:$RST, DForm:$dst)]>;2335let Predicates = [HasFPU] in {2336def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst),2337 "stfs $RST, $dst", IIC_LdStSTFD,2338 [(store f32:$RST, DForm:$dst)]>;2339def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst),2340 "stfd $RST, $dst", IIC_LdStSTFD,2341 [(store f64:$RST, DForm:$dst)]>;2342}2343}2344 2345// Unindexed (r+i) Stores with Update (preinc).2346let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {2347def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),2348 "stbu $RST, $dst", IIC_LdStSTU, []>,2349 RegConstraint<"$dst.reg = $ea_res">;2350def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),2351 "sthu $RST, $dst", IIC_LdStSTU, []>,2352 RegConstraint<"$dst.reg = $ea_res">;2353def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),2354 "stwu $RST, $dst", IIC_LdStSTU, []>,2355 RegConstraint<"$dst.reg = $ea_res">;2356let Predicates = [HasFPU] in {2357def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst),2358 "stfsu $RST, $dst", IIC_LdStSTFDU, []>,2359 RegConstraint<"$dst.reg = $ea_res">;2360def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst),2361 "stfdu $RST, $dst", IIC_LdStSTFDU, []>,2362 RegConstraint<"$dst.reg = $ea_res">;2363}2364}2365 2366// Patterns to match the pre-inc stores. We can't put the patterns on2367// the instruction definitions directly as ISel wants the address base2368// and offset to be separate operands, not a single complex operand.2369def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),2370 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;2371def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),2372 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;2373def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),2374 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;2375def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),2376 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;2377def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),2378 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;2379 2380// Indexed (r+r) Stores.2381let PPC970_Unit = 2 in {2382def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2383 "stbx $RST, $addr", IIC_LdStStore,2384 [(truncstorei8 i32:$RST, XForm:$addr)]>,2385 PPC970_DGroup_Cracked;2386def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2387 "sthx $RST, $addr", IIC_LdStStore,2388 [(truncstorei16 i32:$RST, XForm:$addr)]>,2389 PPC970_DGroup_Cracked;2390def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2391 "stwx $RST, $addr", IIC_LdStStore,2392 [(store i32:$RST, XForm:$addr)]>,2393 PPC970_DGroup_Cracked;2394 2395def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2396 "sthbrx $RST, $addr", IIC_LdStStore,2397 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>,2398 PPC970_DGroup_Cracked;2399def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),2400 "stwbrx $RST, $addr", IIC_LdStStore,2401 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>,2402 PPC970_DGroup_Cracked;2403 2404let Predicates = [HasFPU] in {2405def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),2406 "stfiwx $RST, $addr", IIC_LdStSTFD,2407 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>;2408 2409def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr),2410 "stfsx $RST, $addr", IIC_LdStSTFD,2411 [(store f32:$RST, XForm:$addr)]>;2412def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),2413 "stfdx $RST, $addr", IIC_LdStSTFD,2414 [(store f64:$RST, XForm:$addr)]>;2415}2416}2417 2418// Indexed (r+r) Stores with Update (preinc).2419let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {2420def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),2421 (ins gprc:$RST, (memrr $RA, $RB):$addr),2422 "stbux $RST, $addr", IIC_LdStSTUX, []>,2423 RegConstraint<"$addr.ptrreg = $ea_res">,2424 PPC970_DGroup_Cracked;2425def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),2426 (ins gprc:$RST, (memrr $RA, $RB):$addr),2427 "sthux $RST, $addr", IIC_LdStSTUX, []>,2428 RegConstraint<"$addr.ptrreg = $ea_res">,2429 PPC970_DGroup_Cracked;2430def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),2431 (ins gprc:$RST, (memrr $RA, $RB):$addr),2432 "stwux $RST, $addr", IIC_LdStSTUX, []>,2433 RegConstraint<"$addr.ptrreg = $ea_res">,2434 PPC970_DGroup_Cracked;2435let Predicates = [HasFPU] in {2436def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),2437 (ins f4rc:$RST, (memrr $RA, $RB):$addr),2438 "stfsux $RST, $addr", IIC_LdStSTFDU, []>,2439 RegConstraint<"$addr.ptrreg = $ea_res">,2440 PPC970_DGroup_Cracked;2441def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),2442 (ins f8rc:$RST, (memrr $RA, $RB):$addr),2443 "stfdux $RST, $addr", IIC_LdStSTFDU, []>,2444 RegConstraint<"$addr.ptrreg = $ea_res">,2445 PPC970_DGroup_Cracked;2446}2447}2448 2449// Patterns to match the pre-inc stores. We can't put the patterns on2450// the instruction definitions directly as ISel wants the address base2451// and offset to be separate operands, not a single complex operand.2452def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),2453 (STBUX $rS, $ptrreg, $ptroff)>;2454def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),2455 (STHUX $rS, $ptrreg, $ptroff)>;2456def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),2457 (STWUX $rS, $ptrreg, $ptroff)>;2458let Predicates = [HasFPU] in {2459def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),2460 (STFSUX $rS, $ptrreg, $ptroff)>;2461def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),2462 (STFDUX $rS, $ptrreg, $ptroff)>;2463}2464 2465// Store Multiple2466let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in2467def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),2468 "stmw $RST, $dst", IIC_LdStLMW, []>;2469 2470def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L),2471 "sync $L", IIC_LdStSync, []>;2472 2473let isCodeGenOnly = 1 in {2474 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),2475 "msync", IIC_LdStSync, []> {2476 let L = 0;2477 }2478}2479 2480// We used to have EIEIO as value but E[0-9A-Z] is a reserved name2481def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),2482 "eieio", IIC_LdStLoad, []>;2483 2484def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",2485 [(int_ppc_eieio)]>;2486 2487def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;2488def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>;2489def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;2490def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;2491def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;2492def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;2493def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;2494def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;2495def : Pat<(int_ppc_eieio), (PseudoEIEIO)>;2496def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>;2497 2498//===----------------------------------------------------------------------===//2499// PPC32 Arithmetic Instructions.2500//2501 2502let PPC970_Unit = 1 in { // FXU Operations.2503def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),2504 "addi $RST, $RA, $D", IIC_IntSimple,2505 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>;2506let BaseName = "addic" in {2507let Defs = [CARRY] in2508def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),2509 "addic $RST, $RA, $D", IIC_IntGeneral,2510 [(set i32:$RST, (PPCaddc i32:$RA, imm32SExt16:$D))]>,2511 RecFormRel, PPC970_DGroup_Cracked;2512let Defs = [CARRY, CR0] in2513def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),2514 "addic. $RST, $RA, $D", IIC_IntGeneral,2515 []>, isRecordForm, RecFormRel;2516}2517def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D),2518 "addis $RST, $RA, $D", IIC_IntSimple,2519 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>;2520let isCodeGenOnly = 1 in2521def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),2522 "la $RST, $D($RA)", IIC_IntGeneral,2523 [(set i32:$RST, (add i32:$RA,2524 (PPClo tglobaladdr:$D, 0)))]>, MemriOp;2525def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),2526 "mulli $RST, $RA, $D", IIC_IntMulLI,2527 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>;2528let Defs = [CARRY] in2529def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),2530 "subfic $RST, $RA, $D", IIC_IntGeneral,2531 [(set i32:$RST, (PPCsubc imm32SExt16:$D, i32:$RA))]>;2532 2533let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {2534 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D),2535 "li $RST, $D", IIC_IntSimple,2536 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64;2537 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D),2538 "lis $RST, $D", IIC_IntSimple,2539 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64;2540}2541}2542 2543def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;2544def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;2545 2546let PPC970_Unit = 1 in { // FXU Operations.2547let Defs = [CR0] in {2548def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2549 "andi. $RA, $RST, $D", IIC_IntGeneral,2550 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>,2551 isRecordForm, ZExt32To64, SExt32To64;2552def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2553 "andis. $RA, $RST, $D", IIC_IntGeneral,2554 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>,2555 isRecordForm, ZExt32To64;2556}2557def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2558 "ori $RA, $RST, $D", IIC_IntSimple,2559 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>;2560def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2561 "oris $RA, $RST, $D", IIC_IntSimple,2562 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>;2563def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2564 "xori $RA, $RST, $D", IIC_IntSimple,2565 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>;2566def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),2567 "xoris $RA, $RST, $D", IIC_IntSimple,2568 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>;2569 2570def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,2571 []>;2572let isCodeGenOnly = 1 in {2573// The POWER6 and POWER7 have special group-terminating nops.2574def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),2575 "ori 1, 1, 0", IIC_IntSimple, []>;2576def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),2577 "ori 2, 2, 0", IIC_IntSimple, []>;2578}2579 2580let isCompare = 1, hasSideEffects = 0 in {2581 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D),2582 "cmpwi $BF, $RA, $D", IIC_IntCompare>;2583 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D),2584 "cmplwi $BF, $RA, $D", IIC_IntCompare>;2585 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF),2586 (ins u1imm:$L, gprc:$RA, gprc:$RB),2587 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>,2588 Requires<[IsISA3_0]>;2589}2590}2591 2592let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.2593let isCommutable = 1 in {2594defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2595 "nand", "$RA, $RST, $RB", IIC_IntSimple,2596 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>;2597defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2598 "and", "$RA, $RST, $RB", IIC_IntSimple,2599 [(set i32:$RA, (and i32:$RST, i32:$RB))]>;2600} // isCommutable2601defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2602 "andc", "$RA, $RST, $RB", IIC_IntSimple,2603 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>;2604let isCommutable = 1 in {2605defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2606 "or", "$RA, $RST, $RB", IIC_IntSimple,2607 [(set i32:$RA, (or i32:$RST, i32:$RB))]>;2608defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2609 "nor", "$RA, $RST, $RB", IIC_IntSimple,2610 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>;2611} // isCommutable2612defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2613 "orc", "$RA, $RST, $RB", IIC_IntSimple,2614 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>;2615let isCommutable = 1 in {2616defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2617 "eqv", "$RA, $RST, $RB", IIC_IntSimple,2618 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>;2619defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2620 "xor", "$RA, $RST, $RB", IIC_IntSimple,2621 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>;2622} // isCommutable2623defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2624 "slw", "$RA, $RST, $RB", IIC_IntGeneral,2625 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64;2626defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2627 "srw", "$RA, $RST, $RB", IIC_IntGeneral,2628 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64;2629defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2630 "sraw", "$RA, $RST, $RB", IIC_IntShift,2631 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64;2632}2633 2634def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;2635def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;2636 2637def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;2638def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;2639 2640def : InstAlias<"nop", (ORI R0, R0, 0)>;2641 2642let PPC970_Unit = 1 in { // FXU Operations.2643let hasSideEffects = 0 in {2644defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB),2645 "srawi", "$RA, $RST, $RB", IIC_IntShift,2646 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>,2647 SExt32To64;2648defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST),2649 "cntlzw", "$RA, $RST", IIC_IntGeneral,2650 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64;2651defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST),2652 "cnttzw", "$RA, $RST", IIC_IntGeneral,2653 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>,2654 ZExt32To64;2655defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST),2656 "extsb", "$RA, $RST", IIC_IntSimple,2657 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64;2658defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST),2659 "extsh", "$RA, $RST", IIC_IntSimple,2660 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64;2661 2662let isCommutable = 1 in2663def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),2664 "cmpb $RA, $RST, $RB", IIC_IntGeneral,2665 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>;2666}2667let isCompare = 1, hasSideEffects = 0 in {2668 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB),2669 "cmpw $BF, $RA, $RB", IIC_IntCompare>;2670 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB),2671 "cmplw $BF, $RA, $RB", IIC_IntCompare>;2672}2673}2674let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations.2675let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in {2676 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB),2677 "fcmpu $BF, $RA, $RB", IIC_FPCompare>;2678 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB),2679 "fcmpo $BF, $RA, $RB", IIC_FPCompare>;2680 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {2681 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),2682 "fcmpu $BF, $RA, $RB", IIC_FPCompare>;2683 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),2684 "fcmpo $BF, $RA, $RB", IIC_FPCompare>;2685 }2686}2687 2688def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),2689 "ftdiv $BF, $RA, $RB", IIC_FPCompare>;2690def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB),2691 "ftsqrt $BF, $RB", IIC_FPCompare,2692 [(set i32:$BF, (PPCftsqrt f64:$RB))]>;2693 2694let mayRaiseFPException = 1, hasSideEffects = 0 in {2695 let Interpretation64Bit = 1, isCodeGenOnly = 1 in2696 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB),2697 "frin", "$RST, $RB", IIC_FPGeneral,2698 [(set f64:$RST, (any_fround f64:$RB))]>;2699 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB),2700 "frin", "$RST, $RB", IIC_FPGeneral,2701 [(set f32:$RST, (any_fround f32:$RB))]>;2702 2703 let Interpretation64Bit = 1, isCodeGenOnly = 1 in2704 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB),2705 "frip", "$RST, $RB", IIC_FPGeneral,2706 [(set f64:$RST, (any_fceil f64:$RB))]>;2707 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB),2708 "frip", "$RST, $RB", IIC_FPGeneral,2709 [(set f32:$RST, (any_fceil f32:$RB))]>;2710 let Interpretation64Bit = 1, isCodeGenOnly = 1 in2711 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB),2712 "friz", "$RST, $RB", IIC_FPGeneral,2713 [(set f64:$RST, (any_ftrunc f64:$RB))]>;2714 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB),2715 "friz", "$RST, $RB", IIC_FPGeneral,2716 [(set f32:$RST, (any_ftrunc f32:$RB))]>;2717 let Interpretation64Bit = 1, isCodeGenOnly = 1 in2718 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB),2719 "frim", "$RST, $RB", IIC_FPGeneral,2720 [(set f64:$RST, (any_ffloor f64:$RB))]>;2721 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB),2722 "frim", "$RST, $RB", IIC_FPGeneral,2723 [(set f32:$RST, (any_ffloor f32:$RB))]>;2724}2725 2726let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in {2727 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB),2728 "fctiw", "$RST, $RB", IIC_FPGeneral,2729 []>;2730 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB),2731 "fctiwu", "$RST, $RB", IIC_FPGeneral,2732 []>;2733 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB),2734 "fctiwz", "$RST, $RB", IIC_FPGeneral,2735 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>;2736 2737 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB),2738 "frsp", "$RST, $RB", IIC_FPGeneral,2739 [(set f32:$RST, (any_fpround f64:$RB))]>;2740 2741 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB),2742 "fsqrt", "$RST, $RB", IIC_FPSqrtD,2743 [(set f64:$RST, (any_fsqrt f64:$RB))]>;2744 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB),2745 "fsqrts", "$RST, $RB", IIC_FPSqrtS,2746 [(set f32:$RST, (any_fsqrt f32:$RB))]>;2747}2748}2749 2750def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>;2751 2752/// Note that FMR is defined as pseudo-ops on the PPC970 because they are2753/// often coalesced away and we don't want the dispatch group builder to think2754/// that they will fill slots (which could cause the load of a LSU reject to2755/// sneak into a d-group with a store).2756let hasSideEffects = 0, Predicates = [HasFPU] in2757defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB),2758 "fmr", "$RST, $RB", IIC_FPGeneral,2759 []>, // (set f32:$RST, f32:$RB)2760 PPC970_Unit_Pseudo;2761 2762let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations.2763// These are artificially split into two different forms, for 4/8 byte FP.2764defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB),2765 "fabs", "$RST, $RB", IIC_FPGeneral,2766 [(set f32:$RST, (fabs f32:$RB))]>;2767let Interpretation64Bit = 1, isCodeGenOnly = 1 in2768defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB),2769 "fabs", "$RST, $RB", IIC_FPGeneral,2770 [(set f64:$RST, (fabs f64:$RB))]>;2771defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB),2772 "fnabs", "$RST, $RB", IIC_FPGeneral,2773 [(set f32:$RST, (fneg (fabs f32:$RB)))]>;2774let Interpretation64Bit = 1, isCodeGenOnly = 1 in2775defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB),2776 "fnabs", "$RST, $RB", IIC_FPGeneral,2777 [(set f64:$RST, (fneg (fabs f64:$RB)))]>;2778defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB),2779 "fneg", "$RST, $RB", IIC_FPGeneral,2780 [(set f32:$RST, (fneg f32:$RB))]>;2781let Interpretation64Bit = 1, isCodeGenOnly = 1 in2782defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB),2783 "fneg", "$RST, $RB", IIC_FPGeneral,2784 [(set f64:$RST, (fneg f64:$RB))]>;2785 2786defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB),2787 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral,2788 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>;2789let Interpretation64Bit = 1, isCodeGenOnly = 1 in2790defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),2791 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral,2792 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>;2793 2794// Reciprocal estimates.2795let mayRaiseFPException = 1 in {2796// Reciprocal estimate instructions (unary FP ops).2797defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB),2798 "fre", "$RST, $RB", IIC_FPGeneral,2799 [(set f64:$RST, (PPCfre f64:$RB))]>;2800defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB),2801 "fres", "$RST, $RB", IIC_FPGeneral,2802 [(set f32:$RST, (PPCfre f32:$RB))]>;2803defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB),2804 "frsqrte", "$RST, $RB", IIC_FPGeneral,2805 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>;2806defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB),2807 "frsqrtes", "$RST, $RB", IIC_FPGeneral,2808 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>;2809}2810}2811 2812// XL-Form instructions. condition register logical ops.2813//2814let hasSideEffects = 0 in2815def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),2816 "mcrf $BF, $BFA", IIC_BrMCR>,2817 PPC970_DGroup_First, PPC970_Unit_CRU;2818 2819// FIXME: According to the ISA (section 2.5.1 of version 2.06), the2820// condition-register logical instructions have preferred forms. Specifically,2821// it is preferred that the bit specified by the BT field be in the same2822// condition register as that specified by the bit BB. We might want to account2823// for this via hinting the register allocator and anti-dep breakers, or we2824// could constrain the register class to force this constraint and then loosen2825// it during register allocation via convertToThreeAddress or some similar2826// mechanism.2827 2828let isCommutable = 1 in {2829def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),2830 (ins crbitrc:$CRA, crbitrc:$CRB),2831 "crand $CRD, $CRA, $CRB", IIC_BrCR,2832 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;2833 2834def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),2835 (ins crbitrc:$CRA, crbitrc:$CRB),2836 "crnand $CRD, $CRA, $CRB", IIC_BrCR,2837 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;2838 2839def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),2840 (ins crbitrc:$CRA, crbitrc:$CRB),2841 "cror $CRD, $CRA, $CRB", IIC_BrCR,2842 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;2843 2844def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),2845 (ins crbitrc:$CRA, crbitrc:$CRB),2846 "crxor $CRD, $CRA, $CRB", IIC_BrCR,2847 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;2848 2849def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),2850 (ins crbitrc:$CRA, crbitrc:$CRB),2851 "crnor $CRD, $CRA, $CRB", IIC_BrCR,2852 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;2853def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),2854 (ins crbitrc:$CRA, crbitrc:$CRB),2855 "creqv $CRD, $CRA, $CRB", IIC_BrCR,2856 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;2857} // isCommutable2858 2859let isCodeGenOnly = 1 in2860def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA),2861 "crnot $CRD, $CRA", IIC_BrCR,2862 [(set i1:$CRD, (not i1:$CRA))]>;2863 2864def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),2865 (ins crbitrc:$CRA, crbitrc:$CRB),2866 "crandc $CRD, $CRA, $CRB", IIC_BrCR,2867 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;2868 2869def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),2870 (ins crbitrc:$CRA, crbitrc:$CRB),2871 "crorc $CRD, $CRA, $CRB", IIC_BrCR,2872 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;2873 2874let isCodeGenOnly = 1 in {2875let isReMaterializable = 1, isAsCheapAsAMove = 1 in {2876def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins),2877 "creqv $CRD, $CRD, $CRD", IIC_BrCR,2878 [(set i1:$CRD, 1)]>;2879 2880def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins),2881 "crxor $CRD, $CRD, $CRD", IIC_BrCR,2882 [(set i1:$CRD, 0)]>;2883}2884 2885let Defs = [CR1EQ], CRD = 6 in {2886def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),2887 "creqv 6, 6, 6", IIC_BrCR,2888 [(PPCcr6set)]>;2889 2890def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),2891 "crxor 6, 6, 6", IIC_BrCR,2892 [(PPCcr6unset)]>;2893}2894}2895 2896// XFX-Form instructions. Instructions that deal with SPRs.2897//2898 2899def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR),2900 "mfspr $RST, $SPR", IIC_SprMFSPR>;2901def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST),2902 "mtspr $SPR, $RST", IIC_SprMTSPR>;2903 2904def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR),2905 "mftb $RST, $SPR", IIC_SprMFTB>;2906 2907def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR),2908 "mfpmr $RST, $SPR", IIC_SprMFPMR>;2909 2910def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST),2911 "mtpmr $SPR, $RST", IIC_SprMTPMR>;2912 2913 2914// A pseudo-instruction used to implement the read of the 64-bit cycle counter2915// on a 32-bit target.2916let hasSideEffects = 1 in2917def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins),2918 "#ReadTB", []>;2919 2920let Uses = [CTR] in {2921def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins),2922 "mfctr $RST", IIC_SprMFSPR>,2923 PPC970_DGroup_First, PPC970_Unit_FXU;2924}2925let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in {2926def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST),2927 "mtctr $RST", IIC_SprMTSPR>,2928 PPC970_DGroup_First, PPC970_Unit_FXU;2929}2930let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in {2931let Pattern = [(int_set_loop_iterations i32:$RST)] in2932def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST),2933 "mtctr $RST", IIC_SprMTSPR>,2934 PPC970_DGroup_First, PPC970_Unit_FXU;2935}2936 2937let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in2938def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride),2939 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>;2940 2941let hasSideEffects = 0 in {2942let Defs = [LR] in {2943def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST),2944 "mtlr $RST", IIC_SprMTSPR>,2945 PPC970_DGroup_First, PPC970_Unit_FXU;2946}2947let Uses = [LR] in {2948def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins),2949 "mflr $RST", IIC_SprMFSPR>,2950 PPC970_DGroup_First, PPC970_Unit_FXU;2951}2952}2953 2954let hasSideEffects = 1 in {2955 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST),2956 "mtspr 3, $RST", IIC_SprMTSPR>,2957 PPC970_DGroup_Single, PPC970_Unit_FXU;2958 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins),2959 "mfspr $RST, 3", IIC_SprMFSPR>,2960 PPC970_DGroup_First, PPC970_Unit_FXU;2961}2962 2963// Disable these alias on AIX since they are not supported.2964let Predicates = [ModernAs] in {2965// Aliases for moving to/from dscr to mtspr/mfspr2966def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>;2967def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>;2968}2969 2970let isCodeGenOnly = 1 in {2971 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed2972 // like a GPR on the PPC970. As such, copies in and out have the same2973 // performance characteristics as an OR instruction.2974 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST),2975 "mtspr 256, $RST", IIC_IntGeneral>,2976 PPC970_DGroup_Single, PPC970_Unit_FXU;2977 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins),2978 "mfspr $RST, 256", IIC_IntGeneral>,2979 PPC970_DGroup_First, PPC970_Unit_FXU;2980 2981 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256,2982 (outs VRSAVERC:$SPR), (ins gprc:$RST),2983 "mtspr 256, $RST", IIC_IntGeneral>,2984 PPC970_DGroup_Single, PPC970_Unit_FXU;2985 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST),2986 (ins VRSAVERC:$SPR),2987 "mfspr $RST, 256", IIC_IntGeneral>,2988 PPC970_DGroup_First, PPC970_Unit_FXU;2989}2990 2991// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.2992def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;2993def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;2994 2995let hasSideEffects = 0 in {2996// mtocrf's input needs to be prepared by shifting by an amount dependent2997// on the cr register selected. Thus, post-ra anti-dep breaking must not2998// later change that register assignment.2999let hasExtraDefRegAllocReq = 1 in {3000def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST),3001 "mtocrf $FXM, $RST", IIC_BrMCRX>,3002 PPC970_DGroup_First, PPC970_Unit_CRU;3003 3004// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that3005// is dependent on the cr fields being set.3006def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST),3007 "mtcrf $FXM, $RST", IIC_BrMCRX>,3008 PPC970_MicroCode, PPC970_Unit_CRU;3009} // hasExtraDefRegAllocReq = 13010 3011// mfocrf's input needs to be prepared by shifting by an amount dependent3012// on the cr register selected. Thus, post-ra anti-dep breaking must not3013// later change that register assignment.3014let hasExtraSrcRegAllocReq = 1 in {3015def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM),3016 "mfocrf $RST, $FXM", IIC_SprMFCRF>,3017 PPC970_DGroup_First, PPC970_Unit_CRU;3018 3019// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that3020// is dependent on the cr fields being copied.3021def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins),3022 "mfcr $RT", IIC_SprMFCR>,3023 PPC970_MicroCode, PPC970_Unit_CRU;3024} // hasExtraSrcRegAllocReq = 13025 3026def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),3027 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;3028} // hasSideEffects = 03029 3030def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;3031 3032let Predicates = [HasFPU] in {3033// Custom inserter instruction to perform FADD in round-to-zero mode.3034let Uses = [RM], mayRaiseFPException = 1 in {3035 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",3036 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>;3037}3038 3039// The above pseudo gets expanded to make use of the following instructions3040// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.3041 3042// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def3043// RM should be set.3044let hasSideEffects = 1, Defs = [RM] in {3045def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),3046 "mtfsb0 $FM", IIC_IntMTFSB0,3047 [(int_ppc_mtfsb0 timm:$FM)]>,3048 PPC970_DGroup_Single, PPC970_Unit_FPU;3049def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),3050 "mtfsb1 $FM", IIC_IntMTFSB0,3051 [(int_ppc_mtfsb1 timm:$FM)]>,3052 PPC970_DGroup_Single, PPC970_Unit_FPU;3053}3054 3055let Defs = [RM], hasSideEffects = 1 in {3056 let isCodeGenOnly = 1 in3057 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT),3058 "mtfsf $FM, $RT", IIC_IntMTFSB0,3059 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>,3060 PPC970_DGroup_Single, PPC970_Unit_FPU;3061}3062let Uses = [RM], hasSideEffects = 1 in {3063 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins),3064 "mffs $RST", IIC_IntMFFS,3065 [(set f64:$RST, (PPCmffs))]>,3066 PPC970_DGroup_Single, PPC970_Unit_FPU;3067 3068 let Defs = [CR1] in3069 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins),3070 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm;3071 3072 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins),3073 "mffsce $RST", IIC_IntMFFS, []>,3074 PPC970_DGroup_Single, PPC970_Unit_FPU;3075 3076 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST),3077 (ins f8rc:$FRB), "mffscdrn $RST, $FRB",3078 IIC_IntMFFS, []>,3079 PPC970_DGroup_Single, PPC970_Unit_FPU;3080 3081 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST),3082 (ins u3imm:$DRM),3083 "mffscdrni $RST, $DRM",3084 IIC_IntMFFS, []>,3085 PPC970_DGroup_Single, PPC970_Unit_FPU;3086 3087 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST),3088 (ins f8rc:$FRB), "mffscrn $RST, $FRB",3089 IIC_IntMFFS, []>,3090 PPC970_DGroup_Single, PPC970_Unit_FPU;3091 3092 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST),3093 (ins u2imm:$RM), "mffscrni $RST, $RM",3094 IIC_IntMFFS, []>,3095 PPC970_DGroup_Single, PPC970_Unit_FPU;3096 3097 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins),3098 "mffsl $RST", IIC_IntMFFS, []>,3099 PPC970_DGroup_Single, PPC970_Unit_FPU;3100}3101}3102 3103let Predicates = [IsISA3_0] in {3104def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB),3105 "modsw $RST, $RA, $RB", IIC_IntDivW,3106 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>;3107def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB),3108 "moduw $RST, $RA, $RB", IIC_IntDivW,3109 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>;3110let hasSideEffects = 1 in3111def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT),3112 (ins gprc:$RA, gprc:$RB, u2imm:$CY),3113 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>;3114}3115 3116let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.3117// XO-Form instructions. Arithmetic instructions that can set overflow bit3118let isCommutable = 1 in3119defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3120 "add", "$RT, $RA, $RB", IIC_IntSimple,3121 [(set i32:$RT, (add i32:$RA, i32:$RB))]>;3122let isCodeGenOnly = 1 in3123def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB),3124 "add $RT, $RA, $RB", IIC_IntSimple,3125 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>;3126let isCommutable = 1 in3127defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3128 "addc", "$RT, $RA, $RB", IIC_IntGeneral,3129 [(set i32:$RT, (PPCaddc i32:$RA, i32:$RB))]>,3130 PPC970_DGroup_Cracked;3131 3132defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3133 "divw", "$RT, $RA, $RB", IIC_IntDivW,3134 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>;3135defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3136 "divwu", "$RT, $RA, $RB", IIC_IntDivW,3137 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>;3138defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3139 "divwe", "$RT, $RA, $RB", IIC_IntDivW,3140 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>,3141 Requires<[HasExtDiv]>;3142defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3143 "divweu", "$RT, $RA, $RB", IIC_IntDivW,3144 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>,3145 Requires<[HasExtDiv]>;3146let isCommutable = 1 in {3147defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3148 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW,3149 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>;3150defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3151 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU,3152 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>;3153defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3154 "mullw", "$RT, $RA, $RB", IIC_IntMulHW,3155 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>;3156} // isCommutable3157defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3158 "subf", "$RT, $RA, $RB", IIC_IntGeneral,3159 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>;3160defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3161 "subfc", "$RT, $RA, $RB", IIC_IntGeneral,3162 [(set i32:$RT, (PPCsubc i32:$RB, i32:$RA))]>,3163 PPC970_DGroup_Cracked;3164defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA),3165 "neg", "$RT, $RA", IIC_IntSimple,3166 [(set i32:$RT, (ineg i32:$RA))]>;3167let Uses = [CARRY] in {3168let isCommutable = 1 in3169defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3170 "adde", "$RT, $RA, $RB", IIC_IntGeneral,3171 [(set i32:$RT, (PPCadde i32:$RA, i32:$RB, CARRY))]>;3172defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA),3173 "addme", "$RT, $RA", IIC_IntGeneral,3174 [(set i32:$RT, (PPCadde i32:$RA, -1, CARRY))]>;3175defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA),3176 "addze", "$RT, $RA", IIC_IntGeneral,3177 [(set i32:$RT, (PPCadde i32:$RA, 0, CARRY))]>;3178defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),3179 "subfe", "$RT, $RA, $RB", IIC_IntGeneral,3180 [(set i32:$RT, (PPCsube i32:$RB, i32:$RA, CARRY))]>;3181defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA),3182 "subfme", "$RT, $RA", IIC_IntGeneral,3183 [(set i32:$RT, (PPCsube -1, i32:$RA, CARRY))]>;3184defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA),3185 "subfze", "$RT, $RA", IIC_IntGeneral,3186 [(set i32:$RT, (PPCsube 0, i32:$RA, CARRY))]>;3187}3188}3189 3190def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;3191def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;3192def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;3193def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;3194 3195// A-Form instructions. Most of the instructions executed in the FPU are of3196// this type.3197//3198let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations.3199let mayRaiseFPException = 1, Uses = [RM] in {3200let isCommutable = 1 in {3201 defm FMADD : AForm_1r<63, 29,3202 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),3203 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,3204 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>;3205 defm FMADDS : AForm_1r<59, 29,3206 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),3207 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3208 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>;3209 defm FMSUB : AForm_1r<63, 28,3210 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),3211 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,3212 [(set f64:$FRT,3213 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;3214 defm FMSUBS : AForm_1r<59, 28,3215 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),3216 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3217 [(set f32:$FRT,3218 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;3219 defm FNMADD : AForm_1r<63, 31,3220 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),3221 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,3222 [(set f64:$FRT,3223 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;3224 defm FNMADDS : AForm_1r<59, 31,3225 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),3226 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3227 [(set f32:$FRT,3228 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;3229 defm FNMSUB : AForm_1r<63, 30,3230 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),3231 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,3232 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC,3233 (fneg f64:$FRB))))]>;3234 defm FNMSUBS : AForm_1r<59, 30,3235 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),3236 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3237 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC,3238 (fneg f32:$FRB))))]>;3239} // isCommutable3240}3241// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid3242// having 4 of these, force the comparison to always be an 8-byte double (code3243// should use an FMRSD if the input comparison value really wants to be a float)3244// and 4/8 byte forms for the result and operand type..3245let Interpretation64Bit = 1, isCodeGenOnly = 1 in3246defm FSELD : AForm_1r<63, 23,3247 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),3248 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3249 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;3250defm FSELS : AForm_1r<63, 23,3251 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),3252 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,3253 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;3254let Uses = [RM], mayRaiseFPException = 1 in {3255 let isCommutable = 1 in {3256 defm FADD : AForm_2r<63, 21,3257 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),3258 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,3259 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>;3260 defm FADDS : AForm_2r<59, 21,3261 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),3262 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,3263 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>;3264 } // isCommutable3265 defm FDIV : AForm_2r<63, 18,3266 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),3267 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,3268 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>;3269 defm FDIVS : AForm_2r<59, 18,3270 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),3271 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,3272 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>;3273 let isCommutable = 1 in {3274 defm FMUL : AForm_3r<63, 25,3275 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),3276 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,3277 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>;3278 defm FMULS : AForm_3r<59, 25,3279 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),3280 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,3281 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>;3282 } // isCommutable3283 defm FSUB : AForm_2r<63, 20,3284 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),3285 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,3286 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>;3287 defm FSUBS : AForm_2r<59, 20,3288 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),3289 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,3290 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>;3291 }3292}3293 3294let hasSideEffects = 0 in {3295let PPC970_Unit = 1 in { // FXU Operations.3296 let isSelect = 1 in3297 def ISEL : AForm_4<31, 15,3298 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND),3299 "isel $RT, $RA, $RB, $COND", IIC_IntISEL,3300 []>;3301}3302 3303let PPC970_Unit = 1 in { // FXU Operations.3304// M-Form instructions. rotate and mask instructions.3305//3306let isCommutable = 1 in {3307// RLWIMI can be commuted if the rotate amount is zero.3308defm RLWIMI : MForm_2r<20, (outs gprc:$RA),3309 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB,3310 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",3311 IIC_IntRotate, []>, PPC970_DGroup_Cracked,3312 RegConstraint<"$RAi = $RA">;3313}3314let BaseName = "rlwinm" in {3315def RLWINM : MForm_2<21,3316 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),3317 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,3318 []>, RecFormRel;3319let Defs = [CR0] in3320def RLWINM_rec : MForm_2<21,3321 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),3322 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,3323 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked;3324}3325defm RLWNM : MForm_1r<23, (outs gprc:$RA),3326 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME),3327 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral,3328 []>;3329}3330} // hasSideEffects = 03331 3332//===----------------------------------------------------------------------===//3333// PowerPC Instruction Patterns3334//3335 3336// Arbitrary immediate support. Implement in terms of LIS/ORI.3337def : Pat<(i32 imm:$imm),3338 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;3339 3340// Implement the 'not' operation with the NOR instruction.3341def i32not : OutPatFrag<(ops node:$in),3342 (NOR $in, $in)>;3343def : Pat<(not i32:$in),3344 (i32not $in)>;3345 3346// ADD an arbitrary immediate.3347def : Pat<(add i32:$in, imm:$imm),3348 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;3349// OR an arbitrary immediate.3350def : Pat<(or i32:$in, imm:$imm),3351 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;3352// XOR an arbitrary immediate.3353def : Pat<(xor i32:$in, imm:$imm),3354 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;3355// SUBFIC3356def : Pat<(sub imm32SExt16:$imm, i32:$in),3357 (SUBFIC $in, imm:$imm)>;3358 3359// SHL/SRL3360def : Pat<(shl i32:$in, (i32 imm:$imm)),3361 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;3362def : Pat<(srl i32:$in, (i32 imm:$imm)),3363 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;3364 3365// ROTL3366def : Pat<(rotl i32:$in, i32:$sh),3367 (RLWNM $in, $sh, 0, 31)>;3368def : Pat<(rotl i32:$in, (i32 imm:$imm)),3369 (RLWINM $in, imm:$imm, 0, 31)>;3370 3371// RLWNM3372def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),3373 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;3374 3375// Calls3376def : Pat<(PPCcall (i32 tglobaladdr:$dst)),3377 (BL tglobaladdr:$dst)>;3378 3379def : Pat<(PPCcall (i32 texternalsym:$dst)),3380 (BL texternalsym:$dst)>;3381 3382def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)),3383 (BL_RM tglobaladdr:$dst)>;3384 3385def : Pat<(PPCcall_rm (i32 texternalsym:$dst)),3386 (BL_RM texternalsym:$dst)>;3387 3388// Calls for AIX only3389def : Pat<(PPCcall (i32 mcsym:$dst)),3390 (BL mcsym:$dst)>;3391 3392def : Pat<(PPCcall_nop (i32 mcsym:$dst)),3393 (BL_NOP mcsym:$dst)>;3394 3395def : Pat<(PPCcall_nop (i32 texternalsym:$dst)),3396 (BL_NOP texternalsym:$dst)>;3397 3398def : Pat<(PPCcall_rm (i32 mcsym:$dst)),3399 (BL_RM mcsym:$dst)>;3400 3401def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)),3402 (BL_NOP_RM mcsym:$dst)>;3403 3404def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)),3405 (BL_NOP_RM texternalsym:$dst)>;3406 3407def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),3408 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;3409 3410def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),3411 (TCRETURNdi texternalsym:$dst, imm:$imm)>;3412 3413def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),3414 (TCRETURNri CTRRC:$dst, imm:$imm)>;3415 3416def : Pat<(int_ppc_fence), (FENCE)>;3417def : Pat<(int_ppc_readflm), (MFFS)>;3418def : Pat<(int_ppc_mffsl), (MFFSL)>;3419 3420// Hi and Lo for Darwin Global Addresses.3421def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;3422def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;3423def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;3424def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;3425def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;3426def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;3427def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;3428def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;3429def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),3430 (ADDIS $in, tglobaltlsaddr:$g)>;3431def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),3432 (ADDI $in, tglobaltlsaddr:$g)>;3433def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),3434 (ADDIS $in, tglobaladdr:$g)>;3435def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),3436 (ADDIS $in, tconstpool:$g)>;3437def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),3438 (ADDIS $in, tjumptable:$g)>;3439def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),3440 (ADDIS $in, tblockaddress:$g)>;3441 3442// Support for thread-local storage.3443def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",3444 [(set i32:$rD, (PPCppc32GOT))]>;3445 3446// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.3447// This uses two output registers, the first as the real output, the second as a3448// temporary register, used internally in code generation. A "bl" also clobbers LR.3449let Defs = [LR] in3450def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",3451 []>;3452 3453def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg),3454 "#LDgotTprelL32",3455 [(set i32:$rD,3456 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;3457def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),3458 (ADD4TLS $in, tglobaltlsaddr:$g)>;3459 3460def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),3461 "#ADDItlsgdL32",3462 [(set i32:$rD,3463 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;3464// LR is a true define, while the rest of the Defs are clobbers. R3 is3465// explicitly defined when this op is created, so not mentioned here.3466let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3467 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in3468def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),3469 "GETtlsADDR32",3470 [(set i32:$rD,3471 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;3472// R3 is explicitly defined when this op is created, so not mentioned here.3473// The rest of the Defs are the exact set of registers that will be clobbered by3474// the call.3475let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3476 Defs = [R0,R4,R5,R11,LR,CR0] in {3477def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle),3478 "GETtlsADDR32AIX",3479 [(set i32:$rD,3480 (PPCgetTlsAddr i32:$offset, i32:$handle))]>;3481def GETtlsMOD32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle),3482 "GETtlsMOD32AIX",3483 [(set i32:$rD,3484 (PPCgetTlsMod i32:$handle))]>;3485}3486 3487// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is3488// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both3489// R3 and the LR (link register).3490let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3491 Defs = [R3,LR] in3492def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins),3493 "GETtlsTpointer32AIX",3494 [(set i32:$rD, (PPCgetTpointer))]>;3495 3496// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX.3497// PPCaddTls is used in local- and initial-exec accesses in order to:3498// - Get the address of a variable (add the variable offset to the thread3499// pointer, retrieved by calling .__get_tpointer).3500// - Create an opportunity to optimize the user of the loaded address.3501def : Pat<(PPCaddTls i32:$in, i32:$addr),3502 (ADD4TLS $in, $addr)>;3503 3504// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR3505// are true defines while the rest of the Defs are clobbers.3506let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3507 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in3508def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),3509 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),3510 "#ADDItlsgdLADDR32",3511 [(set i32:$rD,3512 (PPCaddiTlsgdLAddr i32:$reg,3513 tglobaltlsaddr:$disp,3514 tglobaltlsaddr:$sym))]>;3515def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),3516 "#ADDItlsldL32",3517 [(set i32:$rD,3518 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;3519// This pseudo is expanded to two copies to put the variable offset in R4 and3520// the region handle in R3 and GETtlsADDR32AIX.3521def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle),3522 "#TLSGDAIX",3523 [(set i32:$rD,3524 (PPCTlsgdAIX i32:$offset, i32:$handle))]>;3525// This pseudo is expanded to the call to GETtlsMOD32AIX.3526def TLSLDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle),3527 "#TLSLDAIX", [(set i32:$rD, (PPCTlsldAIX i32:$handle))]>;3528// LR is a true define, while the rest of the Defs are clobbers. R3 is3529// explicitly defined when this op is created, so not mentioned here.3530let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3531 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in3532def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),3533 "GETtlsldADDR32",3534 [(set i32:$rD,3535 (PPCgetTlsldAddr i32:$reg,3536 tglobaltlsaddr:$sym))]>;3537// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR3538// are true defines while the rest of the Defs are clobbers.3539let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,3540 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in3541def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),3542 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),3543 "#ADDItlsldLADDR32",3544 [(set i32:$rD,3545 (PPCaddiTlsldLAddr i32:$reg,3546 tglobaltlsaddr:$disp,3547 tglobaltlsaddr:$sym))]>;3548def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),3549 "#ADDIdtprelL32",3550 [(set i32:$rD,3551 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;3552def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),3553 "#ADDISdtprelHA32",3554 [(set i32:$rD,3555 (PPCaddisDtprelHA i32:$reg,3556 tglobaltlsaddr:$disp))]>;3557 3558// Support for Position-independent code3559def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),3560 "#LWZtoc",3561 [(set i32:$rD,3562 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;3563def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg),3564 "#LWZtocL",3565 [(set i32:$rD,3566 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;3567def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),3568 "#ADDIStocHA", []>;3569// TOC Data Transform on AIX3570def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp),3571 "#ADDItoc", []>;3572def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),3573 "#ADDItocL", []>;3574 3575// Get Global (GOT) Base Register offset, from the word immediately preceding3576// the function label.3577def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;3578 3579// Pseudo-instruction marked for deletion. When deleting the instruction would3580// cause iterator invalidation in MIR transformation passes, this pseudo can be3581// used instead. It will be removed unconditionally at pre-emit time (prior to3582// branch selection).3583def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>;3584 3585// Standard shifts. These are represented separately from the real shifts above3586// so that we can distinguish between shifts that allow 5-bit and 6-bit shift3587// amounts.3588def : Pat<(sra i32:$rS, i32:$rB),3589 (SRAW $rS, $rB)>;3590def : Pat<(srl i32:$rS, i32:$rB),3591 (SRW $rS, $rB)>;3592def : Pat<(shl i32:$rS, i32:$rB),3593 (SLW $rS, $rB)>;3594 3595def : Pat<(i32 (zextloadi1 DForm:$src)),3596 (LBZ DForm:$src)>;3597def : Pat<(i32 (zextloadi1 XForm:$src)),3598 (LBZX XForm:$src)>;3599def : Pat<(i32 (extloadi1 DForm:$src)),3600 (LBZ DForm:$src)>;3601def : Pat<(i32 (extloadi1 XForm:$src)),3602 (LBZX XForm:$src)>;3603def : Pat<(i32 (extloadi8 DForm:$src)),3604 (LBZ DForm:$src)>;3605def : Pat<(i32 (extloadi8 XForm:$src)),3606 (LBZX XForm:$src)>;3607def : Pat<(i32 (extloadi16 DForm:$src)),3608 (LHZ DForm:$src)>;3609def : Pat<(i32 (extloadi16 XForm:$src)),3610 (LHZX XForm:$src)>;3611let Predicates = [HasFPU] in {3612def : Pat<(f64 (extloadf32 DForm:$src)),3613 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>;3614def : Pat<(f64 (extloadf32 XForm:$src)),3615 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>;3616 3617def : Pat<(f64 (any_fpextend f32:$src)),3618 (COPY_TO_REGCLASS $src, F8RC)>;3619}3620 3621// Only seq_cst fences require the heavyweight sync (SYNC 0).3622// All others can use the lightweight sync (SYNC 1).3623// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html3624// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits3625// versions of Power.3626def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>;3627def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>;3628def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>;3629def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;3630 3631let Predicates = [HasFPU] in {3632// Additional fnmsub patterns for custom node3633def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),3634 (FNMSUB $A, $B, $C)>;3635def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C),3636 (FNMSUBS $A, $B, $C)>;3637def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),3638 (FMSUB $A, $B, $C)>;3639def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)),3640 (FMSUBS $A, $B, $C)>;3641def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),3642 (FNMADD $A, $B, $C)>;3643def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)),3644 (FNMADDS $A, $B, $C)>;3645 3646// FCOPYSIGN's operand types need not agree.3647def : Pat<(fcopysign f64:$frB, f32:$frA),3648 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;3649def : Pat<(fcopysign f32:$frB, f64:$frA),3650 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;3651}3652 3653// XL Compat intrinsics.3654def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>;3655def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>;3656def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>;3657def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>;3658def : Pat<(int_ppc_fre f64:$A), (FRE $A)>;3659def : Pat<(int_ppc_fres f32:$A), (FRES $A)>;3660def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>;3661def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>;3662 3663include "PPCInstrAltivec.td"3664include "PPCInstrSPE.td"3665include "PPCInstr64Bit.td"3666include "PPCInstrVSX.td"3667include "PPCInstrHTM.td"3668 3669def crnot : OutPatFrag<(ops node:$in),3670 (CRNOT $in)>;3671def : Pat<(not i1:$in),3672 (crnot $in)>;3673 3674// Pseudo-instructions for alternate assembly syntax (never used by codegen).3675// These are aliases that require C++ handling to convert to the target3676// instruction, while InstAliases can be handled directly by tblgen.3677class PPCAsmPseudo<string asm, dag iops>3678 : Instruction {3679 let Namespace = "PPC";3680 bit PPC64 = 0; // Default value, override with isPPC643681 3682 let OutOperandList = (outs);3683 let InOperandList = iops;3684 let Pattern = [];3685 let AsmString = asm;3686 let isAsmParserOnly = 1;3687 let isPseudo = 1;3688 let hasNoSchedulingInfo = 1;3689 3690 // Indicate that this instruction takes a register+immediate memory operand.3691 bits<1> MemriOp = 0;3692 let TSFlags{10} = MemriOp;3693}3694 3695// Mask immediates for MMA instructions (2, 4 and 8 bits).3696def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;3697def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;3698def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;3699 3700// Prefixed instructions may require access to the above defs at a later3701// time so we include this after the def.3702include "PPCInstrP10.td"3703include "PPCInstrFutureMMA.td"3704include "PPCInstrFuture.td"3705include "PPCInstrMMA.td"3706include "PPCInstrDFP.td"3707 3708// Patterns for arithmetic i1 operations.3709def : Pat<(add i1:$a, i1:$b),3710 (CRXOR $a, $b)>;3711def : Pat<(sub i1:$a, i1:$b),3712 (CRXOR $a, $b)>;3713def : Pat<(mul i1:$a, i1:$b),3714 (CRAND $a, $b)>;3715 3716// We're sometimes asked to materialize i1 -1, which is just 1 in this case3717// (-1 is used to mean all bits set).3718def : Pat<(i1 -1), (CRSET)>;3719 3720// i1 extensions, implemented in terms of isel.3721def : Pat<(i32 (zext i1:$in)),3722 (SELECT_I4 $in, (LI 1), (LI 0))>;3723def : Pat<(i32 (sext i1:$in)),3724 (SELECT_I4 $in, (LI -1), (LI 0))>;3725 3726def : Pat<(i64 (zext i1:$in)),3727 (SELECT_I8 $in, (LI8 1), (LI8 0))>;3728def : Pat<(i64 (sext i1:$in)),3729 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;3730 3731// FIXME: We should choose either a zext or a sext based on other constants3732// already around.3733def : Pat<(i32 (anyext i1:$in)),3734 (SELECT_I4 $in, (LI 1), (LI 0))>;3735def : Pat<(i64 (anyext i1:$in)),3736 (SELECT_I8 $in, (LI8 1), (LI8 0))>;3737 3738// match setcc on i1 variables.3739// CRANDC is:3740// 1 1 : F3741// 1 0 : T3742// 0 1 : F3743// 0 0 : F3744//3745// LT is:3746// -1 -1 : F3747// -1 0 : T3748// 0 -1 : F3749// 0 0 : F3750//3751// ULT is:3752// 1 1 : F3753// 1 0 : F3754// 0 1 : T3755// 0 0 : F3756def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),3757 (CRANDC $s1, $s2)>;3758def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),3759 (CRANDC $s2, $s1)>;3760// CRORC is:3761// 1 1 : T3762// 1 0 : T3763// 0 1 : F3764// 0 0 : T3765//3766// LE is:3767// -1 -1 : T3768// -1 0 : T3769// 0 -1 : F3770// 0 0 : T3771//3772// ULE is:3773// 1 1 : T3774// 1 0 : F3775// 0 1 : T3776// 0 0 : T3777def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),3778 (CRORC $s1, $s2)>;3779def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),3780 (CRORC $s2, $s1)>;3781 3782def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),3783 (CREQV $s1, $s2)>;3784 3785// GE is:3786// -1 -1 : T3787// -1 0 : F3788// 0 -1 : T3789// 0 0 : T3790//3791// UGE is:3792// 1 1 : T3793// 1 0 : T3794// 0 1 : F3795// 0 0 : T3796def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),3797 (CRORC $s2, $s1)>;3798def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),3799 (CRORC $s1, $s2)>;3800 3801// GT is:3802// -1 -1 : F3803// -1 0 : F3804// 0 -1 : T3805// 0 0 : F3806//3807// UGT is:3808// 1 1 : F3809// 1 0 : T3810// 0 1 : F3811// 0 0 : F3812def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),3813 (CRANDC $s2, $s1)>;3814def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),3815 (CRANDC $s1, $s2)>;3816 3817def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),3818 (CRXOR $s1, $s2)>;3819 3820// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,3821// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for3822// floating-point types.3823 3824multiclass CRNotPat<dag pattern, dag result> {3825 def : Pat<pattern, (crnot result)>;3826 def : Pat<(not pattern), result>;3827 3828 // We can also fold the crnot into an extension:3829 def : Pat<(i32 (zext pattern)),3830 (SELECT_I4 result, (LI 0), (LI 1))>;3831 def : Pat<(i32 (sext pattern)),3832 (SELECT_I4 result, (LI 0), (LI -1))>;3833 3834 // We can also fold the crnot into an extension:3835 def : Pat<(i64 (zext pattern)),3836 (SELECT_I8 result, (LI8 0), (LI8 1))>;3837 def : Pat<(i64 (sext pattern)),3838 (SELECT_I8 result, (LI8 0), (LI8 -1))>;3839 3840 // FIXME: We should choose either a zext or a sext based on other constants3841 // already around.3842 def : Pat<(i32 (anyext pattern)),3843 (SELECT_I4 result, (LI 0), (LI 1))>;3844 3845 def : Pat<(i64 (anyext pattern)),3846 (SELECT_I8 result, (LI8 0), (LI8 1))>;3847}3848 3849// FIXME: Because of what seems like a bug in TableGen's type-inference code,3850// we need to write imm:$imm in the output patterns below, not just $imm, or3851// else the resulting matcher will not correctly add the immediate operand3852// (making it a register operand instead).3853 3854// extended SETCC.3855multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,3856 OutPatFrag rfrag, OutPatFrag rfrag8> {3857 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),3858 (rfrag $s1)>;3859 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),3860 (rfrag8 $s1)>;3861 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),3862 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;3863 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),3864 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;3865 3866 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),3867 (rfrag $s1)>;3868 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),3869 (rfrag8 $s1)>;3870 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),3871 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;3872 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),3873 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;3874}3875 3876// Note that we do all inversions below with i(32|64)not, instead of using3877// (xori x, 1) because on the A2 nor has single-cycle latency while xori3878// has 2-cycle latency.3879 3880defm : ExtSetCCPat<SETEQ,3881 PatFrag<(ops node:$in, node:$cc),3882 (setcc $in, 0, $cc)>,3883 OutPatFrag<(ops node:$in),3884 (RLWINM (CNTLZW $in), 27, 31, 31)>,3885 OutPatFrag<(ops node:$in),3886 (RLDICL (CNTLZD $in), 58, 63)> >;3887 3888defm : ExtSetCCPat<SETNE,3889 PatFrag<(ops node:$in, node:$cc),3890 (setcc $in, 0, $cc)>,3891 OutPatFrag<(ops node:$in),3892 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,3893 OutPatFrag<(ops node:$in),3894 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;3895 3896defm : ExtSetCCPat<SETLT,3897 PatFrag<(ops node:$in, node:$cc),3898 (setcc $in, 0, $cc)>,3899 OutPatFrag<(ops node:$in),3900 (RLWINM $in, 1, 31, 31)>,3901 OutPatFrag<(ops node:$in),3902 (RLDICL $in, 1, 63)> >;3903 3904defm : ExtSetCCPat<SETGE,3905 PatFrag<(ops node:$in, node:$cc),3906 (setcc $in, 0, $cc)>,3907 OutPatFrag<(ops node:$in),3908 (RLWINM (i32not $in), 1, 31, 31)>,3909 OutPatFrag<(ops node:$in),3910 (RLDICL (i64not $in), 1, 63)> >;3911 3912defm : ExtSetCCPat<SETGT,3913 PatFrag<(ops node:$in, node:$cc),3914 (setcc $in, 0, $cc)>,3915 OutPatFrag<(ops node:$in),3916 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,3917 OutPatFrag<(ops node:$in),3918 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;3919 3920defm : ExtSetCCPat<SETLE,3921 PatFrag<(ops node:$in, node:$cc),3922 (setcc $in, 0, $cc)>,3923 OutPatFrag<(ops node:$in),3924 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,3925 OutPatFrag<(ops node:$in),3926 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;3927 3928defm : ExtSetCCPat<SETLT,3929 PatFrag<(ops node:$in, node:$cc),3930 (setcc $in, -1, $cc)>,3931 OutPatFrag<(ops node:$in),3932 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,3933 OutPatFrag<(ops node:$in),3934 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;3935 3936defm : ExtSetCCPat<SETGE,3937 PatFrag<(ops node:$in, node:$cc),3938 (setcc $in, -1, $cc)>,3939 OutPatFrag<(ops node:$in),3940 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,3941 OutPatFrag<(ops node:$in),3942 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;3943 3944defm : ExtSetCCPat<SETGT,3945 PatFrag<(ops node:$in, node:$cc),3946 (setcc $in, -1, $cc)>,3947 OutPatFrag<(ops node:$in),3948 (RLWINM (i32not $in), 1, 31, 31)>,3949 OutPatFrag<(ops node:$in),3950 (RLDICL (i64not $in), 1, 63)> >;3951 3952defm : ExtSetCCPat<SETLE,3953 PatFrag<(ops node:$in, node:$cc),3954 (setcc $in, -1, $cc)>,3955 OutPatFrag<(ops node:$in),3956 (RLWINM $in, 1, 31, 31)>,3957 OutPatFrag<(ops node:$in),3958 (RLDICL $in, 1, 63)> >;3959 3960// An extended SETCC with shift amount.3961multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,3962 OutPatFrag rfrag, OutPatFrag rfrag8> {3963 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),3964 (rfrag $s1, $sa)>;3965 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),3966 (rfrag8 $s1, $sa)>;3967 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),3968 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;3969 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),3970 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;3971 3972 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),3973 (rfrag $s1, $sa)>;3974 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),3975 (rfrag8 $s1, $sa)>;3976 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),3977 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;3978 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),3979 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;3980}3981 3982defm : ExtSetCCShiftPat<SETNE,3983 PatFrag<(ops node:$in, node:$sa, node:$cc),3984 (setcc (and $in, (shl 1, $sa)), 0, $cc)>,3985 OutPatFrag<(ops node:$in, node:$sa),3986 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,3987 OutPatFrag<(ops node:$in, node:$sa),3988 (RLDCL $in, (SUBFIC $sa, 64), 63)> >;3989 3990defm : ExtSetCCShiftPat<SETEQ,3991 PatFrag<(ops node:$in, node:$sa, node:$cc),3992 (setcc (and $in, (shl 1, $sa)), 0, $cc)>,3993 OutPatFrag<(ops node:$in, node:$sa),3994 (RLWNM (i32not $in),3995 (SUBFIC $sa, 32), 31, 31)>,3996 OutPatFrag<(ops node:$in, node:$sa),3997 (RLDCL (i64not $in),3998 (SUBFIC $sa, 64), 63)> >;3999 4000// SETCC for i32.4001def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),4002 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;4003def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),4004 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;4005def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),4006 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;4007def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),4008 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;4009def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),4010 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;4011def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),4012 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;4013 4014// For non-equality comparisons, the default code would materialize the4015// constant, then compare against it, like this:4016// lis r2, 46604017// ori r2, r2, 221364018// cmpw cr0, r3, r24019// beq cr0,L64020// Since we are just comparing for equality, we can emit this instead:4021// xoris r0,r3,0x12344022// cmplwi cr0,r0,0x56784023// beq cr0,L64024 4025def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),4026 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),4027 (LO16 imm:$imm)), sub_eq)>;4028 4029def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),4030 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;4031def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),4032 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;4033def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),4034 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;4035def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),4036 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;4037def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),4038 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;4039 4040// SETCC for i64.4041def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),4042 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;4043def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),4044 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;4045def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),4046 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;4047def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),4048 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;4049def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),4050 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;4051def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),4052 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;4053 4054// For non-equality comparisons, the default code would materialize the4055// constant, then compare against it, like this:4056// lis r2, 46604057// ori r2, r2, 221364058// cmpd cr0, r3, r24059// beq cr0,L64060// Since we are just comparing for equality, we can emit this instead:4061// xoris r0,r3,0x12344062// cmpldi cr0,r0,0x56784063// beq cr0,L64064 4065def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),4066 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),4067 (LO16 imm:$imm)), sub_eq)>;4068 4069def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),4070 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;4071def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),4072 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;4073def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),4074 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;4075def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),4076 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;4077def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),4078 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;4079 4080let Predicates = [IsNotISA3_1] in {4081// Instantiations of CRNotPat for i32.4082defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),4083 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;4084defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),4085 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;4086defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),4087 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;4088defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),4089 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;4090defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),4091 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;4092defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),4093 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;4094 4095defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),4096 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),4097 (LO16 imm:$imm)), sub_eq)>;4098 4099defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),4100 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;4101defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),4102 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;4103defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),4104 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;4105defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),4106 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;4107defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),4108 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;4109 4110// Instantiations of CRNotPat for i64.4111defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),4112 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;4113defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),4114 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;4115defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),4116 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;4117defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),4118 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;4119defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),4120 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;4121defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),4122 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;4123 4124defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),4125 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),4126 (LO16 imm:$imm)), sub_eq)>;4127 4128defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),4129 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;4130defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),4131 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;4132defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),4133 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;4134defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),4135 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;4136defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),4137 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;4138}4139 4140multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {4141 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),4142 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;4143 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),4144 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;4145 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),4146 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;4147 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),4148 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;4149 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),4150 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;4151 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),4152 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;4153 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),4154 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;4155 4156 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),4157 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;4158 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),4159 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;4160 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),4161 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;4162 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),4163 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;4164 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),4165 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;4166 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),4167 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;4168 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)),4169 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;4170}4171 4172let Predicates = [HasFPU] in {4173// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set.4174// SETCC for f32.4175defm : FSetCCPat<any_fsetcc, f32, FCMPUS>;4176 4177// SETCC for f64.4178defm : FSetCCPat<any_fsetcc, f64, FCMPUD>;4179 4180// SETCC for f128.4181defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>;4182 4183// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and,4184// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN,4185// then VXVC is set.4186// SETCCS for f32.4187defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>;4188 4189// SETCCS for f64.4190defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>;4191 4192// SETCCS for f128.4193defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>;4194}4195 4196// This must be in this file because it relies on patterns defined in this file4197// after the inclusion of the instruction sets.4198let Predicates = [HasSPE] in {4199// SETCC for f32.4200def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)),4201 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;4202def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),4203 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;4204def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)),4205 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;4206def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)),4207 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;4208def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)),4209 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;4210def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)),4211 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;4212 4213defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),4214 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;4215defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)),4216 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;4217defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)),4218 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;4219defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)),4220 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;4221defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)),4222 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;4223defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)),4224 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;4225 4226// SETCC for f64.4227def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)),4228 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;4229def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),4230 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;4231def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)),4232 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;4233def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)),4234 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;4235def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)),4236 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;4237def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)),4238 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;4239 4240defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),4241 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;4242defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)),4243 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;4244defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)),4245 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;4246defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)),4247 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;4248defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)),4249 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;4250defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)),4251 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;4252}4253// match select on i1 variables:4254def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),4255 (CROR (CRAND $cond , $tval),4256 (CRAND (crnot $cond), $fval))>;4257 4258// match selectcc on i1 variables:4259// select (lhs == rhs), tval, fval is:4260// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)4261def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),4262 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),4263 (CRAND (CRORC $rhs, $lhs), $fval))>;4264def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),4265 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),4266 (CRAND (CRORC $lhs, $rhs), $fval))>;4267def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),4268 (CROR (CRAND (CRORC $lhs, $rhs), $tval),4269 (CRAND (CRANDC $rhs, $lhs), $fval))>;4270def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),4271 (CROR (CRAND (CRORC $rhs, $lhs), $tval),4272 (CRAND (CRANDC $lhs, $rhs), $fval))>;4273def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),4274 (CROR (CRAND (CREQV $lhs, $rhs), $tval),4275 (CRAND (CRXOR $lhs, $rhs), $fval))>;4276def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),4277 (CROR (CRAND (CRORC $rhs, $lhs), $tval),4278 (CRAND (CRANDC $lhs, $rhs), $fval))>;4279def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),4280 (CROR (CRAND (CRORC $lhs, $rhs), $tval),4281 (CRAND (CRANDC $rhs, $lhs), $fval))>;4282def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),4283 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),4284 (CRAND (CRORC $lhs, $rhs), $fval))>;4285def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),4286 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),4287 (CRAND (CRORC $rhs, $lhs), $fval))>;4288def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),4289 (CROR (CRAND (CREQV $lhs, $rhs), $fval),4290 (CRAND (CRXOR $lhs, $rhs), $tval))>;4291 4292// match selectcc on i1 variables with non-i1 output.4293def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),4294 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;4295def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),4296 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;4297def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),4298 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;4299def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),4300 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;4301def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),4302 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;4303def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),4304 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;4305def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),4306 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;4307def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),4308 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;4309def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),4310 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;4311def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),4312 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;4313 4314def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),4315 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;4316def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),4317 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;4318def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),4319 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;4320def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),4321 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;4322def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),4323 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;4324def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),4325 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;4326def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),4327 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;4328def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),4329 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;4330def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),4331 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;4332def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),4333 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;4334 4335let Predicates = [HasFPU] in {4336def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),4337 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;4338def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),4339 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;4340def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),4341 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;4342def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),4343 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;4344def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),4345 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;4346def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),4347 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;4348def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),4349 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;4350def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),4351 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;4352def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),4353 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;4354def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),4355 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;4356 4357def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),4358 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;4359def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),4360 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;4361def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),4362 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;4363def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),4364 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;4365def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),4366 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;4367def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),4368 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;4369def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),4370 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;4371def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),4372 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;4373def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),4374 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;4375def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),4376 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;4377}4378 4379def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)),4380 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;4381def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)),4382 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;4383def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)),4384 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;4385def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)),4386 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;4387def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)),4388 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>;4389def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)),4390 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;4391def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)),4392 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;4393def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)),4394 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;4395def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)),4396 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;4397def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)),4398 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>;4399 4400def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),4401 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;4402def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),4403 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;4404def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),4405 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;4406def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),4407 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;4408def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),4409 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;4410def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),4411 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;4412def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),4413 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;4414def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),4415 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;4416def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),4417 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;4418def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),4419 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;4420 4421let Defs = [CR0] in {4422def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),4423 "#ANDI_rec_1_EQ_BIT",4424 [(set i1:$dst, (trunc (not i32:$in)))]>;4425def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),4426 "#ANDI_rec_1_GT_BIT",4427 [(set i1:$dst, (trunc i32:$in))]>;4428 4429def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),4430 "#ANDI_rec_1_EQ_BIT8",4431 [(set i1:$dst, (trunc (not i64:$in)))]>;4432def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),4433 "#ANDI_rec_1_GT_BIT8",4434 [(set i1:$dst, (trunc i64:$in))]>;4435}4436 4437def : Pat<(i1 (not (trunc i32:$in))),4438 (ANDI_rec_1_EQ_BIT $in)>;4439def : Pat<(i1 (not (trunc i64:$in))),4440 (ANDI_rec_1_EQ_BIT8 $in)>;4441 4442def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;4443def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>;4444def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>;4445 4446//===----------------------------------------------------------------------===//4447// PowerPC Instructions used for assembler/disassembler only4448//4449 4450// FIXME: For B=0 or B > 8, the registers following RT are used.4451// WARNING: Do not add patterns for this instruction without fixing this.4452def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST),4453 (ins gprc:$RA, u5imm:$RB),4454 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>;4455 4456// FIXME: For B=0 or B > 8, the registers following RT are used.4457// WARNING: Do not add patterns for this instruction without fixing this.4458def STSWI : XForm_base_r3xo_memOp<31, 725, (outs),4459 (ins gprc:$RST, gprc:$RA, u5imm:$RB),4460 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>;4461 4462def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),4463 "isync", IIC_SprISYNC, []>;4464 4465def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr),4466 "icbi $addr", IIC_LdStICBI, []>;4467 4468def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L),4469 "wait $L", IIC_LdStLoad, []>;4470 4471def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),4472 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;4473 4474def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),4475 "mtsr $SR, $RS", IIC_SprMTSR>;4476 4477def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),4478 "mfsr $RS, $SR", IIC_SprMFSR>;4479 4480def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),4481 "mtsrin $RS, $RB", IIC_SprMTSR>;4482 4483def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),4484 "mfsrin $RS, $RB", IIC_SprMFSR>;4485 4486def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L),4487 "mtmsr $RS, $L", IIC_SprMTMSR>;4488 4489def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),4490 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {4491 let L = 0;4492}4493 4494def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,4495 Requires<[IsBookE]> {4496 bits<1> E;4497 4498 let Inst{16} = E;4499 let Inst{21...30} = 163;4500}4501 4502def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB),4503 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>;4504def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB),4505 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>;4506 4507def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;4508def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;4509def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;4510def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;4511 4512def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins),4513 "mfmsr $RST", IIC_SprMFMSR, []>;4514 4515def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L),4516 "mtmsrd $RS, $L", IIC_SprMTMSRD>;4517 4518def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),4519 "mcrfs $BF, $BFA", IIC_BrMCR>;4520 4521// All MTFSF variants may change the rounding mode so conservatively set it4522// as an implicit def for all of them.4523let Predicates = [HasFPU] in {4524let Defs = [RM], hasSideEffects = 1 in {4525let isCodeGenOnly = 1,4526 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in4527def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U),4528 "mtfsfi $BF, $U", IIC_IntMFFS>;4529def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W),4530 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;4531let Defs = [CR1] in4532def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W),4533 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;4534 4535def MTFSF : XFLForm_1<63, 711, (outs),4536 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),4537 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;4538let Defs = [CR1] in4539def MTFSF_rec : XFLForm_1<63, 711, (outs),4540 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),4541 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;4542}4543 4544def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>;4545def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>;4546def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;4547def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;4548}4549 4550def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),4551 "slbie $RB", IIC_SprSLBIE, []>;4552 4553def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB),4554 "slbmte $RST, $RB", IIC_SprSLBMTE, []>;4555 4556def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB),4557 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>;4558 4559def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),4560 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;4561 4562def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;4563 4564let Defs = [CR0] in4565def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB),4566 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm;4567 4568def TLBIA : XForm_0<31, 370, (outs), (ins),4569 "tlbia", IIC_SprTLBIA, []>;4570 4571def TLBSYNC : XForm_0<31, 566, (outs), (ins),4572 "tlbsync", IIC_SprTLBSYNC, []>;4573 4574def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),4575 "tlbiel $RB", IIC_SprTLBIEL, []>;4576 4577def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),4578 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;4579def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),4580 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;4581 4582def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB),4583 "tlbie $RB, $RST", IIC_SprTLBIE, []>,4584 Requires<[IsNotISA3_0]>;4585 4586let Predicates = [IsISA3_0] in {4587 def TLBIEP9 : XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),4588 (ins gprc:$RB, gprc:$RS, u2imm:$RIC,4589 u1imm:$PRS, u1imm:$R),4590 "tlbie $RB, $RS, $RIC, $PRS, $R", []>;4591 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {4592 def TLBIE8P94593 : XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),4594 (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,4595 u1imm:$PRS, u1imm:$R),4596 "tlbie $RB, $RS, $RIC, $PRS, $R", []>;4597 }4598}4599 4600def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",4601 IIC_LdStLoad>, Requires<[IsBookE]>;4602 4603def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",4604 IIC_LdStLoad>, Requires<[IsBookE]>;4605 4606def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB),4607 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>;4608 4609def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),4610 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;4611 4612def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),4613 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;4614 4615def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS),4616 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;4617 4618def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS),4619 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;4620 4621def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB),4622 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>,4623 Requires<[IsPPC4xx]>;4624def TLBSX2D : XForm_base_r3xo<31, 914, (outs),4625 (ins gprc:$RST, gprc:$RA, gprc:$RB),4626 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>,4627 Requires<[IsPPC4xx]>, isRecordForm;4628 4629def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;4630 4631def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,4632 Requires<[IsBookE]>;4633def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,4634 Requires<[IsBookE]>;4635 4636def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,4637 Requires<[IsE500]>;4638def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,4639 Requires<[IsE500]>;4640 4641def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR),4642 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;4643def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR),4644 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;4645 4646def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;4647def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;4648 4649def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;4650 4651def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST),4652 (ins gprc:$RA, gprc:$RB),4653 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>;4654def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST),4655 (ins gprc:$RA, gprc:$RB),4656 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>;4657def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST),4658 (ins gprc:$RA, gprc:$RB),4659 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>;4660def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST),4661 (ins gprc:$RA, gprc:$RB),4662 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>;4663 4664def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs),4665 (ins gprc:$RST, gprc:$RA, gprc:$RB),4666 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>;4667def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs),4668 (ins gprc:$RST, gprc:$RA, gprc:$RB),4669 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>;4670def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs),4671 (ins gprc:$RST, gprc:$RA, gprc:$RB),4672 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>;4673def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs),4674 (ins gprc:$RST, gprc:$RA, gprc:$RB),4675 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>;4676 4677// External PID Load Store Instructions4678 4679def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),4680 "lbepx $RST, $addr", IIC_LdStLoad, []>,4681 Requires<[IsE500]>;4682 4683def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),4684 "lfdepx $RST, $addr", IIC_LdStLFD, []>,4685 Requires<[IsE500]>;4686 4687def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),4688 "lhepx $RST, $addr", IIC_LdStLoad, []>,4689 Requires<[IsE500]>;4690 4691def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),4692 "lwepx $RST, $addr", IIC_LdStLoad, []>,4693 Requires<[IsE500]>;4694 4695def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),4696 "stbepx $RST, $addr", IIC_LdStStore, []>,4697 Requires<[IsE500]>;4698 4699def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),4700 "stfdepx $RST, $addr", IIC_LdStSTFD, []>,4701 Requires<[IsE500]>;4702 4703def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),4704 "sthepx $RST, $addr", IIC_LdStStore, []>,4705 Requires<[IsE500]>;4706 4707def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),4708 "stwepx $RST, $addr", IIC_LdStStore, []>,4709 Requires<[IsE500]>;4710 4711def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr",4712 IIC_LdStDCBF, []>, Requires<[IsE500]>;4713 4714def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr",4715 IIC_LdStDCBF, []>, Requires<[IsE500]>;4716 4717def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH),4718 "dcbtep $TH, $addr", IIC_LdStDCBF, []>,4719 Requires<[IsE500]>;4720 4721def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH),4722 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>,4723 Requires<[IsE500]>;4724 4725def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr",4726 IIC_LdStDCBF, []>, Requires<[IsE500]>;4727 4728def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr",4729 IIC_LdStDCBF, []>, Requires<[IsE500]>;4730 4731def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr",4732 IIC_LdStICBI, []>, Requires<[IsE500]>;4733 4734//===----------------------------------------------------------------------===//4735// PowerPC Assembler Instruction Aliases4736//4737 4738def : InstAlias<"sc", (SC 0)>;4739 4740def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;4741def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>;4742def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;4743def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;4744def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;4745 4746def : InstAlias<"wait", (WAIT 0)>;4747def : InstAlias<"waitrsv", (WAIT 1)>;4748def : InstAlias<"waitimpl", (WAIT 2)>;4749 4750def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;4751 4752def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;4753def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;4754 4755def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;4756def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;4757def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;4758 4759def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;4760def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;4761def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;4762 4763def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;4764def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;4765def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;4766 4767def : Pat<(int_ppc_isync), (ISYNC)>;4768def : Pat<(int_ppc_dcbfl xoaddr:$dst),4769 (DCBF 1, xoaddr:$dst)>;4770def : Pat<(int_ppc_dcbflp xoaddr:$dst),4771 (DCBF 3, xoaddr:$dst)>;4772 4773let Predicates = [IsISA3_1] in {4774 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>;4775 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>;4776 4777 def : Pat<(int_ppc_dcbfps xoaddr:$dst),4778 (DCBF 4, xoaddr:$dst)>;4779 def : Pat<(int_ppc_dcbstps xoaddr:$dst),4780 (DCBF 6, xoaddr:$dst)>;4781}4782 4783def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;4784def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;4785def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;4786def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;4787 4788def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;4789def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;4790def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;4791 4792def : InstAlias<"xnop", (XORI R0, R0, 0)>;4793 4794def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;4795def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;4796 4797//Disable this alias on AIX for now because as does not support them.4798let Predicates = [ModernAs] in {4799 4800foreach BR = 0-7 in {4801 def : InstAlias<"mfbr"#BR#" $Rx",4802 (MFDCR gprc:$Rx, !add(BR, 0x80))>,4803 Requires<[IsPPC4xx]>;4804 def : InstAlias<"mtbr"#BR#" $Rx",4805 (MTDCR gprc:$Rx, !add(BR, 0x80))>,4806 Requires<[IsPPC4xx]>;4807}4808 4809def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;4810def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;4811def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>;4812def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>;4813 4814def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;4815def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;4816 4817def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>;4818def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>;4819 4820def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>;4821def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>;4822 4823def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>;4824def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>;4825 4826def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;4827def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;4828 4829def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;4830def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;4831 4832def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;4833def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;4834 4835def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;4836def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;4837 4838def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;4839def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;4840 4841def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;4842def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;4843 4844def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;4845def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;4846 4847def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;4848def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;4849 4850def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;4851def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;4852 4853def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;4854def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;4855def : InstAlias<"mtpidr $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsISA3_0]>;4856def : InstAlias<"mfpidr $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsISA3_0]>;4857 4858foreach SPRG = 4-7 in {4859 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,4860 Requires<[IsBookE]>;4861 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,4862 Requires<[IsBookE]>;4863 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,4864 Requires<[IsBookE]>;4865 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,4866 Requires<[IsBookE]>;4867}4868 4869foreach SPRG = 0-3 in {4870 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;4871 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;4872 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;4873 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;4874}4875 4876def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;4877def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;4878 4879def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;4880def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;4881 4882def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;4883 4884def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;4885def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;4886 4887foreach BATR = 0-3 in {4888 def : InstAlias<"mtdbatu "#BATR#", $Rx",4889 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,4890 Requires<[IsPPC6xx]>;4891 def : InstAlias<"mfdbatu $Rx, "#BATR,4892 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,4893 Requires<[IsPPC6xx]>;4894 def : InstAlias<"mtdbatl "#BATR#", $Rx",4895 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,4896 Requires<[IsPPC6xx]>;4897 def : InstAlias<"mfdbatl $Rx, "#BATR,4898 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,4899 Requires<[IsPPC6xx]>;4900 def : InstAlias<"mtibatu "#BATR#", $Rx",4901 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,4902 Requires<[IsPPC6xx]>;4903 def : InstAlias<"mfibatu $Rx, "#BATR,4904 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,4905 Requires<[IsPPC6xx]>;4906 def : InstAlias<"mtibatl "#BATR#", $Rx",4907 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,4908 Requires<[IsPPC6xx]>;4909 def : InstAlias<"mfibatl $Rx, "#BATR,4910 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,4911 Requires<[IsPPC6xx]>;4912}4913 4914def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>;4915def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>;4916 4917def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;4918def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;4919 4920def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;4921def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;4922 4923def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;4924def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;4925 4926def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;4927def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;4928 4929def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;4930def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;4931 4932def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;4933def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;4934 4935def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;4936def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;4937 4938def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;4939def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;4940 4941def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;4942def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;4943 4944}4945 4946def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>, Requires<[IsNotISA3_0]>;4947let Predicates = [IsISA3_0] in {4948 def : InstAlias<"tlbie $RB", (TLBIEP9 R0, gprc:$RB, 0, 0, 0)>;4949 def : InstAlias<"tlbie $RB, $RS", (TLBIEP9 gprc:$RB, gprc:$RS, 0, 0, 0)>;4950}4951 4952def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,4953 Requires<[IsPPC4xx]>;4954def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,4955 Requires<[IsPPC4xx]>;4956def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,4957 Requires<[IsPPC4xx]>;4958def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,4959 Requires<[IsPPC4xx]>;4960 4961def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>;4962def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>;4963def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,4964 Requires<[IsBookE]>;4965def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;4966 4967def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemriOp;4968 4969def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",4970 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;4971def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",4972 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;4973def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",4974 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;4975def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm",4976 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;4977 4978def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",4979 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,4980 ZExt32To64;4981def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",4982 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,4983 ZExt32To64;4984def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",4985 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4986def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",4987 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4988def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",4989 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4990def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",4991 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4992def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",4993 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4994def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",4995 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;4996def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",4997 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;4998def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",4999 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;5000def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",5001 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;5002def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n",5003 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;5004def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",5005 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;5006def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n",5007 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;5008def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",5009 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;5010def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",5011 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;5012def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",5013 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;5014def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",5015 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;5016 5017def : InstAlias<"isellt $rT, $rA, $rB",5018 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>;5019def : InstAlias<"iselgt $rT, $rA, $rB",5020 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>;5021def : InstAlias<"iseleq $rT, $rA, $rB",5022 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>;5023 5024def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;5025def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;5026def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;5027def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;5028def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;5029def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;5030 5031def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;5032def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>;5033// The POWER variant5034def : MnemonicAlias<"cntlz", "cntlzw">;5035def : MnemonicAlias<"cntlz.", "cntlzw.">;5036 5037def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",5038 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5039def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",5040 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5041def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",5042 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5043def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",5044 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5045def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",5046 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5047def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",5048 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;5049def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",5050 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5051def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",5052 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5053def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",5054 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5055def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n",5056 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5057def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",5058 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5059def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n",5060 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5061def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",5062 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5063def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",5064 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;5065def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",5066 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;5067def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",5068 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;5069def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;5070 5071def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;5072def : InstAlias<"rotldi $rA, $rS, $n",5073 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>;5074def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;5075def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;5076def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;5077def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;5078def : InstAlias<"clrldi $rA, $rS, $n",5079 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;5080def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;5081def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;5082 5083def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",5084 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5085def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",5086 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5087def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",5088 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5089def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",5090 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5091def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",5092 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5093def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",5094 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;5095def PPCLdFixedAddr :5096 PPCPostRAExpPseudo<(outs gprc:$rT), (ins i32imm:$imm), "#FA_LOAD",5097 [(set i32:$rT, (int_ppc_fixed_addr_ld timm:$imm))]>;5098 5099// These generic branch instruction forms are used for the assembler parser only.5100// Defs and Uses are conservative, since we don't know the BO value.5101let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in {5102 let Defs = [CTR], Uses = [CTR, RM] in {5103 def gBC : BForm_3<16, 0, 0, (outs),5104 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD),5105 "bc $BO, $BI, $BD">;5106 def gBCA : BForm_3<16, 1, 0, (outs),5107 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD),5108 "bca $BO, $BI, $BD">;5109 let isAsmParserOnly = 1 in {5110 def gBCat : BForm_3_at<16, 0, 0, (outs),5111 (ins u5imm:$BO, atimm:$at, crbitrc:$BI,5112 condbrtarget:$BD),5113 "bc$at $BO, $BI, $BD">;5114 def gBCAat : BForm_3_at<16, 1, 0, (outs),5115 (ins u5imm:$BO, atimm:$at, crbitrc:$BI,5116 abscondbrtarget:$BD),5117 "bca$at $BO, $BI, $BD">;5118 } // isAsmParserOnly = 15119 }5120 let Defs = [LR, CTR], Uses = [CTR, RM] in {5121 def gBCL : BForm_3<16, 0, 1, (outs),5122 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD),5123 "bcl $BO, $BI, $BD">;5124 def gBCLA : BForm_3<16, 1, 1, (outs),5125 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD),5126 "bcla $BO, $BI, $BD">;5127 let isAsmParserOnly = 1 in {5128 def gBCLat : BForm_3_at<16, 0, 1, (outs),5129 (ins u5imm:$BO, atimm:$at, crbitrc:$BI,5130 condbrtarget:$BD),5131 "bcl$at $BO, $BI, $BD">;5132 def gBCLAat : BForm_3_at<16, 1, 1, (outs),5133 (ins u5imm:$BO, atimm:$at, crbitrc:$BI,5134 abscondbrtarget:$BD),5135 "bcla$at $BO, $BI, $BD">;5136 } // // isAsmParserOnly = 15137 }5138 let Defs = [CTR], Uses = [CTR, LR, RM] in5139 def gBCLR : XLForm_2<19, 16, 0, (outs),5140 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),5141 "bclr $BO, $BI, $BH", IIC_BrB, []>;5142 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in5143 def gBCLRL : XLForm_2<19, 16, 1, (outs),5144 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),5145 "bclrl $BO, $BI, $BH", IIC_BrB, []>;5146 let Defs = [CTR], Uses = [CTR, LR, RM] in5147 def gBCCTR : XLForm_2<19, 528, 0, (outs),5148 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),5149 "bcctr $BO, $BI, $BH", IIC_BrB, []>;5150 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in5151 def gBCCTRL : XLForm_2<19, 528, 1, (outs),5152 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),5153 "bcctrl $BO, $BI, $BH", IIC_BrB, []>;5154}5155 5156multiclass BranchSimpleMnemonicAT<string pm, int at> {5157 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,5158 condbrtarget:$dst)>;5159 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,5160 condbrtarget:$dst)>;5161 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,5162 condbrtarget:$dst)>;5163 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,5164 condbrtarget:$dst)>;5165}5166defm : BranchSimpleMnemonicAT<"+", 3>;5167defm : BranchSimpleMnemonicAT<"-", 2>;5168 5169def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;5170def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;5171def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;5172def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;5173 5174multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {5175 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;5176 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;5177 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;5178 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;5179 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;5180 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;5181}5182multiclass BranchSimpleMnemonic2<string name, string pm, int bo>5183 : BranchSimpleMnemonic1<name, pm, bo> {5184 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;5185 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;5186}5187defm : BranchSimpleMnemonic2<"t", "", 12>;5188defm : BranchSimpleMnemonic2<"f", "", 4>;5189defm : BranchSimpleMnemonic2<"t", "-", 14>;5190defm : BranchSimpleMnemonic2<"f", "-", 6>;5191defm : BranchSimpleMnemonic2<"t", "+", 15>;5192defm : BranchSimpleMnemonic2<"f", "+", 7>;5193defm : BranchSimpleMnemonic1<"dnzt", "", 8>;5194defm : BranchSimpleMnemonic1<"dnzf", "", 0>;5195defm : BranchSimpleMnemonic1<"dzt", "", 10>;5196defm : BranchSimpleMnemonic1<"dzf", "", 2>;5197 5198multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {5199 def : InstAlias<"b"#name#pm#" $cc, $dst",5200 (BCC (pred bibo, crrc:$cc), condbrtarget:$dst)>;5201 def : InstAlias<"b"#name#pm#" $dst",5202 (BCC (pred bibo, CR0), condbrtarget:$dst)>;5203 5204 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",5205 (BCCA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;5206 def : InstAlias<"b"#name#"a"#pm#" $dst",5207 (BCCA (pred bibo, CR0), abscondbrtarget:$dst)>;5208 5209 def : InstAlias<"b"#name#"lr"#pm#" $cc",5210 (BCCLR (pred bibo, crrc:$cc))>;5211 def : InstAlias<"b"#name#"lr"#pm,5212 (BCCLR (pred bibo, CR0))>;5213 5214 def : InstAlias<"b"#name#"ctr"#pm#" $cc",5215 (BCCCTR (pred bibo, crrc:$cc))>;5216 def : InstAlias<"b"#name#"ctr"#pm,5217 (BCCCTR (pred bibo, CR0))>;5218 5219 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",5220 (BCCL (pred bibo, crrc:$cc), condbrtarget:$dst)>;5221 def : InstAlias<"b"#name#"l"#pm#" $dst",5222 (BCCL (pred bibo, CR0), condbrtarget:$dst)>;5223 5224 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",5225 (BCCLA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;5226 def : InstAlias<"b"#name#"la"#pm#" $dst",5227 (BCCLA (pred bibo, CR0), abscondbrtarget:$dst)>;5228 5229 def : InstAlias<"b"#name#"lrl"#pm#" $cc",5230 (BCCLRL (pred bibo, crrc:$cc))>;5231 def : InstAlias<"b"#name#"lrl"#pm,5232 (BCCLRL (pred bibo, CR0))>;5233 5234 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",5235 (BCCCTRL (pred bibo, crrc:$cc))>;5236 def : InstAlias<"b"#name#"ctrl"#pm,5237 (BCCCTRL (pred bibo, CR0))>;5238}5239multiclass BranchExtendedMnemonic<string name, int bibo> {5240 defm : BranchExtendedMnemonicPM<name, "", bibo>;5241 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;5242 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;5243}5244defm : BranchExtendedMnemonic<"lt", 12>;5245defm : BranchExtendedMnemonic<"gt", 44>;5246defm : BranchExtendedMnemonic<"eq", 76>;5247defm : BranchExtendedMnemonic<"un", 108>;5248defm : BranchExtendedMnemonic<"so", 108>;5249defm : BranchExtendedMnemonic<"ge", 4>;5250defm : BranchExtendedMnemonic<"nl", 4>;5251defm : BranchExtendedMnemonic<"le", 36>;5252defm : BranchExtendedMnemonic<"ng", 36>;5253defm : BranchExtendedMnemonic<"ne", 68>;5254defm : BranchExtendedMnemonic<"nu", 100>;5255defm : BranchExtendedMnemonic<"ns", 100>;5256 5257def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;5258def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;5259def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;5260def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;5261def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;5262def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;5263def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;5264def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;5265 5266def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;5267def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;5268def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;5269def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;5270def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;5271def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;5272def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;5273def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;5274 5275def : InstAlias<"trap", (TW 31, R0, R0)>;5276 5277multiclass TrapExtendedMnemonic<string name, int to> {5278 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;5279 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;5280 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;5281 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;5282}5283defm : TrapExtendedMnemonic<"lt", 16>;5284defm : TrapExtendedMnemonic<"le", 20>;5285defm : TrapExtendedMnemonic<"eq", 4>;5286defm : TrapExtendedMnemonic<"ge", 12>;5287defm : TrapExtendedMnemonic<"gt", 8>;5288defm : TrapExtendedMnemonic<"nl", 12>;5289defm : TrapExtendedMnemonic<"ne", 24>;5290defm : TrapExtendedMnemonic<"ng", 20>;5291defm : TrapExtendedMnemonic<"llt", 2>;5292defm : TrapExtendedMnemonic<"lle", 6>;5293defm : TrapExtendedMnemonic<"lge", 5>;5294defm : TrapExtendedMnemonic<"lgt", 1>;5295defm : TrapExtendedMnemonic<"lnl", 5>;5296defm : TrapExtendedMnemonic<"lng", 6>;5297defm : TrapExtendedMnemonic<"u", 31>;5298 5299// Atomic loads5300def : Pat<(i32 (atomic_load_azext_8 DForm:$src)), (LBZ memri:$src)>;5301def : Pat<(i32 (atomic_load_azext_16 DForm:$src)), (LHZ memri:$src)>;5302def : Pat<(i32 (atomic_load_nonext_32 DForm:$src)), (LWZ memri:$src)>;5303def : Pat<(i32 (atomic_load_azext_8 XForm:$src)), (LBZX memrr:$src)>;5304def : Pat<(i32 (atomic_load_azext_16 XForm:$src)), (LHZX memrr:$src)>;5305def : Pat<(i32 (atomic_load_nonext_32 XForm:$src)), (LWZX memrr:$src)>;5306 5307// Atomic stores5308def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>;5309def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>;5310def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>;5311def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>;5312def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>;5313def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>;5314 5315let Predicates = [IsISA3_0] in {5316 5317// Copy-Paste Facility5318// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to5319// PASTE for naming consistency.5320let mayLoad = 1 in5321def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>;5322 5323let mayStore = 1, Defs = [CR0] in5324def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm;5325 5326def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>;5327def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>;5328 5329// Message Synchronize5330def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;5331 5332// Power-Saving Mode Instruction:5333def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;5334 5335def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),5336 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64;5337} // IsISA3_05338 5339let Predicates = [IsISA3_0] in {5340def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)),5341 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>;5342}5343def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)),5344 (i32 (MULHW $a, $b))>;5345def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),5346 (i32 (MULHWU $a, $b))>;5347def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),5348 (i32 (CMPB $a, $b))>;5349 5350def : Pat<(int_ppc_load2r ForceXForm:$ptr),5351 (LHBRX ForceXForm:$ptr)>;5352def : Pat<(int_ppc_load4r ForceXForm:$ptr),5353 (LWBRX ForceXForm:$ptr)>;5354def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr),5355 (STHBRX gprc:$a, ForceXForm:$ptr)>;5356def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr),5357 (STWBRX gprc:$a, ForceXForm:$ptr)>;5358 5359// Fast 32-bit reverse bits algorithm:5360// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):5361// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);5362// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):5363// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC);5364// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):5365// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0);5366// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]):5367// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes):5368// n' = (n rotl 24); After which n' = [B4, B1, B2, B3]5369// Step 4.2: Insert B3 to the right position:5370// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3]5371// Step 4.3: Insert B1 to the right position:5372// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1]5373def MaskValues {5374 dag Lo1 = (ORI (LIS 0x5555), 0x5555);5375 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);5376 dag Lo2 = (ORI (LIS 0x3333), 0x3333);5377 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);5378 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);5379 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0);5380}5381 5382def Shift1 {5383 dag Right = (RLWINM $A, 31, 1, 31);5384 dag Left = (RLWINM $A, 1, 0, 30);5385}5386 5387def Swap1 {5388 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),5389 (AND Shift1.Left, MaskValues.Hi1));5390}5391 5392def Shift2 {5393 dag Right = (RLWINM Swap1.Bit, 30, 2, 31);5394 dag Left = (RLWINM Swap1.Bit, 2, 0, 29);5395}5396 5397def Swap2 {5398 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),5399 (AND Shift2.Left, MaskValues.Hi2));5400}5401 5402def Shift4 {5403 dag Right = (RLWINM Swap2.Bits, 28, 4, 31);5404 dag Left = (RLWINM Swap2.Bits, 4, 0, 27);5405}5406 5407def Swap4 {5408 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),5409 (AND Shift4.Left, MaskValues.Hi4));5410}5411 5412def Rotate {5413 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31);5414}5415 5416def RotateInsertByte3 {5417 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15);5418}5419 5420def RotateInsertByte1 {5421 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);5422}5423 5424// Clear the upper half of the register when in 64-bit mode5425let Predicates = [IsPPC64] in5426def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;5427let Predicates = [IsPPC32] in5428def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;5429 5430// Fast 64-bit reverse bits algorithm:5431// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):5432// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA);5433// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):5434// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC);5435// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):5436// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0);5437// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]):5438// Apply the same byte reverse algorithm mentioned above for the fast 32-bit5439// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And5440// then OR them together to get the final result.5441def MaskValues64 {5442 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32));5443 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));5444 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32));5445 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32));5446 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32));5447 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32));5448}5449 5450def DWMaskValues {5451 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555);5452 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);5453 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333);5454 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC);5455 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F);5456 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0);5457}5458 5459def DWSwapInByte {5460 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1),5461 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));5462 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2),5463 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2));5464 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4),5465 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4));5466}5467 5468// Intra-byte swap is done, now start inter-byte swap.5469def DWBytes4567 {5470 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32));5471}5472 5473def DWBytes7456 {5474 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31);5475}5476 5477def DWBytes7656 {5478 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15);5479}5480 5481// B7 B6 B5 B4 in the right order5482def DWBytes7654 {5483 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31);5484 dag DWord =5485 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32));5486}5487 5488def DWBytes0123 {5489 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32));5490}5491 5492def DWBytes3012 {5493 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31);5494}5495 5496def DWBytes3212 {5497 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15);5498}5499 5500// B3 B2 B1 B0 in the right order5501def DWBytes3210 {5502 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31);5503 dag DWord =5504 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32));5505}5506 5507// These instructions store a hash computed from the value of the link register5508// and the value of the stack pointer.5509let mayStore = 1 in {5510def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs),5511 (ins gprc:$RB, (memrihash $D, $RA):$addr),5512 "hashst $RB, $addr", IIC_IntGeneral, []>;5513def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs),5514 (ins gprc:$RB, (memrihash $D, $RA):$addr),5515 "hashstp $RB, $addr", IIC_IntGeneral, []>;5516}5517 5518// These instructions check a hash computed from the value of the link register5519// and the value of the stack pointer. The hasSideEffects flag is needed as the5520// instruction may TRAP if the hash does not match the hash stored at the5521// specified address.5522let mayLoad = 1, hasSideEffects = 1 in {5523def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs),5524 (ins gprc:$RB, (memrihash $D, $RA):$addr),5525 "hashchk $RB, $addr", IIC_IntGeneral, []>;5526def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs),5527 (ins gprc:$RB, (memrihash $D, $RA):$addr),5528 "hashchkp $RB, $addr", IIC_IntGeneral, []>;5529}5530 5531let Defs = [CR7], Itinerary = IIC_LdStSync in5532def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>;5533 5534// Now both high word and low word are reversed, next5535// swap the high word and low word.5536def : Pat<(i64 (bitreverse i64:$A)),5537 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;5538 5539def : Pat<(int_ppc_lwarx ForceXForm:$ptr),5540 (LWARX ForceXForm:$ptr)>;5541def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),5542 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5543def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4),5544 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5545def : Pat<(int_ppc_lbarx ForceXForm:$ptr),5546 (LBARX ForceXForm:$ptr)>;5547def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),5548 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5549def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1),5550 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5551 5552def : Pat<(int_ppc_fcfid f64:$A),5553 (XSCVSXDDP $A)>;5554def : Pat<(int_ppc_fcfud f64:$A),5555 (XSCVUXDDP $A)>;5556def : Pat<(int_ppc_fctid f64:$A),5557 (FCTID $A)>;5558def : Pat<(int_ppc_fctidz f64:$A),5559 (XSCVDPSXDS $A)>;5560def : Pat<(int_ppc_fctiw f64:$A),5561 (FCTIW $A)>;5562def : Pat<(int_ppc_fctiwz f64:$A),5563 (XSCVDPSXWS $A)>;5564def : Pat<(int_ppc_fctudz f64:$A),5565 (XSCVDPUXDS $A)>;5566def : Pat<(int_ppc_fctuwz f64:$A),5567 (XSCVDPUXWS $A)>;5568 5569def : Pat<(int_ppc_mfmsr), (MFMSR)>;5570def : Pat<(int_ppc_mftbu), (MFTB 269)>;5571def : Pat<(i32 (int_ppc_mfspr timm:$SPR)),5572 (MFSPR $SPR)>;5573def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT),5574 (MTSPR $SPR, $RT)>;5575def : Pat<(int_ppc_mtmsr gprc:$RS),5576 (MTMSR $RS, 0)>;5577 5578let Predicates = [IsISA2_07] in {5579 def : Pat<(int_ppc_lharx ForceXForm:$ptr),5580 (LHARX ForceXForm:$ptr)>;5581 5582 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A),5583 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5584 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2),5585 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;5586}5587def : Pat<(int_ppc_dcbtstt ForceXForm:$dst),5588 (DCBTST 16, ForceXForm:$dst)>;5589def : Pat<(int_ppc_dcbtt ForceXForm:$dst),5590 (DCBT 16, ForceXForm:$dst)>;5591 5592def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),5593 (STFIWX f64:$XT, ForceXForm:$dst)>;5594