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1 2// Multiclass definitions for MMA accumulator instructions.3// ----------------------------------------------------------------------------4 5// Defines 2 unmasked instructions where the xo field for acc/non-acc version6// is even/odd.7multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,8 string asmstr> {9 let Predicates = [MMA, IsNotISAFuture] in {10 def NAME :11 XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL,12 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,13 RegConstraint<"@earlyclobber $AT">;14 def PP :15 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL),16 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,17 RegConstraint<"$ATi = $AT">;18 }19 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {20 def NAME#W :21 XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs wacc:$AT), IOL,22 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,23 RegConstraint<"@earlyclobber $AT">;24 def WPP :25 XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), !con((ins wacc:$ATi), IOL),26 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,27 RegConstraint<"$ATi = $AT">;28 }29}30 31// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits.32// The XO field for acc/non-acc version is even/odd.33multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,34 string asmstr> {35 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;36 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {37 def PM#NAME :38 MMIRR_XX3Form_XY4P8_XAB6<39 opcode, !or(xo, 0x01), (outs acc:$AT),40 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),41 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),42 IIC_VecFP, []>,43 RegConstraint<"@earlyclobber $AT">;44 def PM#NAME#PP :45 MMIRR_XX3Form_XY4P8_XAB6<46 opcode, xo, (outs acc:$AT),47 !con((ins acc:$ATi),48 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),49 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),50 IIC_VecFP, []>,51 RegConstraint<"$ATi = $AT">;52 }53 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {54 def PM#NAME#W :55 MMIRR_XX3Form_XY4P8_XAB6<56 opcode, !or(xo, 0x01), (outs wacc:$AT),57 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),58 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),59 IIC_VecFP, []>,60 RegConstraint<"@earlyclobber $AT">;61 def PM#NAME#WPP :62 MMIRR_XX3Form_XY4P8_XAB6<63 opcode, xo, (outs wacc:$AT),64 !con((ins wacc:$ATi),65 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),66 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),67 IIC_VecFP, []>,68 RegConstraint<"$ATi = $AT">;69 }70}71 72// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits.73// The XO field for acc/non-acc version is even/odd.74multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,75 string asmstr> {76 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;77 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {78 def PM#NAME :79 MMIRR_XX3Form_XYP4_XAB6<80 opcode, !or(xo, 0x01), (outs acc:$AT),81 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),82 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),83 IIC_VecFP, []>,84 RegConstraint<"@earlyclobber $AT">;85 def PM#NAME#PP :86 MMIRR_XX3Form_XYP4_XAB6<87 opcode, xo, (outs acc:$AT),88 !con((ins acc:$ATi),89 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),90 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),91 IIC_VecFP, []>,92 RegConstraint<"$ATi = $AT">;93 }94 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {95 def PM#NAME#W :96 MMIRR_XX3Form_XYP4_XAB6<97 opcode, !or(xo, 0x01), (outs wacc:$AT),98 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),99 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),100 IIC_VecFP, []>,101 RegConstraint<"@earlyclobber $AT">;102 def PM#NAME#WPP :103 MMIRR_XX3Form_XYP4_XAB6<104 opcode, xo, (outs wacc:$AT),105 !con((ins wacc:$ATi),106 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),107 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),108 IIC_VecFP, []>,109 RegConstraint<"$ATi = $AT">;110 }111}112 113// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.114// The XO field for acc/non-acc version is even/odd.115multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,116 string asmstr> {117 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;118 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {119 def PM#NAME :120 MMIRR_XX3Form_XY4P2_XAB6<121 opcode, !or(xo, 0x01), (outs acc:$AT),122 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),123 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),124 IIC_VecFP, []>,125 RegConstraint<"@earlyclobber $AT">;126 def PM#NAME#PP :127 MMIRR_XX3Form_XY4P2_XAB6<128 opcode, xo, (outs acc:$AT),129 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),130 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),131 IIC_VecFP, []>,132 RegConstraint<"$ATi = $AT">;133 }134 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {135 def PM#NAME#W :136 MMIRR_XX3Form_XY4P2_XAB6<137 opcode, !or(xo, 0x01), (outs wacc:$AT),138 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),139 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),140 IIC_VecFP, []>,141 RegConstraint<"@earlyclobber $AT">;142 def PM#NAME#WPP :143 MMIRR_XX3Form_XY4P2_XAB6<144 opcode, xo, (outs wacc:$AT),145 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),146 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),147 IIC_VecFP, []>,148 RegConstraint<"$ATi = $AT">;149 }150}151 152// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.153// Upper nibble of XO field for acc/non-acc version is 0x4/0x6.154multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,155 string asmstr> {156 let Predicates = [MMA, IsNotISAFuture] in {157 def NAME :158 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL,159 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,160 RegConstraint<"@earlyclobber $AT">;161 def PP :162 XX3Form_AT3_XAB6<163 opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL),164 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,165 RegConstraint<"$ATi = $AT">;166 }167 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {168 def PM#NAME :169 MMIRR_XX3Form_XY4P2_XAB6<170 opcode, xo, (outs acc:$AT),171 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),172 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),173 IIC_VecFP, []>,174 RegConstraint<"@earlyclobber $AT">;175 def PM#NAME#PP :176 MMIRR_XX3Form_XY4P2_XAB6<177 opcode, !or(xo, 0x20), (outs acc:$AT),178 !con((ins acc:$ATi),179 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),180 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),181 IIC_VecFP, []>,182 RegConstraint<"$ATi = $AT">;183 }184 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {185 def NAME#W :186 XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), IOL,187 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,188 RegConstraint<"@earlyclobber $AT">;189 def WPP :190 XX3Form_AT3_XAB6<191 opcode, !or(xo, 0x20), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),192 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,193 RegConstraint<"$ATi = $AT">;194 }195 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {196 def PM#NAME#W :197 MMIRR_XX3Form_XY4P2_XAB6<198 opcode, xo, (outs wacc:$AT),199 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),200 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),201 IIC_VecFP, []>,202 RegConstraint<"@earlyclobber $AT">;203 def PM#NAME#WPP :204 MMIRR_XX3Form_XY4P2_XAB6<205 opcode, !or(xo, 0x20), (outs wacc:$AT),206 !con((ins wacc:$ATi),207 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),208 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),209 IIC_VecFP, []>,210 RegConstraint<"$ATi = $AT">;211 }212}213 214// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4215// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.216multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,217 string asmbase, string asmstr> {218 defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>;219 let Predicates = [MMA, IsNotISAFuture] in {220 def PN : XX3Form_AT3_XAB6<221 opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),222 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,223 RegConstraint<"$ATi = $AT">;224 def NP : XX3Form_AT3_XAB6<225 opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL),226 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,227 RegConstraint<"$ATi = $AT">;228 def NN : XX3Form_AT3_XAB6<229 opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL),230 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,231 RegConstraint<"$ATi = $AT">;232 }233 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {234 def WPN : XX3Form_AT3_XAB6<235 opcode, !or(xo, 0x80), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),236 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,237 RegConstraint<"$ATi = $AT">;238 def WNP : XX3Form_AT3_XAB6<239 opcode, !or(xo, 0x40), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),240 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,241 RegConstraint<"$ATi = $AT">;242 def WNN : XX3Form_AT3_XAB6<243 opcode, !or(xo, 0xC0), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),244 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,245 RegConstraint<"$ATi = $AT">;246 }247 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {248 def PM#NAME#PN :249 MMIRR_XX3Form_XY4P2_XAB6<250 opcode, !or(xo, 0x80), (outs acc:$AT),251 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),252 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),253 IIC_VecFP, []>,254 RegConstraint<"$ATi = $AT">;255 def PM#NAME#NP :256 MMIRR_XX3Form_XY4P2_XAB6<257 opcode, !or(xo, 0x40), (outs acc:$AT),258 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),259 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),260 IIC_VecFP, []>,261 RegConstraint<"$ATi = $AT">;262 def PM#NAME#NN :263 MMIRR_XX3Form_XY4P2_XAB6<264 opcode, !or(xo, 0xC0), (outs acc:$AT),265 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),266 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),267 IIC_VecFP, []>,268 RegConstraint<"$ATi = $AT">;269 }270 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {271 def PM#NAME#WPN :272 MMIRR_XX3Form_XY4P2_XAB6<273 opcode, !or(xo, 0x80), (outs wacc:$AT),274 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),275 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),276 IIC_VecFP, []>,277 RegConstraint<"$ATi = $AT">;278 def PM#NAME#WNP :279 MMIRR_XX3Form_XY4P2_XAB6<280 opcode, !or(xo, 0x40), (outs wacc:$AT),281 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),282 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),283 IIC_VecFP, []>,284 RegConstraint<"$ATi = $AT">;285 def PM#NAME#WNN :286 MMIRR_XX3Form_XY4P2_XAB6<287 opcode, !or(xo, 0xC0), (outs wacc:$AT),288 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),289 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),290 IIC_VecFP, []>,291 RegConstraint<"$ATi = $AT">;292 }293}294 295// Defines 5 instructions, unmasked, operand negating.296// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.297multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,298 string asmbase, string asmstr> {299 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;300 let Predicates = [MMA, IsNotISAFuture] in {301 def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),302 !con((ins acc:$ATi), IOL),303 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,304 RegConstraint<"$ATi = $AT">;305 def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT),306 !con((ins acc:$ATi), IOL),307 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,308 RegConstraint<"$ATi = $AT">;309 def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT),310 !con((ins acc:$ATi), IOL),311 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,312 RegConstraint<"$ATi = $AT">;313 }314 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {315 def WPN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs wacc:$AT),316 !con((ins wacc:$ATi), IOL),317 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,318 RegConstraint<"$ATi = $AT">;319 def WNP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs wacc:$AT),320 !con((ins wacc:$ATi), IOL),321 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,322 RegConstraint<"$ATi = $AT">;323 def WNN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs wacc:$AT),324 !con((ins wacc:$ATi), IOL),325 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,326 RegConstraint<"$ATi = $AT">;327 }328}329 330// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits.331// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.332multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,333 string asmbase, string asmstr> {334 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;335 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {336 def PM#NAME :337 MMIRR_XX3Form_XY4_XAB6<338 opcode, !or(xo, 0x01), (outs acc:$AT),339 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),340 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),341 IIC_VecFP, []>,342 RegConstraint<"@earlyclobber $AT">;343 def PM#NAME#PP :344 MMIRR_XX3Form_XY4_XAB6<345 opcode, xo, (outs acc:$AT),346 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),347 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),348 IIC_VecFP, []>,349 RegConstraint<"$ATi = $AT">;350 def PM#NAME#PN :351 MMIRR_XX3Form_XY4_XAB6<352 opcode, !or(xo, 0x80), (outs acc:$AT),353 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),354 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),355 IIC_VecFP, []>,356 RegConstraint<"$ATi = $AT">;357 def PM#NAME#NP :358 MMIRR_XX3Form_XY4_XAB6<359 opcode, !or(xo, 0x40), (outs acc:$AT),360 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),361 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),362 IIC_VecFP, []>,363 RegConstraint<"$ATi = $AT">;364 def PM#NAME#NN :365 MMIRR_XX3Form_XY4_XAB6<366 opcode, !or(xo, 0xC0), (outs acc:$AT),367 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),368 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),369 IIC_VecFP, []>,370 RegConstraint<"$ATi = $AT">;371 }372 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {373 def PM#NAME#W :374 MMIRR_XX3Form_XY4_XAB6<375 opcode, !or(xo, 0x01), (outs wacc:$AT),376 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),377 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),378 IIC_VecFP, []>,379 RegConstraint<"@earlyclobber $AT">;380 def PM#NAME#WPP :381 MMIRR_XX3Form_XY4_XAB6<382 opcode, xo, (outs wacc:$AT),383 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),384 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),385 IIC_VecFP, []>,386 RegConstraint<"$ATi = $AT">;387 def PM#NAME#WPN :388 MMIRR_XX3Form_XY4_XAB6<389 opcode, !or(xo, 0x80), (outs wacc:$AT),390 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),391 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),392 IIC_VecFP, []>,393 RegConstraint<"$ATi = $AT">;394 def PM#NAME#WNP :395 MMIRR_XX3Form_XY4_XAB6<396 opcode, !or(xo, 0x40), (outs wacc:$AT),397 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),398 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),399 IIC_VecFP, []>,400 RegConstraint<"$ATi = $AT">;401 def PM#NAME#WNN :402 MMIRR_XX3Form_XY4_XAB6<403 opcode, !or(xo, 0xC0), (outs wacc:$AT),404 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),405 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),406 IIC_VecFP, []>,407 RegConstraint<"$ATi = $AT">;408 }409}410 411// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits.412// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.413multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,414 string asmbase, string asmstr> {415 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;416 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {417 def PM#NAME :418 MMIRR_XX3Form_X4Y2_XAB6<419 opcode, !or(xo, 0x01), (outs acc:$AT),420 !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),421 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),422 IIC_VecFP, []>,423 RegConstraint<"@earlyclobber $AT">;424 def PM#NAME#PP :425 MMIRR_XX3Form_X4Y2_XAB6<426 opcode, xo, (outs acc:$AT),427 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),428 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),429 IIC_VecFP, []>,430 RegConstraint<"$ATi = $AT">;431 def PM#NAME#PN :432 MMIRR_XX3Form_X4Y2_XAB6<433 opcode, !or(xo, 0x80), (outs acc:$AT),434 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),435 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),436 IIC_VecFP, []>,437 RegConstraint<"$ATi = $AT">;438 def PM#NAME#NP :439 MMIRR_XX3Form_X4Y2_XAB6<440 opcode, !or(xo, 0x40), (outs acc:$AT),441 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),442 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),443 IIC_VecFP, []>,444 RegConstraint<"$ATi = $AT">;445 def PM#NAME#NN :446 MMIRR_XX3Form_X4Y2_XAB6<447 opcode, !or(xo, 0xC0), (outs acc:$AT),448 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),449 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),450 IIC_VecFP, []>,451 RegConstraint<"$ATi = $AT">;452 }453 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {454 def PM#NAME#W :455 MMIRR_XX3Form_X4Y2_XAB6<456 opcode, !or(xo, 0x01), (outs wacc:$AT),457 !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),458 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),459 IIC_VecFP, []>,460 RegConstraint<"@earlyclobber $AT">;461 def PM#NAME#WPP :462 MMIRR_XX3Form_X4Y2_XAB6<463 opcode, xo, (outs wacc:$AT),464 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),465 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),466 IIC_VecFP, []>,467 RegConstraint<"$ATi = $AT">;468 def PM#NAME#WPN :469 MMIRR_XX3Form_X4Y2_XAB6<470 opcode, !or(xo, 0x80), (outs wacc:$AT),471 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),472 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),473 IIC_VecFP, []>,474 RegConstraint<"$ATi = $AT">;475 def PM#NAME#WNP :476 MMIRR_XX3Form_X4Y2_XAB6<477 opcode, !or(xo, 0x40), (outs wacc:$AT),478 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),479 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),480 IIC_VecFP, []>,481 RegConstraint<"$ATi = $AT">;482 def PM#NAME#WNN :483 MMIRR_XX3Form_X4Y2_XAB6<484 opcode, !or(xo, 0xC0), (outs wacc:$AT),485 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),486 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),487 IIC_VecFP, []>,488 RegConstraint<"$ATi = $AT">;489 }490}491 492// End of class definitions.493//-----------------------------------------------------------------------------494 495let Predicates = [MMA, IsNotISAFuture] in {496 def XXMFACC :497 XForm_AT3<31, 0, 177, (outs acc:$ATo), (ins acc:$AT), "xxmfacc $AT",498 IIC_VecGeneral,499 [(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>,500 RegConstraint<"$ATo = $AT">;501 def XXMTACC :502 XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT",503 IIC_VecGeneral,504 [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,505 RegConstraint<"$ATi = $AT">;506 def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp),507 "#KILL_PAIR", []>,508 RegConstraint<"$XTp = $XSp">;509 def BUILD_UACC : PPCPostRAExpPseudo<(outs acc:$AT), (ins uacc:$AS),510 "#BUILD_UACC $AT, $AS", []>;511 // We define XXSETACCZ as rematerializable to undo CSE of that intrinsic in512 // the backend. We avoid CSE here because it generates a copy of the acc513 // register and this copy is more expensive than calling the intrinsic again.514 let isAsCheapAsAMove = 1, isReMaterializable = 1 in {515 def XXSETACCZ :516 XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT", IIC_VecGeneral,517 [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;518 }519 def XVI8GER4SPP :520 XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB),521 "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,522 RegConstraint<"$ATi = $AT">;523 let mayStore = 1 in {524 def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst),525 "#SPILL_ACC", []>;526 def SPILL_UACC: PPCEmitTimePseudo<(outs), (ins uacc:$AT, memrix16:$dst),527 "#SPILL_UACC", []>;528 }529 let mayLoad = 1, hasSideEffects = 0 in {530 def RESTORE_ACC: PPCEmitTimePseudo<(outs acc:$AT), (ins memrix16:$src),531 "#RESTORE_ACC", []>;532 def RESTORE_UACC: PPCEmitTimePseudo<(outs uacc:$AT), (ins memrix16:$src),533 "#RESTORE_UACC", []>;534 }535}536 537let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {538 // For Future and up XXMFACCW and XXMTACCW will not have patterns.539 // On Future CPU the wacc registers no longer overlap with the vsr registers540 // and so register allocation would have to know to match 4 vsr registers541 // with one wacc register.542 // On top of that Future CPU has a more convenient way to move between vsrs543 // and wacc registers using xxextfdmr512 and xxinstdmr512.544 def XXMFACCW :545 XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "xxmfacc $AT",546 IIC_VecGeneral, []>,547 RegConstraint<"$ATo = $AT">;548 def XXMTACCW :549 XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT",550 IIC_VecGeneral, []>,551 RegConstraint<"$ATi = $AT">;552 553 let isAsCheapAsAMove = 1, isReMaterializable = 1 in {554 def DMXXSETACCZ :555 XForm_AT3<31, 3, 177, (outs wacc:$AT), (ins), "dmxxsetaccz $AT",556 IIC_VecGeneral, [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;557 }558 559 def XVI8GER4WSPP :560 XX3Form_AT3_XAB6<59, 99, (outs wacc:$AT),561 (ins wacc:$ATi, vsrc:$XA, vsrc:$XB),562 "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,563 RegConstraint<"$ATi = $AT">;564 565 let mayStore = 1 in {566 def SPILL_WACC: PPCEmitTimePseudo<(outs), (ins wacc:$AT, memrix16:$dst),567 "#SPILL_WACC", []>;568 def SPILL_DMRP: PPCEmitTimePseudo<(outs), (ins dmrp:$AT, memrix16:$dst),569 "#SPILL_DMRP", []>;570 def SPILL_DMR: PPCEmitTimePseudo<(outs), (ins dmr:$AT, memrix16:$dst),571 "#SPILL_DMR", []>;572 }573 let mayLoad = 1, hasSideEffects = 0 in {574 def RESTORE_WACC: PPCEmitTimePseudo<(outs wacc:$AT), (ins memrix16:$src),575 "#RESTORE_WACC", []>;576 def RESTORE_DMRP: PPCEmitTimePseudo<(outs dmrp:$AT), (ins memrix16:$src),577 "#RESTORE_DMRP", []>;578 def RESTORE_DMR: PPCEmitTimePseudo<(outs dmr:$AT), (ins memrix16:$src),579 "#RESTORE_DMR", []>;580 }581}582 583let Predicates = [MMA, IsISAFuture] in {584 def : InstAlias<"dmxxmmfacc $AT ", (XXMFACC acc:$AT)>;585 def : InstAlias<"dmxxmmtacc $AT ", (XXMTACC acc:$AT)>;586 def : InstAlias<"dmxxsetaccz $AT ", (XXSETACCZ acc:$AT)>;587}588 589let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {590 def PMXVI8GER4SPP :591 MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT),592 (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,593 u4imm:$YMSK, u4imm:$PMSK),594 "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",595 IIC_VecGeneral, []>,596 RegConstraint<"$ATi = $AT">;597}598 599let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {600 def PMXVI8GER4WSPP :601 MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs wacc:$AT),602 (ins wacc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,603 u4imm:$YMSK, u4imm:$PMSK),604 "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",605 IIC_VecGeneral, []>,606 RegConstraint<"$ATi = $AT">;607}608 609// MMA accumulating/non-accumulating instructions.610//------------------------------------------------------------------------------611 612// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN613// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN614defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB),615 "xvbf16ger2", "$AT, $XA, $XB">;616 617// XVI4GER8, XVI4GER8PP, PMXVI4GER8, PMXVI4GER8PP618defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB),619 "xvi4ger8", "$AT, $XA, $XB">;620 621// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP622defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB),623 "xvi8ger4", "$AT, $XA, $XB">;624 625// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP626defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB),627 "xvi16ger2", "$AT, $XA, $XB">;628 629// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP630defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB),631 "xvi16ger2s", "$AT, $XA, $XB">;632 633// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN634// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN635defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB),636 "xvf16ger2", "$AT, $XA, $XB">;637 638// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP639// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP640defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB),641 "xvf32ger", "$AT, $XA, $XB">;642 643// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN644// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN645defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB),646 "xvf64ger", "$AT, $XA, $XB">;647//------------------------------------------------------------------------------648 649// MMA Intrinsics650let Predicates = [MMA, IsNotISAFuture] in {651 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),652 (XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>;653 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),654 (XVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;655 656 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),657 (XVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC)>;658 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),659 (XVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;660 661 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),662 (XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>;663 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),664 (XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;665}666 667let Predicates = [MMA, IsISAFuture] in {668 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),669 (XVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC)>;670 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),671 (XVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;672 673 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),674 (XVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC)>;675 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),676 (XVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;677 678 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),679 (XVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC)>;680 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),681 (XVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;682}683 684let Predicates = [MMA, IsNotISAFuture] in {685 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),686 (XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;687 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),688 (XVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;689 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),690 (XVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;691 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),692 (XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;693 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),694 (XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;695}696 697let Predicates = [MMA, IsISAFuture] in {698 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),699 (XVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;700 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),701 (XVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;702 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),703 (XVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;704 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),705 (XVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;706 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),707 (XVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;708}709 710let Predicates = [MMA, IsNotISAFuture] in {711 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),712 (XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>;713 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),714 (XVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;715 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),716 (XVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;717 def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),718 (XVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;719 def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),720 (XVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;721 def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)),722 (XVF64GER $XA, RCCp.BToVSRC)>;723 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),724 (XVF64GERPP $ATi, $XA, RCCp.BToVSRC)>;725 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),726 (XVF64GERPN $ATi, $XA, RCCp.BToVSRC)>;727 def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),728 (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>;729 def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),730 (XVF64GERNN $ATi, $XA, RCCp.BToVSRC)>;731 732 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),733 (XVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;734 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),735 (XVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;736 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),737 (XVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;738 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),739 (XVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;740 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),741 (XVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;742 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),743 (XVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;744 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),745 (XVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;746 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),747 (XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;748}749 750let Predicates = [MMA, IsISAFuture] in {751 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),752 (XVF32GERW RCCp.AToVSRC, RCCp.BToVSRC)>;753 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),754 (XVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;755 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),756 (XVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;757 def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),758 (XVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;759 def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),760 (XVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;761 def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)),762 (XVF64GERW $XA, RCCp.BToVSRC)>;763 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),764 (XVF64GERWPP $ATi, $XA, RCCp.BToVSRC)>;765 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),766 (XVF64GERWPN $ATi, $XA, RCCp.BToVSRC)>;767 def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),768 (XVF64GERWNP $ATi, $XA, RCCp.BToVSRC)>;769 def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),770 (XVF64GERWNN $ATi, $XA, RCCp.BToVSRC)>;771 772 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),773 (XVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;774 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),775 (XVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;776 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),777 (XVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;778 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),779 (XVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;780 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),781 (XVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;782 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),783 (XVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>;784 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),785 (XVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;786 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),787 (XVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;788}789// MMA Intrinsics790 791let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {792 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,793 Msk4Imm:$YMSK, Msk8Imm:$PMSK)),794 (PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,795 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;796 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,797 Msk4Imm:$XMSK, Msk4Imm:$YMSK,798 Msk8Imm:$PMSK)),799 (PMXVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,800 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;801 802 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,803 Msk4Imm:$YMSK, Msk4Imm:$PMSK)),804 (PMXVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,805 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;806 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,807 Msk4Imm:$XMSK, Msk4Imm:$YMSK,808 Msk4Imm:$PMSK)),809 (PMXVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,810 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;811 812 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,813 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),814 (PMXVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,815 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;816 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,817 Msk4Imm:$XMSK, Msk4Imm:$YMSK,818 Msk2Imm:$PMSK)),819 (PMXVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,820 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;821 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,822 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),823 (PMXVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,824 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;825 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,826 Msk4Imm:$XMSK, Msk4Imm:$YMSK,827 Msk2Imm:$PMSK)),828 (PMXVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,829 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;830 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,831 Msk4Imm:$XMSK, Msk4Imm:$YMSK,832 Msk2Imm:$PMSK)),833 (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,834 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;835 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,836 Msk4Imm:$XMSK, Msk4Imm:$YMSK,837 Msk2Imm:$PMSK)),838 (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,839 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;840 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,841 Msk4Imm:$XMSK, Msk4Imm:$YMSK,842 Msk2Imm:$PMSK)),843 (PMXVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,844 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;845 846 def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,847 Msk4Imm:$YMSK)),848 (PMXVF32GER RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,849 Msk4Imm:$YMSK)>;850 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB,851 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),852 (PMXVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,853 Msk4Imm:$YMSK)>;854 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB,855 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),856 (PMXVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,857 Msk4Imm:$YMSK)>;858 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB,859 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),860 (PMXVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,861 Msk4Imm:$YMSK)>;862 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB,863 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),864 (PMXVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,865 Msk4Imm:$YMSK)>;866 867 def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK,868 Msk2Imm:$YMSK)),869 (PMXVF64GER $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>;870 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB,871 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),872 (PMXVF64GERPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,873 Msk2Imm:$YMSK)>;874 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB,875 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),876 (PMXVF64GERPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,877 Msk2Imm:$YMSK)>;878 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB,879 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),880 (PMXVF64GERNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,881 Msk2Imm:$YMSK)>;882 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB,883 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),884 (PMXVF64GERNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,885 Msk2Imm:$YMSK)>;886 887 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,888 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),889 (PMXVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,890 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;891 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,892 Msk4Imm:$XMSK, Msk4Imm:$YMSK,893 Msk2Imm:$PMSK)),894 (PMXVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,895 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;896 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,897 Msk4Imm:$XMSK, Msk4Imm:$YMSK,898 Msk2Imm:$PMSK)),899 (PMXVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,900 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;901 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,902 Msk4Imm:$XMSK, Msk4Imm:$YMSK,903 Msk2Imm:$PMSK)),904 (PMXVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,905 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;906 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,907 Msk4Imm:$XMSK, Msk4Imm:$YMSK,908 Msk2Imm:$PMSK)),909 (PMXVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,910 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;911 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,912 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),913 (PMXVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,914 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;915 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,916 Msk4Imm:$XMSK, Msk4Imm:$YMSK,917 Msk2Imm:$PMSK)),918 (PMXVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,919 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;920 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,921 Msk4Imm:$XMSK, Msk4Imm:$YMSK,922 Msk2Imm:$PMSK)),923 (PMXVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,924 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;925}926 927let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {928 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,929 Msk4Imm:$YMSK, Msk8Imm:$PMSK)),930 (PMXVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,931 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;932 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,933 Msk4Imm:$XMSK, Msk4Imm:$YMSK,934 Msk8Imm:$PMSK)),935 (PMXVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,936 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;937 938 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,939 Msk4Imm:$YMSK, Msk4Imm:$PMSK)),940 (PMXVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,941 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;942 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,943 Msk4Imm:$XMSK, Msk4Imm:$YMSK,944 Msk4Imm:$PMSK)),945 (PMXVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,946 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;947 948 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,949 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),950 (PMXVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,951 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;952 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,953 Msk4Imm:$XMSK, Msk4Imm:$YMSK,954 Msk2Imm:$PMSK)),955 (PMXVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,956 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;957 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,958 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),959 (PMXVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,960 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;961 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,962 Msk4Imm:$XMSK, Msk4Imm:$YMSK,963 Msk2Imm:$PMSK)),964 (PMXVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,965 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;966 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,967 Msk4Imm:$XMSK, Msk4Imm:$YMSK,968 Msk2Imm:$PMSK)),969 (PMXVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,970 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;971 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,972 Msk4Imm:$XMSK, Msk4Imm:$YMSK,973 Msk2Imm:$PMSK)),974 (PMXVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,975 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;976 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,977 Msk4Imm:$XMSK, Msk4Imm:$YMSK,978 Msk2Imm:$PMSK)),979 (PMXVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,980 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;981 982 def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,983 Msk4Imm:$YMSK)),984 (PMXVF32GERW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,985 Msk4Imm:$YMSK)>;986 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB,987 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),988 (PMXVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,989 Msk4Imm:$YMSK)>;990 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB,991 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),992 (PMXVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,993 Msk4Imm:$YMSK)>;994 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB,995 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),996 (PMXVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,997 Msk4Imm:$YMSK)>;998 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB,999 Msk4Imm:$XMSK, Msk4Imm:$YMSK)),1000 (PMXVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1001 Msk4Imm:$YMSK)>;1002 1003 def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK,1004 Msk2Imm:$YMSK)),1005 (PMXVF64GERW $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>;1006 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB,1007 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),1008 (PMXVF64GERWPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,1009 Msk2Imm:$YMSK)>;1010 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB,1011 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),1012 (PMXVF64GERWPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,1013 Msk2Imm:$YMSK)>;1014 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB,1015 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),1016 (PMXVF64GERWNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,1017 Msk2Imm:$YMSK)>;1018 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB,1019 Msk4Imm:$XMSK, Msk2Imm:$YMSK)),1020 (PMXVF64GERWNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,1021 Msk2Imm:$YMSK)>;1022 1023 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,1024 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),1025 (PMXVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1026 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1027 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,1028 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1029 Msk2Imm:$PMSK)),1030 (PMXVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1031 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1032 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,1033 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1034 Msk2Imm:$PMSK)),1035 (PMXVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1036 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1037 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,1038 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1039 Msk2Imm:$PMSK)),1040 (PMXVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1041 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1042 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,1043 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1044 Msk2Imm:$PMSK)),1045 (PMXVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1046 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1047 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,1048 Msk4Imm:$YMSK, Msk2Imm:$PMSK)),1049 (PMXVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1050 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1051 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,1052 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1053 Msk2Imm:$PMSK)),1054 (PMXVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1055 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1056 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,1057 Msk4Imm:$XMSK, Msk4Imm:$YMSK,1058 Msk2Imm:$PMSK)),1059 (PMXVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,1060 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;1061}1062 1063def ConcatsMMA {1064 dag VecsToVecPair0 =1065 (v256i1 (INSERT_SUBREG1066 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),1067 $vs1, sub_vsx0));1068 dag VecsToVecPair1 =1069 (v256i1 (INSERT_SUBREG1070 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),1071 $vs3, sub_vsx0));1072 dag VecsToVecQuad = (BUILD_UACC1073 (v512i1 (REG_SEQUENCE UACCRC,1074 (KILL_PAIR VecsToVecPair0), sub_pair0,1075 (KILL_PAIR VecsToVecPair1), sub_pair1)));1076}1077 1078def Extracts {1079 dag Pair0 = (v256i1 (EXTRACT_SUBREG $v, sub_pair0));1080 dag Pair1 = (v256i1 (EXTRACT_SUBREG $v, sub_pair1));1081 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));1082 dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1));1083 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));1084 dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1));1085}1086 1087let Predicates = [MMA, IsNotISAFuture] in {1088 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),1089 (XXMTACC ConcatsMMA.VecsToVecQuad)>;1090 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,1091 v16i8:$vs3, v16i8:$vs2)),1092 (XXMTACC ConcatsMMA.VecsToVecQuad)>;1093 def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;1094 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 0)),1095 Extracts.Vec0>;1096 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 1)),1097 Extracts.Vec1>;1098 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 2)),1099 Extracts.Vec2>;1100 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 3)),1101 Extracts.Vec3>;1102}1103 1104let Predicates = [MMA, IsISAFuture] in {1105 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),1106 (DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;1107 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,1108 v16i8:$vs3, v16i8:$vs2)),1109 (DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;1110 def : Pat<(v512i1 immAllZerosV), (DMXXSETACCZ)>;1111}1112