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1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file describes the instructions introduced for the Power10 CPU.12//13//===----------------------------------------------------------------------===//14 15//===----------------------------------------------------------------------===//16// Naming convention for future instruction formats17//18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+19//20// Where:21// <INSTR_FORM> - name of instruction format as per the ISA22// (X-Form, VX-Form, etc.)23// <OP_TYPE> - operand type24// * FRT/RT/VT/XT/BT - target register25// (FPR, GPR, VR, VSR, CR-bit respectively)26// In some situations, the 'T' is replaced by27// 'D' when describing the target register.28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.)29// * IMM - immediate (where signedness matters,30// this is SI/UI for signed/unsigned)31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp)32// * R - PC-Relative bit33// (denotes that the address is computed pc-relative)34// * VRM - Masked Registers35// * AT - target accumulator36// * N - the Nth bit in a VSR37// * Additional 1-bit operands may be required for certain38// instruction formats such as: MC, P, MP39// * X / Y / P - mask values. In the instruction encoding, this is40// represented as XMSK, YMSK and PMSK.41// * MEM - indicates if the instruction format requires any memory42// accesses. This does not have <OP_LENGTH> attached to it.43// <OP_LENGTH> - the length of each operand in bits.44// For operands that are 1 bit, the '1' is omitted from the name.45//46// Example: 8RR_XX4Form_IMM8_XTAB647// 8RR_XX4Form is the instruction format.48// The operand is an 8-bit immediate (IMM), the destination (XT)49// and sources (XA, XB) that are all 6-bits. The destination and50// source registers are combined if they are of the same length.51// Moreover, the order of operands reflects the order of operands52// in the encoding.53 54//===----------------------------------------------------------------------===//55// PowerPC ISA 3.1 specific type constraints.56//57 58def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,59 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3>60]>;61def SDT_PPCAccBuild : SDTypeProfile<1, 4, [62 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,63 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>64]>;65def SDT_PPCPairBuild : SDTypeProfile<1, 2, [66 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>67]>;68def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [69 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>70]>;71def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [72 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>73]>;74def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [75 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>76]>;77 78def SDT_PPCsetbc : SDTypeProfile<1, 1, [79 SDTCisInt<0>, SDTCisInt<1>80]>;81 82//===----------------------------------------------------------------------===//83// ISA 3.1 specific PPCISD nodes.84//85 86// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.87def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;88 89// ACC_BUILD = Build an accumulator register from 4 VSX registers.90def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>;91 92// PAIR_BUILD = Build a vector pair register from 2 VSX registers.93def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>;94 95// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of96// an accumulator or pair register. This node is needed because97// EXTRACT_SUBVECTOR expects the input and output vectors to have the same98// element type.99def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx,100 []>;101def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx,102 []>;103 104// XXMFACC = This corresponds to the xxmfacc instruction.105def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>;106 107// SETBC - The ISA 3.1 (P10) SETBC instruction.108def PPCsetbc : SDNode<"PPCISD::SETBC", SDT_PPCsetbc, []>;109 110// SETBCR - The ISA 3.1 (P10) SETBCR instruction.111def PPCsetbcr : SDNode<"PPCISD::SETBCR", SDT_PPCsetbc, []>;112 113//===----------------------------------------------------------------------===//114 115// PC Relative flag (for instructions that use the address of the prefix for116// address computations).117class isPCRel { bit PCRel = 1; }118 119// PowerPC specific type constraints.120def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [121 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>122]>;123 124// LXVRZX - Load VSX Vector Rightmost and Zero Extend125// This node represents v1i128 BUILD_VECTOR of a zero extending load126// instruction from <byte, halfword, word, or doubleword> to i128.127// Allows utilization of the Load VSX Vector Rightmost Instructions.128def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;130 131// Top-level class for prefixed instructions.132class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,133 InstrItinClass itin> : Instruction {134 field bits<64> Inst;135 bit PCRel = 0; // Default value, set by isPCRel.136 let Size = 8;137 138 let Namespace = "PPC";139 let OutOperandList = OOL;140 let InOperandList = IOL;141 let AsmString = asmstr;142 let Itinerary = itin;143 let Inst{0...5} = pref;144 let Inst{32...37} = opcode;145 146 bits<1> PPC970_First = 0;147 bits<1> PPC970_Single = 0;148 bits<1> PPC970_Cracked = 0;149 bits<3> PPC970_Unit = 0;150 151 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to152 /// these must be reflected there! See comments there for what these are.153 let TSFlags{0} = PPC970_First;154 let TSFlags{1} = PPC970_Single;155 let TSFlags{2} = PPC970_Cracked;156 let TSFlags{5...3} = PPC970_Unit;157 158 bits<1> Prefixed = 1; // This is a prefixed instruction.159 let TSFlags{7} = Prefixed;160 161 // Indicate that this instruction takes a register+immediate memory operand.162 bits<1> MemriOp = 0;163 let TSFlags{10} = MemriOp;164 165 // For cases where multiple instruction definitions really represent the166 // same underlying instruction but with one definition for 64-bit arguments167 // and one for 32-bit arguments, this bit breaks the degeneracy between168 // the two forms and allows TableGen to generate mapping tables.169 bit Interpretation64Bit = 0;170 171 // Fields used for relation models.172 string BaseName = "";173}174 175// VX-Form: [ PO VT R VB RC XO ]176class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,177 InstrItinClass itin, list<dag> pattern>178 : I<4, OOL, IOL, asmstr, itin> {179 bits<5> VT;180 bits<5> VB;181 bit RC = 0;182 183 let Pattern = pattern;184 185 let Inst{6...10} = VT;186 let Inst{11...15} = R;187 let Inst{16...20} = VB;188 let Inst{21} = RC;189 let Inst{22...31} = xo;190}191 192// Multiclass definition to account for record and non-record form193// instructions of VXRForm.194multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,195 string asmbase, string asmstr,196 InstrItinClass itin, list<dag> pattern> {197 let BaseName = asmbase in {198 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,199 !strconcat(asmbase, !strconcat(" ", asmstr)),200 itin, pattern>, RecFormRel;201 let Defs = [CR6] in202 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,203 !strconcat(asmbase, !strconcat(". ", asmstr)),204 itin, []>, isRecordForm, RecFormRel;205 }206}207 208class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,209 InstrItinClass itin, list<dag> pattern>210 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {211 bits<5> RST;212 bits<5> RA;213 bits<34> D;214 215 let Pattern = pattern;216 217 // The prefix.218 let Inst{6...7} = 2;219 let Inst{8...10} = 0;220 let Inst{11} = PCRel;221 let Inst{12...13} = 0;222 let Inst{14...31} = D{33...16}; // d0223 224 // The instruction.225 let Inst{38...42} = RST{4...0};226 let Inst{43...47} = RA;227 let Inst{48...63} = D{15...0}; // d1228}229 230class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,231 InstrItinClass itin, list<dag> pattern>232 : PI<1, opcode, OOL, IOL, asmstr, itin> {233 bits<5> RT;234 bits<5> RA;235 bits<34> SI;236 237 let Pattern = pattern;238 239 // The prefix.240 let Inst{6...7} = 2;241 let Inst{8...10} = 0;242 let Inst{11} = PCRel;243 let Inst{12...13} = 0;244 let Inst{14...31} = SI{33...16};245 246 // The instruction.247 let Inst{38...42} = RT;248 let Inst{43...47} = RA;249 let Inst{48...63} = SI{15...0};250}251 252class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,253 InstrItinClass itin, list<dag> pattern>254 : PI<1, opcode, OOL, IOL, asmstr, itin> {255 bits<5> RT;256 bits<34> SI;257 258 let Pattern = pattern;259 260 // The prefix.261 let Inst{6...7} = 2;262 let Inst{8...10} = 0;263 let Inst{11} = 0;264 let Inst{12...13} = 0;265 let Inst{14...31} = SI{33...16};266 267 // The instruction.268 let Inst{38...42} = RT;269 let Inst{43...47} = 0;270 let Inst{48...63} = SI{15...0};271}272 273multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,274 dag PCRel_IOL, string asmstr,275 InstrItinClass itin> {276 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,277 !strconcat(asmstr, ", 0"), itin, []>;278 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,279 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;280}281 282class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,283 InstrItinClass itin, list<dag> pattern>284 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {285 bits<5> RST;286 bits<5> RA;287 bits<34> D;288 289 let Pattern = pattern;290 291 // The prefix.292 let Inst{6...10} = 0;293 let Inst{11} = PCRel;294 let Inst{12...13} = 0;295 let Inst{14...31} = D{33...16}; // d0296 297 // The instruction.298 let Inst{38...42} = RST{4...0};299 let Inst{43...47} = RA;300 let Inst{48...63} = D{15...0}; // d1301}302 303// 8LS:D-Form: [ 1 0 0 // R // d0304// PO TX T RA d1 ]305class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,306 string asmstr, InstrItinClass itin,307 list<dag> pattern>308 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin>, MemriOp {309 bits<6> XST;310 bits<5> RA;311 bits<34> D;312 313 let Pattern = pattern;314 315 // The prefix.316 let Inst{6...7} = 0;317 let Inst{8} = 0;318 let Inst{9...10} = 0; // reserved319 let Inst{11} = PCRel;320 let Inst{12...13} = 0; // reserved321 let Inst{14...31} = D{33...16}; // d0322 323 // The instruction.324 let Inst{37} = XST{5};325 let Inst{38...42} = XST{4...0};326 let Inst{43...47} = RA;327 let Inst{48...63} = D{15...0}; // d1328}329 330// X-Form: [PO T IMM VRB XO TX]331class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,332 string asmstr, InstrItinClass itin, list<dag> pattern>333 : I<opcode, OOL, IOL, asmstr, itin> {334 bits<6> XT;335 bits<5> VRB;336 bits<5> IMM;337 338 let Pattern = pattern;339 let Inst{6...10} = XT{4...0};340 let Inst{11...15} = IMM;341 let Inst{16...20} = VRB;342 let Inst{21...30} = xo;343 let Inst{31} = XT{5};344}345 346class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,347 dag OOL, dag IOL, string asmstr,348 InstrItinClass itin, list<dag> pattern>349 : PI<1, opcode, OOL, IOL, asmstr, itin> {350 bits<6> XT;351 bits<6> XA;352 bits<6> XB;353 bits<6> XC;354 bits<8> IMM;355 356 let Pattern = pattern;357 358 // The prefix.359 let Inst{6...7} = 1;360 let Inst{8} = 0;361 let Inst{9...11} = 0;362 let Inst{12...13} = 0;363 let Inst{14...23} = 0;364 let Inst{24...31} = IMM;365 366 // The instruction.367 let Inst{38...42} = XT{4...0};368 let Inst{43...47} = XA{4...0};369 let Inst{48...52} = XB{4...0};370 let Inst{53...57} = XC{4...0};371 let Inst{58...59} = xo;372 let Inst{60} = XC{5};373 let Inst{61} = XA{5};374 let Inst{62} = XB{5};375 let Inst{63} = XT{5};376}377 378class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,379 InstrItinClass itin, list<dag> pattern>380 : I<4, OOL, IOL, asmstr, itin> {381 bits<5> RD;382 bits<5> VB;383 bits<3> N;384 385 let Pattern = pattern;386 387 let Inst{6...10} = RD;388 let Inst{11...12} = 0;389 let Inst{13...15} = N;390 let Inst{16...20} = VB;391 let Inst{21...31} = xo;392}393 394 395// VX-Form: [PO VRT RA VRB XO].396// Destructive (insert) forms are suffixed with _ins.397class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>398 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB),399 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,400 RegConstraint<"$VDi = $VD">;401 402// VX-Form: [PO VRT RA RB XO].403// Destructive (insert) forms are suffixed with _ins.404class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>405 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB),406 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,407 RegConstraint<"$VDi = $VD">;408 409// VX-Form: [ PO BF // VRA VRB XO ]410class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,411 InstrItinClass itin, list<dag> pattern>412 : I<4, OOL, IOL, asmstr, itin> {413 bits<3> BF;414 bits<5> VA;415 bits<5> VB;416 417 let Pattern = pattern;418 419 let Inst{6...8} = BF;420 let Inst{9...10} = 0;421 let Inst{11...15} = VA;422 let Inst{16...20} = VB;423 let Inst{21...31} = xo;424}425 426// VN-Form: [PO VRT VRA VRB PS SD XO]427// SD is "Shift Direction"428class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,429 InstrItinClass itin, list<dag> pattern>430 : I<4, OOL, IOL, asmstr, itin> {431 bits<5> VRT;432 bits<5> VRA;433 bits<5> VRB;434 bits<3> SD;435 436 let Pattern = pattern;437 438 let Inst{6...10} = VRT;439 let Inst{11...15} = VRA;440 let Inst{16...20} = VRB;441 let Inst{21...22} = ps;442 let Inst{23...25} = SD;443 let Inst{26...31} = xo;444}445 446class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,447 string asmstr, InstrItinClass itin, list<dag> pattern>448 : I<4, OOL, IOL, asmstr, itin> {449 bits<5> RD;450 bits<5> VB;451 bit MP;452 453 let Pattern = pattern;454 455 let Inst{6...10} = RD;456 let Inst{11...14} = eo;457 let Inst{15} = MP;458 let Inst{16...20} = VB;459 let Inst{21...31} = xo;460}461 462// 8RR:D-Form: [ 1 1 0 // // imm0463// PO T XO TX imm1 ].464class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,465 string asmstr, InstrItinClass itin,466 list<dag> pattern>467 : PI<1, opcode, OOL, IOL, asmstr, itin> {468 bits<6> XT;469 bits<32> IMM32;470 471 let Pattern = pattern;472 473 // The prefix.474 let Inst{6...7} = 1;475 let Inst{8...11} = 0;476 let Inst{12...13} = 0; // reserved477 let Inst{14...15} = 0; // reserved478 let Inst{16...31} = IMM32{31...16};479 480 // The instruction.481 let Inst{38...42} = XT{4...0};482 let Inst{43...46} = xo;483 let Inst{47} = XT{5};484 let Inst{48...63} = IMM32{15...0};485}486 487// 8RR:D-Form: [ 1 1 0 // // imm0488// PO T XO IX TX imm1 ].489class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,490 string asmstr, InstrItinClass itin,491 list<dag> pattern>492 : PI<1, opcode, OOL, IOL, asmstr, itin> {493 bits<6> XT;494 bit IX;495 bits<32> IMM32;496 497 let Pattern = pattern;498 499 // The prefix.500 let Inst{6...7} = 1;501 let Inst{8...11} = 0;502 let Inst{12...13} = 0; // reserved503 let Inst{14...15} = 0; // reserved504 let Inst{16...31} = IMM32{31...16};505 506 // The instruction.507 let Inst{38...42} = XT{4...0};508 let Inst{43...45} = xo;509 let Inst{46} = IX;510 let Inst{47} = XT{5};511 let Inst{48...63} = IMM32{15...0};512}513 514class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,515 string asmstr, InstrItinClass itin, list<dag> pattern>516 : PI<1, opcode, OOL, IOL, asmstr, itin> {517 bits<6> XT;518 bits<6> XA;519 bits<6> XB;520 bits<6> XC;521 522 let Pattern = pattern;523 524 // The prefix.525 let Inst{6...7} = 1;526 let Inst{8...11} = 0;527 let Inst{12...13} = 0;528 let Inst{14...31} = 0;529 530 // The instruction.531 let Inst{38...42} = XT{4...0};532 let Inst{43...47} = XA{4...0};533 let Inst{48...52} = XB{4...0};534 let Inst{53...57} = XC{4...0};535 let Inst{58...59} = xo;536 let Inst{60} = XC{5};537 let Inst{61} = XA{5};538 let Inst{62} = XB{5};539 let Inst{63} = XT{5};540}541 542class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,543 string asmstr, InstrItinClass itin,544 list<dag> pattern>545 : PI<1, opcode, OOL, IOL, asmstr, itin> {546 bits<6> XT;547 bits<6> XA;548 bits<6> XB;549 bits<6> XC;550 bits<3> IMM;551 552 let Pattern = pattern;553 554 // The prefix.555 let Inst{6...7} = 1;556 let Inst{8...11} = 0;557 let Inst{12...13} = 0;558 let Inst{14...28} = 0;559 let Inst{29...31} = IMM;560 561 // The instruction.562 let Inst{38...42} = XT{4...0};563 let Inst{43...47} = XA{4...0};564 let Inst{48...52} = XB{4...0};565 let Inst{53...57} = XC{4...0};566 let Inst{58...59} = xo;567 let Inst{60} = XC{5};568 let Inst{61} = XA{5};569 let Inst{62} = XB{5};570 let Inst{63} = XT{5};571}572 573// [PO BF / XO2 B XO BX /]574class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,575 dag IOL, string asmstr, InstrItinClass itin,576 list<dag> pattern>577 : I<opcode, OOL, IOL, asmstr, itin> {578 bits<3> BF;579 bits<6> XB;580 581 let Pattern = pattern;582 583 let Inst{6...8} = BF;584 let Inst{9...10} = 0;585 let Inst{11...15} = xo2;586 let Inst{16...20} = XB{4...0};587 let Inst{21...29} = xo;588 let Inst{30} = XB{5};589 let Inst{31} = 0;590}591 592// X-Form: [ PO RT BI /// XO / ]593class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,594 string asmstr, InstrItinClass itin, list<dag> pattern>595 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {596 bits<5> BI;597 let RA = BI;598 let RB = 0;599}600 601multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,602 dag PCRel_IOL, dag PCRelOnly_IOL,603 string asmstr, string asmstr_pcext,604 InstrItinClass itin> {605 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,606 !strconcat(asmstr, ", 0"), itin, []>;607 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,608 !strconcat(asmstr, ", 1"), itin, []>,609 isPCRel;610 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {611 def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;612 let RA = 0, MemriOp = 0 in613 def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,614 asmstr_pcext, itin, []>, isPCRel;615 }616}617 618multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,619 dag PCRel_IOL, dag PCRelOnly_IOL,620 string asmstr, string asmstr_pcext,621 InstrItinClass itin> {622 def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,623 !strconcat(asmstr, ", 0"), itin, []>;624 def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,625 !strconcat(asmstr, ", 1"), itin, []>,626 isPCRel;627 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {628 def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;629 let RA = 0, MemriOp = 0 in630 def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,631 asmstr_pcext, itin, []>, isPCRel;632 }633}634 635multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,636 dag PCRel_IOL, dag PCRelOnly_IOL,637 string asmstr, string asmstr_pcext,638 InstrItinClass itin> {639 def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,640 !strconcat(asmstr, ", 0"), itin, []>;641 def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,642 !strconcat(asmstr, ", 1"), itin, []>,643 isPCRel;644 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {645 def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;646 let RA = 0, MemriOp = 0 in647 def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL,648 asmstr_pcext, itin, []>, isPCRel;649 }650}651 652def RCCp {653 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);654 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);655}656 657let Predicates = [PrefixInstrs] in {658 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {659 defm PADDI8 :660 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI),661 (ins immZero:$RA, s34imm_pcrel:$SI),662 "paddi $RT, $RA, $SI", IIC_LdStLFD>;663 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {664 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),665 (ins s34imm:$SI),666 "pli $RT, $SI", IIC_IntSimple, []>;667 }668 }669 defm PADDI :670 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI),671 (ins immZero:$RA, s34imm_pcrel:$SI),672 "paddi $RT, $RA, $SI", IIC_LdStLFD>;673 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {674 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),675 (ins s34imm:$SI),676 "pli $RT, $SI", IIC_IntSimple, []>;677 }678 679 let mayLoad = 1, mayStore = 0 in {680 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {681 defm PLBZ8 :682 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),683 (ins (memri34_pcrel $D, $RA):$addr),684 (ins s34imm_pcrel:$D), "plbz $RST, $addr",685 "plbz $RST, $D", IIC_LdStLFD>;686 defm PLHZ8 :687 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),688 (ins (memri34_pcrel $D, $RA):$addr),689 (ins s34imm_pcrel:$D), "plhz $RST, $addr",690 "plhz $RST, $D", IIC_LdStLFD>;691 defm PLHA8 :692 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),693 (ins (memri34_pcrel $D, $RA):$addr),694 (ins s34imm_pcrel:$D), "plha $RST, $addr",695 "plha $RST, $D", IIC_LdStLFD>;696 defm PLWA8 :697 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),698 (ins (memri34_pcrel $D, $RA):$addr),699 (ins s34imm_pcrel:$D),700 "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>;701 defm PLWZ8 :702 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),703 (ins (memri34_pcrel $D, $RA):$addr),704 (ins s34imm_pcrel:$D), "plwz $RST, $addr",705 "plwz $RST, $D", IIC_LdStLFD>;706 }707 defm PLBZ :708 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),709 (ins (memri34_pcrel $D, $RA):$addr),710 (ins s34imm_pcrel:$D), "plbz $RST, $addr",711 "plbz $RST, $D", IIC_LdStLFD>;712 defm PLHZ :713 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),714 (ins (memri34_pcrel $D, $RA):$addr),715 (ins s34imm_pcrel:$D), "plhz $RST, $addr",716 "plhz $RST, $D", IIC_LdStLFD>;717 defm PLHA :718 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),719 (ins (memri34_pcrel $D, $RA):$addr),720 (ins s34imm_pcrel:$D), "plha $RST, $addr",721 "plha $RST, $D", IIC_LdStLFD>;722 defm PLWZ :723 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),724 (ins (memri34_pcrel $D, $RA):$addr),725 (ins s34imm_pcrel:$D), "plwz $RST, $addr",726 "plwz $RST, $D", IIC_LdStLFD>;727 defm PLWA :728 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),729 (ins (memri34_pcrel $D, $RA):$addr),730 (ins s34imm_pcrel:$D),731 "plwa $RST, $addr", "plwa $RST, $D",732 IIC_LdStLFD>;733 defm PLD :734 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),735 (ins (memri34_pcrel $D, $RA):$addr),736 (ins s34imm_pcrel:$D),737 "pld $RST, $addr", "pld $RST, $D",738 IIC_LdStLFD>;739 }740 741 let mayStore = 1, mayLoad = 0 in {742 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {743 defm PSTB8 :744 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),745 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),746 (ins g8rc:$RST, s34imm_pcrel:$D),747 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;748 defm PSTH8 :749 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),750 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),751 (ins g8rc:$RST, s34imm_pcrel:$D),752 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;753 defm PSTW8 :754 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),755 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),756 (ins g8rc:$RST, s34imm_pcrel:$D),757 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;758 }759 defm PSTB :760 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),761 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),762 (ins gprc:$RST, s34imm_pcrel:$D),763 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;764 defm PSTH :765 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),766 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),767 (ins gprc:$RST, s34imm_pcrel:$D),768 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;769 defm PSTW :770 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),771 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),772 (ins gprc:$RST, s34imm_pcrel:$D),773 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;774 defm PSTD :775 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),776 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),777 (ins g8rc:$RST, s34imm_pcrel:$D),778 "pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>;779 }780}781 782let Predicates = [PrefixInstrs, HasFPU] in {783 let mayLoad = 1, mayStore = 0 in {784 defm PLFS :785 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),786 (ins (memri34_pcrel $D, $RA):$addr),787 (ins s34imm_pcrel:$D), "plfs $RST, $addr",788 "plfs $RST, $D", IIC_LdStLFD>;789 defm PLFD :790 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),791 (ins (memri34_pcrel $D, $RA):$addr),792 (ins s34imm_pcrel:$D), "plfd $RST, $addr",793 "plfd $RST, $D", IIC_LdStLFD>;794 }795 let mayStore = 1, mayLoad = 0 in {796 defm PSTFS :797 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),798 (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),799 (ins f4rc:$RST, s34imm_pcrel:$D),800 "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;801 defm PSTFD :802 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),803 (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),804 (ins f8rc:$RST, s34imm_pcrel:$D),805 "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;806 }807}808 809let Predicates = [PrefixInstrs, HasP10Vector] in {810 let mayLoad = 1, mayStore = 0 in {811 defm PLXV :812 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),813 (ins (memri34_pcrel $D, $RA):$addr),814 (ins s34imm_pcrel:$D),815 "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;816 defm PLXSSP :817 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),818 (ins (memri34_pcrel $D, $RA):$addr),819 (ins s34imm_pcrel:$D),820 "plxssp $RST, $addr", "plxssp $RST, $D",821 IIC_LdStLFD>;822 defm PLXSD :823 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),824 (ins (memri34_pcrel $D, $RA):$addr),825 (ins s34imm_pcrel:$D),826 "plxsd $RST, $addr", "plxsd $RST, $D",827 IIC_LdStLFD>;828 }829 let mayStore = 1, mayLoad = 0 in {830 defm PSTXV :831 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),832 (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),833 (ins vsrc:$XST, s34imm_pcrel:$D),834 "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;835 defm PSTXSSP :836 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),837 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),838 (ins vfrc:$RST, s34imm_pcrel:$D),839 "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;840 defm PSTXSD :841 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),842 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),843 (ins vfrc:$RST, s34imm_pcrel:$D),844 "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;845 }846 def XXPERMX :847 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,848 vsrc:$XC, u3imm:$IMM),849 "xxpermx $XT, $XA, $XB, $XC, $IMM",850 IIC_VecPerm, []>;851 def XXBLENDVB :852 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,853 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",854 IIC_VecGeneral, []>;855 def XXBLENDVH :856 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,857 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",858 IIC_VecGeneral, []>;859 def XXBLENDVW :860 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,861 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",862 IIC_VecGeneral, []>;863 def XXBLENDVD :864 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,865 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",866 IIC_VecGeneral, []>;867}868 869class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,870 string asmstr, InstrItinClass itin, list<dag> pattern>871 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp {872 bits<5> XTp;873 bits<5> RA;874 bits<12> DQ;875 876 let Pattern = pattern;877 878 let Inst{6...9} = XTp{3...0};879 let Inst{10} = XTp{4};880 let Inst{11...15} = RA;881 let Inst{16...27} = DQ;882 let Inst{28...31} = xo;883}884 885class XForm_XTp5_RAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,886 string asmstr, InstrItinClass itin, list<dag> pattern>887 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {888 bits<5> XTp;889 bits<5> RA;890 bits<5> RB;891 892 let Pattern = pattern;893 let Inst{6...9} = XTp{3...0};894 let Inst{10} = XTp{4};895 let Inst{11...15} = RA;896 let Inst{16...20} = RB;897 let Inst{21...30} = xo;898 let Inst{31} = 0;899}900 901class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,902 InstrItinClass itin, list<dag> pattern>903 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {904 bits<5> XTp;905 bits<5> RA;906 bits<34> D;907 908 let Pattern = pattern;909 910 // The prefix.911 let Inst{6...10} = 0;912 let Inst{11} = PCRel;913 let Inst{12...13} = 0;914 let Inst{14...31} = D{33...16}; // Imm18915 916 // The instruction.917 let Inst{38...41} = XTp{3...0};918 let Inst{42} = XTp{4};919 let Inst{43...47} = RA;920 let Inst{48...63} = D{15...0};921}922 923multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,924 dag IOL, dag PCRel_IOL, dag PCRelOnly_IOL,925 string asmstr, string asmstr_pcext,926 InstrItinClass itin> {927 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,928 !strconcat(asmstr, ", 0"), itin, []>;929 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,930 !strconcat(asmstr, ", 1"), itin, []>,931 isPCRel;932 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {933 def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>;934 let RA = 0, MemriOp = 0 in935 def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL,936 asmstr_pcext, itin, []>, isPCRel;937 }938}939 940 941 942// [PO AS XO2 XO]943class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,944 string asmstr, InstrItinClass itin, list<dag> pattern>945 : I<opcode, OOL, IOL, asmstr, itin> {946 bits<3> AT;947 948 let Pattern = pattern;949 950 let Inst{6...8} = AT;951 let Inst{9...10} = 0;952 let Inst{11...15} = xo2;953 let Inst{16...20} = 0;954 let Inst{21...30} = xo;955 let Inst{31} = 0;956}957 958// X-Form: [ PO T EO UIM XO TX ]959class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,960 string asmstr, InstrItinClass itin, list<dag> pattern>961 : I<opcode, OOL, IOL, asmstr, itin> {962 bits<6> XT;963 bits<5> UIM;964 965 let Pattern = pattern;966 967 let Inst{6...10} = XT{4...0};968 let Inst{11...15} = eo;969 let Inst{16...20} = UIM;970 let Inst{21...30} = xo;971 let Inst{31} = XT{5};972}973 974class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,975 string asmstr, InstrItinClass itin,976 list<dag> pattern>977 : I<opcode, OOL, IOL, asmstr, itin> {978 bits<3> AT;979 bits<6> XA;980 bits<6> XB;981 982 let Pattern = pattern;983 984 let Inst{6...8} = AT;985 let Inst{9...10} = 0;986 let Inst{11...15} = XA{4...0};987 let Inst{16...20} = XB{4...0};988 let Inst{21...28} = xo;989 let Inst{29} = XA{5};990 let Inst{30} = XB{5};991 let Inst{31} = 0;992}993 994class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,995 string asmstr, InstrItinClass itin,996 list<dag> pattern>997 : PI<1, opcode, OOL, IOL, asmstr, itin> {998 bits<3> AT;999 bits<6> XA;1000 bits<6> XB;1001 bits<4> XMSK;1002 bits<4> YMSK;1003 bits<2> PMSK;1004 1005 let Pattern = pattern;1006 1007 // The prefix.1008 let Inst{6...7} = 3;1009 let Inst{8...11} = 9;1010 let Inst{12...15} = 0;1011 let Inst{16...17} = PMSK;1012 let Inst{18...23} = 0;1013 let Inst{24...27} = XMSK;1014 let Inst{28...31} = YMSK;1015 1016 // The instruction.1017 let Inst{38...40} = AT;1018 let Inst{41...42} = 0;1019 let Inst{43...47} = XA{4...0};1020 let Inst{48...52} = XB{4...0};1021 let Inst{53...60} = xo;1022 let Inst{61} = XA{5};1023 let Inst{62} = XB{5};1024 let Inst{63} = 0;1025}1026 1027class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1028 string asmstr, InstrItinClass itin,1029 list<dag> pattern>1030 : PI<1, opcode, OOL, IOL, asmstr, itin> {1031 bits<3> AT;1032 bits<6> XA;1033 bits<6> XB;1034 bits<4> XMSK;1035 bits<4> YMSK;1036 1037 let Pattern = pattern;1038 1039 // The prefix.1040 let Inst{6...7} = 3;1041 let Inst{8...11} = 9;1042 let Inst{12...23} = 0;1043 let Inst{24...27} = XMSK;1044 let Inst{28...31} = YMSK;1045 1046 // The instruction.1047 let Inst{38...40} = AT;1048 let Inst{41...42} = 0;1049 let Inst{43...47} = XA{4...0};1050 let Inst{48...52} = XB{4...0};1051 let Inst{53...60} = xo;1052 let Inst{61} = XA{5};1053 let Inst{62} = XB{5};1054 let Inst{63} = 0;1055}1056 1057class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1058 string asmstr, InstrItinClass itin,1059 list<dag> pattern>1060 : PI<1, opcode, OOL, IOL, asmstr, itin> {1061 bits<3> AT;1062 bits<6> XA;1063 bits<6> XB;1064 bits<4> XMSK;1065 bits<2> YMSK;1066 1067 let Pattern = pattern;1068 1069 // The prefix.1070 let Inst{6...7} = 3;1071 let Inst{8...11} = 9;1072 let Inst{12...23} = 0;1073 let Inst{24...27} = XMSK;1074 let Inst{28...29} = YMSK;1075 let Inst{30...31} = 0;1076 1077 // The instruction.1078 let Inst{38...40} = AT;1079 let Inst{41...42} = 0;1080 let Inst{43...47} = XA{4...0};1081 let Inst{48...52} = XB{4...0};1082 let Inst{53...60} = xo;1083 let Inst{61} = XA{5};1084 let Inst{62} = XB{5};1085 let Inst{63} = 0;1086}1087 1088class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1089 string asmstr, InstrItinClass itin,1090 list<dag> pattern>1091 : PI<1, opcode, OOL, IOL, asmstr, itin> {1092 bits<3> AT;1093 bits<6> XA;1094 bits<6> XB;1095 bits<4> XMSK;1096 bits<4> YMSK;1097 bits<8> PMSK;1098 1099 let Pattern = pattern;1100 1101 // The prefix.1102 let Inst{6...7} = 3;1103 let Inst{8...11} = 9;1104 let Inst{12...15} = 0;1105 let Inst{16...23} = PMSK;1106 let Inst{24...27} = XMSK;1107 let Inst{28...31} = YMSK;1108 1109 // The instruction.1110 let Inst{38...40} = AT;1111 let Inst{41...42} = 0;1112 let Inst{43...47} = XA{4...0};1113 let Inst{48...52} = XB{4...0};1114 let Inst{53...60} = xo;1115 let Inst{61} = XA{5};1116 let Inst{62} = XB{5};1117 let Inst{63} = 0;1118}1119 1120class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,1121 string asmstr, InstrItinClass itin,1122 list<dag> pattern>1123 : PI<1, opcode, OOL, IOL, asmstr, itin> {1124 bits<3> AT;1125 bits<6> XA;1126 bits<6> XB;1127 bits<4> XMSK;1128 bits<4> YMSK;1129 bits<4> PMSK;1130 1131 let Pattern = pattern;1132 1133 // The prefix.1134 let Inst{6...7} = 3;1135 let Inst{8...11} = 9;1136 let Inst{12...15} = 0;1137 let Inst{16...19} = PMSK;1138 let Inst{20...23} = 0;1139 let Inst{24...27} = XMSK;1140 let Inst{28...31} = YMSK;1141 1142 // The instruction.1143 let Inst{38...40} = AT;1144 let Inst{41...42} = 0;1145 let Inst{43...47} = XA{4...0};1146 let Inst{48...52} = XB{4...0};1147 let Inst{53...60} = xo;1148 let Inst{61} = XA{5};1149 let Inst{62} = XB{5};1150 let Inst{63} = 0;1151}1152 1153def Concats {1154 dag VecsToVecPair0 =1155 (v256i1 (REG_SEQUENCE VSRpRC, $vs0, sub_vsx1, $vs1, sub_vsx0));1156 dag VecsToVecPair1 =1157 (v256i1 (REG_SEQUENCE VSRpRC, $vs2, sub_vsx1, $vs3, sub_vsx0));1158}1159 1160let Predicates = [PairedVectorMemops] in {1161 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),1162 Concats.VecsToVecPair0>;1163 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),1164 Concats.VecsToVecPair0>;1165 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),1166 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;1167 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),1168 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;1169 1170 let mayLoad = 1, mayStore = 0 in {1171 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),1172 (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr",1173 IIC_LdStLFD, []>;1174 def LXVPX : XForm_XTp5_RAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr),1175 "lxvpx $XTp, $addr", IIC_LdStLFD,1176 []>;1177 }1178 1179 let mayLoad = 0, mayStore = 1 in {1180 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,1181 (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr",1182 IIC_LdStLFD, []>;1183 def STXVPX : XForm_XTp5_RAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr),1184 "stxvpx $XTp, $addr", IIC_LdStLFD,1185 []>;1186 }1187}1188let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {1189 defm PLXVP :1190 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),1191 (ins (memri34_pcrel $D, $RA):$addr),1192 (ins s34imm_pcrel:$D),1193 "plxvp $XTp, $addr", "plxvp $XTp, $D",1194 IIC_LdStLFD>;1195}1196 1197let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {1198 defm PSTXVP :1199 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),1200 (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),1201 (ins vsrprc:$XTp, s34imm_pcrel:$D),1202 "pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>;1203}1204 1205let Predicates = [PairedVectorMemops] in {1206 // Intrinsics for Paired Vector Loads.1207 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;1208 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;1209 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {1210 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;1211 }1212 // Intrinsics for Paired Vector Stores.1213 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),1214 (STXVP $XSp, memrix16:$dst)>;1215 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),1216 (STXVPX $XSp, XForm:$dst)>;1217 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {1218 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),1219 (PSTXVP $XSp, memri34:$dst)>;1220 }1221}1222 1223let Predicates = [IsISA3_1] in {1224 def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>;1225 def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>;1226 def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>;1227}1228 1229let Predicates = [PCRelativeMemops] in {1230 // Load i321231 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))),1232 (PLBZpc $ga, 0)>;1233 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))),1234 (PLBZpc $ga, 0)>;1235 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))),1236 (PLBZpc $ga, 0)>;1237 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))),1238 (PLBZpc $ga, 0)>;1239 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1240 (PLHApc $ga, 0)>;1241 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1242 (PLHZpc $ga, 0)>;1243 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1244 (PLHZpc $ga, 0)>;1245 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>;1246 1247 // Store i321248 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1249 (PSTBpc $RS, $ga, 0)>;1250 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1251 (PSTHpc $RS, $ga, 0)>;1252 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1253 (PSTWpc $RS, $ga, 0)>;1254 1255 // Load i641256 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))),1257 (PLBZ8pc $ga, 0)>;1258 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))),1259 (PLBZ8pc $ga, 0)>;1260 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))),1261 (PLBZ8pc $ga, 0)>;1262 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))),1263 (PLBZ8pc $ga, 0)>;1264 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1265 (PLHA8pc $ga, 0)>;1266 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1267 (PLHZ8pc $ga, 0)>;1268 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),1269 (PLHZ8pc $ga, 0)>;1270 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),1271 (PLWZ8pc $ga, 0)>;1272 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),1273 (PLWA8pc $ga, 0)>;1274 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))),1275 (PLWZ8pc $ga, 0)>;1276 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>;1277 1278 // Store i641279 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1280 (PSTB8pc $RS, $ga, 0)>;1281 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1282 (PSTH8pc $RS, $ga, 0)>;1283 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1284 (PSTW8pc $RS, $ga, 0)>;1285 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1286 (PSTDpc $RS, $ga, 0)>;1287 1288 // Atomic Load1289 def : Pat<(i32 (atomic_load_azext_8 (PPCmatpcreladdr PCRelForm:$ga))),1290 (PLBZpc $ga, 0)>;1291 def : Pat<(i32 (atomic_load_azext_16 (PPCmatpcreladdr PCRelForm:$ga))),1292 (PLHZpc $ga, 0)>;1293 def : Pat<(i32 (atomic_load_nonext_32 (PPCmatpcreladdr PCRelForm:$ga))),1294 (PLWZpc $ga, 0)>;1295 def : Pat<(i64 (atomic_load_nonext_64 (PPCmatpcreladdr PCRelForm:$ga))),1296 (PLDpc $ga, 0)>;1297 1298 // Atomic Store1299 def : Pat<(atomic_store_8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1300 (PSTBpc $RS, $ga, 0)>;1301 def : Pat<(atomic_store_16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1302 (PSTHpc $RS, $ga, 0)>;1303 def : Pat<(atomic_store_32 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1304 (PSTWpc $RS, $ga, 0)>;1305 def : Pat<(atomic_store_8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1306 (PSTB8pc $RS, $ga, 0)>;1307 def : Pat<(atomic_store_16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1308 (PSTH8pc $RS, $ga, 0)>;1309 def : Pat<(atomic_store_32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1310 (PSTW8pc $RS, $ga, 0)>;1311 def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),1312 (PSTDpc $RS, $ga, 0)>;1313 1314 // If the PPCmatpcreladdr node is not caught by any other pattern it should be1315 // caught here and turned into a paddi instruction to materialize the address.1316 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;1317 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize1318 // tls global address with paddi instruction.1319 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;1320 // PPCtlslocalexecmataddr node is used for TLS local exec models to1321 // materialize tls global address with paddi instruction.1322 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),1323 (PADDI8 $in, $addr)>;1324}1325 1326let Predicates = [PCRelativeMemops, HasFPU] in {1327 // Load f321328 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;1329 1330 // Store f321331 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),1332 (PSTFSpc $FRS, $ga, 0)>;1333 1334 // Load f641335 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))),1336 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;1337 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>;1338 1339 // Store f641340 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),1341 (PSTFDpc $FRS, $ga, 0)>;1342 1343 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),1344 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;1345}1346 1347let Predicates = [PCRelativeMemops, HasP10Vector] in {1348 // Load f1281349 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),1350 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;1351 1352 // Store f1281353 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)),1354 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;1355 1356 // Load v4i321357 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;1358 1359 // Store v4i321360 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),1361 (PSTXVpc $XS, $ga, 0)>;1362 1363 // Load v2i641364 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;1365 1366 // Store v2i641367 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),1368 (PSTXVpc $XS, $ga, 0)>;1369 1370 // Load v4f321371 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;1372 1373 // Store v4f321374 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),1375 (PSTXVpc $XS, $ga, 0)>;1376 1377 // Load v2f641378 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;1379 1380 // Store v2f641381 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),1382 (PSTXVpc $XS, $ga, 0)>;1383 1384 // Special Cases For PPCstore_scal_int_from_vsr1385 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),1386 (PSTXSDpc $src, $dst, 0)>;1387 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),1388 (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;1389}1390 1391// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt1392// to spill part of the instruction when the values are similar.1393let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {1394 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),1395 (ins i32imm:$IMM32),1396 "xxspltiw $XT, $IMM32", IIC_VecGeneral,1397 []>;1398 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),1399 (ins i32imm:$IMM32),1400 "xxspltidp $XT, $IMM32", IIC_VecGeneral,1401 [(set v2f64:$XT,1402 (PPCxxspltidp i32:$IMM32))]>;1403 def XXSPLTI32DX :1404 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),1405 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),1406 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,1407 [(set v2i64:$XT,1408 (PPCxxsplti32dx v2i64:$XTi, i32:$IX,1409 i32:$IMM32))]>,1410 RegConstraint<"$XTi = $XT">;1411}1412 1413let Predicates = [IsISA3_1] in {1414 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI),1415 "setbc $RST, $BI", IIC_IntCompare,1416 [(set i32:$RST, (PPCsetbc i1:$BI))]>,1417 SExt32To64, ZExt32To64;1418 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI),1419 "setbcr $RST, $BI", IIC_IntCompare,1420 [(set i32:$RST, (PPCsetbcr i1:$BI))]>,1421 SExt32To64, ZExt32To64;1422 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI),1423 "setnbc $RST, $BI", IIC_IntCompare, []>,1424 SExt32To64;1425 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI),1426 "setnbcr $RST, $BI", IIC_IntCompare, []>,1427 SExt32To64;1428 1429 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {1430 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI),1431 "setbc $RST, $BI", IIC_IntCompare, []>,1432 SExt32To64, ZExt32To64;1433 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI),1434 "setbcr $RST, $BI", IIC_IntCompare, []>,1435 SExt32To64, ZExt32To64;1436 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI),1437 "setnbc $RST, $BI", IIC_IntCompare, []>,1438 SExt32To64;1439 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI),1440 "setnbcr $RST, $BI", IIC_IntCompare, []>,1441 SExt32To64;1442 }1443 1444 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),1445 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),1446 "vsldbi $VRT, $VRA, $VRB, $SD",1447 IIC_VecGeneral,1448 [(set v16i8:$VRT,1449 (int_ppc_altivec_vsldbi v16i8:$VRA,1450 v16i8:$VRB,1451 timm:$SD))]>;1452 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),1453 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),1454 "vsrdbi $VRT, $VRA, $VRB, $SD",1455 IIC_VecGeneral,1456 [(set v16i8:$VRT,1457 (int_ppc_altivec_vsrdbi v16i8:$VRA,1458 v16i8:$VRB, 1459 timm:$SD))]>;1460 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB),1461 "vstribr", "$VT, $VB", IIC_VecGeneral,1462 [(set v16i8:$VT,1463 (int_ppc_altivec_vstribr v16i8:$VB))]>;1464 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB),1465 "vstribl", "$VT, $VB", IIC_VecGeneral,1466 [(set v16i8:$VT,1467 (int_ppc_altivec_vstribl v16i8:$VB))]>;1468 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB),1469 "vstrihr", "$VT, $VB", IIC_VecGeneral,1470 [(set v8i16:$VT,1471 (int_ppc_altivec_vstrihr v8i16:$VB))]>;1472 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB),1473 "vstrihl", "$VT, $VB", IIC_VecGeneral,1474 [(set v8i16:$VT,1475 (int_ppc_altivec_vstrihl v8i16:$VB))]>;1476 def VINSW :1477 VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB),1478 "vinsw $VD, $VB, $VA", IIC_VecGeneral,1479 [(set v4i32:$VD,1480 (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,1481 RegConstraint<"$VDi = $VD">;1482 def VINSD :1483 VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),1484 "vinsd $VD, $VB, $VA", IIC_VecGeneral,1485 [(set v2i64:$VD,1486 (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>,1487 RegConstraint<"$VDi = $VD">;1488 def VINSBVLX :1489 VXForm_VTB5_RA5_ins<15, "vinsbvlx",1490 [(set v16i8:$VD,1491 (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA,1492 v16i8:$VB))]>;1493 def VINSBVRX :1494 VXForm_VTB5_RA5_ins<271, "vinsbvrx",1495 [(set v16i8:$VD,1496 (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA,1497 v16i8:$VB))]>;1498 def VINSHVLX :1499 VXForm_VTB5_RA5_ins<79, "vinshvlx",1500 [(set v8i16:$VD,1501 (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA,1502 v8i16:$VB))]>;1503 def VINSHVRX :1504 VXForm_VTB5_RA5_ins<335, "vinshvrx",1505 [(set v8i16:$VD,1506 (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA,1507 v8i16:$VB))]>;1508 def VINSWVLX :1509 VXForm_VTB5_RA5_ins<143, "vinswvlx",1510 [(set v4i32:$VD,1511 (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA,1512 v4i32:$VB))]>;1513 def VINSWVRX :1514 VXForm_VTB5_RA5_ins<399, "vinswvrx",1515 [(set v4i32:$VD,1516 (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA,1517 v4i32:$VB))]>;1518 def VINSBLX :1519 VXForm_VRT5_RAB5_ins<527, "vinsblx",1520 [(set v16i8:$VD,1521 (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA,1522 i32:$VB))]>;1523 def VINSBRX :1524 VXForm_VRT5_RAB5_ins<783, "vinsbrx",1525 [(set v16i8:$VD,1526 (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA,1527 i32:$VB))]>;1528 def VINSHLX :1529 VXForm_VRT5_RAB5_ins<591, "vinshlx",1530 [(set v8i16:$VD,1531 (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA,1532 i32:$VB))]>;1533 def VINSHRX :1534 VXForm_VRT5_RAB5_ins<847, "vinshrx",1535 [(set v8i16:$VD,1536 (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA,1537 i32:$VB))]>;1538 def VINSWLX :1539 VXForm_VRT5_RAB5_ins<655, "vinswlx",1540 [(set v4i32:$VD,1541 (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA,1542 i32:$VB))]>;1543 def VINSWRX :1544 VXForm_VRT5_RAB5_ins<911, "vinswrx",1545 [(set v4i32:$VD,1546 (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA,1547 i32:$VB))]>;1548 def VINSDLX :1549 VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),1550 "vinsdlx $VD, $VA, $VB", IIC_VecGeneral,1551 [(set v2i64:$VD,1552 (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>,1553 RegConstraint<"$VDi = $VD">;1554 def VINSDRX :1555 VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),1556 "vinsdrx $VD, $VA, $VB", IIC_VecGeneral,1557 [(set v2i64:$VD,1558 (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>,1559 RegConstraint<"$VDi = $VD">;1560 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB),1561 "vextractbm $VD, $VB", IIC_VecGeneral,1562 [(set i32:$VD,1563 (int_ppc_altivec_vextractbm v16i8:$VB))]>,1564 ZExt32To64;1565 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB),1566 "vextracthm $VD, $VB", IIC_VecGeneral,1567 [(set i32:$VD,1568 (int_ppc_altivec_vextracthm v8i16:$VB))]>,1569 ZExt32To64;1570 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB),1571 "vextractwm $VD, $VB", IIC_VecGeneral,1572 [(set i32:$VD,1573 (int_ppc_altivec_vextractwm v4i32:$VB))]>,1574 ZExt32To64;1575 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB),1576 "vextractdm $VD, $VB", IIC_VecGeneral,1577 [(set i32:$VD,1578 (int_ppc_altivec_vextractdm v2i64:$VB))]>,1579 ZExt32To64;1580 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB),1581 "vextractqm $VD, $VB", IIC_VecGeneral,1582 [(set i32:$VD,1583 (int_ppc_altivec_vextractqm v1i128:$VB))]>;1584 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB),1585 "vexpandbm $VD, $VB", IIC_VecGeneral,1586 [(set v16i8:$VD, (int_ppc_altivec_vexpandbm1587 v16i8:$VB))]>;1588 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB),1589 "vexpandhm $VD, $VB", IIC_VecGeneral,1590 [(set v8i16:$VD, (int_ppc_altivec_vexpandhm1591 v8i16:$VB))]>;1592 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB),1593 "vexpandwm $VD, $VB", IIC_VecGeneral,1594 [(set v4i32:$VD, (int_ppc_altivec_vexpandwm1595 v4i32:$VB))]>;1596 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB),1597 "vexpanddm $VD, $VB", IIC_VecGeneral,1598 [(set v2i64:$VD, (int_ppc_altivec_vexpanddm1599 v2i64:$VB))]>;1600 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB),1601 "vexpandqm $VD, $VB", IIC_VecGeneral,1602 [(set v1i128:$VD, (int_ppc_altivec_vexpandqm1603 v1i128:$VB))]>;1604 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB),1605 "mtvsrbm $VD, $VB", IIC_VecGeneral,1606 [(set v16i8:$VD,1607 (int_ppc_altivec_mtvsrbm i64:$VB))]>;1608 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB),1609 "mtvsrhm $VD, $VB", IIC_VecGeneral,1610 [(set v8i16:$VD,1611 (int_ppc_altivec_mtvsrhm i64:$VB))]>;1612 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB),1613 "mtvsrwm $VD, $VB", IIC_VecGeneral,1614 [(set v4i32:$VD,1615 (int_ppc_altivec_mtvsrwm i64:$VB))]>;1616 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB),1617 "mtvsrdm $VD, $VB", IIC_VecGeneral,1618 [(set v2i64:$VD,1619 (int_ppc_altivec_mtvsrdm i64:$VB))]>;1620 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB),1621 "mtvsrqm $VD, $VB", IIC_VecGeneral,1622 [(set v1i128:$VD,1623 (int_ppc_altivec_mtvsrqm i64:$VB))]>;1624 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D),1625 "mtvsrbmi $RT, $D", IIC_VecGeneral,1626 [(set v16i8:$RT,1627 (int_ppc_altivec_mtvsrbm imm:$D))]>;1628 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD),1629 (ins vrrc:$VB, u1imm:$MP),1630 "vcntmbb $RD, $VB, $MP", IIC_VecGeneral,1631 [(set i64:$RD, (int_ppc_altivec_vcntmbb1632 v16i8:$VB, timm:$MP))]>;1633 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD),1634 (ins vrrc:$VB, u1imm:$MP),1635 "vcntmbh $RD, $VB, $MP", IIC_VecGeneral,1636 [(set i64:$RD, (int_ppc_altivec_vcntmbh1637 v8i16:$VB, timm:$MP))]>;1638 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD),1639 (ins vrrc:$VB, u1imm:$MP),1640 "vcntmbw $RD, $VB, $MP", IIC_VecGeneral,1641 [(set i64:$RD, (int_ppc_altivec_vcntmbw1642 v4i32:$VB, timm:$MP))]>;1643 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD),1644 (ins vrrc:$VB, u1imm:$MP),1645 "vcntmbd $RD, $VB, $MP", IIC_VecGeneral,1646 [(set i64:$RD, (int_ppc_altivec_vcntmbd1647 v2i64:$VB, timm:$MP))]>;1648 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT),1649 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1650 "vextdubvlx $RT, $RA, $RB, $RC",1651 IIC_VecGeneral,1652 [(set v2i64:$RT,1653 (int_ppc_altivec_vextdubvlx v16i8:$RA,1654 v16i8:$RB,1655 i32:$RC))]>;1656 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT),1657 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1658 "vextdubvrx $RT, $RA, $RB, $RC",1659 IIC_VecGeneral,1660 [(set v2i64:$RT,1661 (int_ppc_altivec_vextdubvrx v16i8:$RA,1662 v16i8:$RB,1663 i32:$RC))]>;1664 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT),1665 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1666 "vextduhvlx $RT, $RA, $RB, $RC",1667 IIC_VecGeneral,1668 [(set v2i64:$RT,1669 (int_ppc_altivec_vextduhvlx v8i16:$RA,1670 v8i16:$RB,1671 i32:$RC))]>;1672 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT),1673 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1674 "vextduhvrx $RT, $RA, $RB, $RC",1675 IIC_VecGeneral,1676 [(set v2i64:$RT,1677 (int_ppc_altivec_vextduhvrx v8i16:$RA,1678 v8i16:$RB,1679 i32:$RC))]>;1680 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT),1681 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1682 "vextduwvlx $RT, $RA, $RB, $RC",1683 IIC_VecGeneral,1684 [(set v2i64:$RT,1685 (int_ppc_altivec_vextduwvlx v4i32:$RA,1686 v4i32:$RB,1687 i32:$RC))]>;1688 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT),1689 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1690 "vextduwvrx $RT, $RA, $RB, $RC",1691 IIC_VecGeneral,1692 [(set v2i64:$RT,1693 (int_ppc_altivec_vextduwvrx v4i32:$RA,1694 v4i32:$RB,1695 i32:$RC))]>;1696 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT),1697 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1698 "vextddvlx $RT, $RA, $RB, $RC",1699 IIC_VecGeneral,1700 [(set v2i64:$RT,1701 (int_ppc_altivec_vextddvlx v2i64:$RA,1702 v2i64:$RB,1703 i32:$RC))]>;1704 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT),1705 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),1706 "vextddvrx $RT, $RA, $RB, $RC",1707 IIC_VecGeneral,1708 [(set v2i64:$RT,1709 (int_ppc_altivec_vextddvrx v2i64:$RA,1710 v2i64:$RB,1711 i32:$RC))]>;1712 def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1713 "vpdepd $VD, $VA, $VB", IIC_VecGeneral,1714 [(set v2i64:$VD,1715 (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>;1716 def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1717 "vpextd $VD, $VA, $VB", IIC_VecGeneral,1718 [(set v2i64:$VD,1719 (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>;1720 def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),1721 "pdepd $RA, $RST, $RB", IIC_IntGeneral,1722 [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>;1723 def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),1724 "pextd $RA, $RST, $RB", IIC_IntGeneral,1725 [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>;1726 def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1727 "vcfuged $VD, $VA, $VB", IIC_VecGeneral,1728 [(set v2i64:$VD,1729 (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>;1730 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N),1731 "vgnb $RD, $VB, $N", IIC_VecGeneral,1732 [(set i64:$RD,1733 (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>;1734 def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),1735 "cfuged $RA, $RST, $RB", IIC_IntGeneral,1736 [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>;1737 def XXEVAL :1738 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,1739 vsrc:$XC, u8imm:$IMM),1740 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,1741 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,1742 v2i64:$XB, v2i64:$XC, timm:$IMM))]>;1743 def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1744 "vclzdm $VD, $VA, $VB", IIC_VecGeneral,1745 [(set v2i64:$VD,1746 (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>;1747 def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1748 "vctzdm $VD, $VA, $VB", IIC_VecGeneral,1749 [(set v2i64:$VD,1750 (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>;1751 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),1752 "cntlzdm $RA, $RST, $RB", IIC_IntGeneral,1753 [(set i64:$RA,1754 (int_ppc_cntlzdm i64:$RST, i64:$RB))]>;1755 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),1756 "cnttzdm $RA, $RST, $RB", IIC_IntGeneral,1757 [(set i64:$RA,1758 (int_ppc_cnttzdm i64:$RST, i64:$RB))]>;1759 def XXGENPCVBM :1760 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),1761 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;1762 def XXGENPCVHM :1763 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),1764 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;1765 def XXGENPCVWM :1766 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),1767 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;1768 def XXGENPCVDM :1769 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),1770 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;1771 def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),1772 "vclrlb $VD, $VA, $VB", IIC_VecGeneral,1773 [(set v16i8:$VD,1774 (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>;1775 def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),1776 "vclrrb $VD, $VA, $VB", IIC_VecGeneral,1777 [(set v16i8:$VD,1778 (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>;1779 def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1780 "vmulld $VD, $VA, $VB", IIC_VecGeneral,1781 [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>;1782 def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1783 "vmulhsw $VD, $VA, $VB", IIC_VecGeneral,1784 [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>;1785 def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1786 "vmulhuw $VD, $VA, $VB", IIC_VecGeneral,1787 [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>;1788 def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1789 "vmulhsd $VD, $VA, $VB", IIC_VecGeneral,1790 [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>;1791 def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1792 "vmulhud $VD, $VA, $VB", IIC_VecGeneral,1793 [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>;1794 def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1795 "vmodsw $VD, $VA, $VB", IIC_VecGeneral,1796 [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>;1797 def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1798 "vmoduw $VD, $VA, $VB", IIC_VecGeneral,1799 [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>;1800 def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1801 "vmodsd $VD, $VA, $VB", IIC_VecGeneral,1802 [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>;1803 def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1804 "vmodud $VD, $VA, $VB", IIC_VecGeneral,1805 [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>;1806 def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1807 "vdivsw $VD, $VA, $VB", IIC_VecGeneral,1808 [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>;1809 def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1810 "vdivuw $VD, $VA, $VB", IIC_VecGeneral,1811 [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>;1812 def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1813 "vdivsd $VD, $VA, $VB", IIC_VecGeneral,1814 [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>;1815 def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1816 "vdivud $VD, $VA, $VB", IIC_VecGeneral,1817 [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>;1818 def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1819 "vdivesw $VD, $VA, $VB", IIC_VecGeneral,1820 [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA,1821 v4i32:$VB))]>;1822 def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1823 "vdiveuw $VD, $VA, $VB", IIC_VecGeneral,1824 [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA,1825 v4i32:$VB))]>;1826 def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1827 "vdivesd $VD, $VA, $VB", IIC_VecGeneral,1828 [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA,1829 v2i64:$VB))]>;1830 def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1831 "vdiveud $VD, $VA, $VB", IIC_VecGeneral,1832 [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA,1833 v2i64:$VB))]>;1834 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),1835 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;1836 def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST),1837 "brh $RA, $RST", IIC_IntRotate, []>;1838 def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST),1839 "brw $RA, $RST", IIC_IntRotate,1840 [(set i32:$RA, (bswap i32:$RST))]>;1841 let isCodeGenOnly = 1 in {1842 def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST),1843 "brh $RA, $RST", IIC_IntRotate, []>;1844 def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST),1845 "brw $RA, $RST", IIC_IntRotate, []>;1846 }1847 def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST),1848 "brd $RA, $RST", IIC_IntRotate,1849 [(set i64:$RA, (bswap i64:$RST))]>;1850 1851 // The XFormMemOp flag for the following 8 instructions is set on1852 // the instruction format.1853 let mayLoad = 1, mayStore = 0 in {1854 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;1855 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;1856 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;1857 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;1858 }1859 1860 let mayLoad = 0, mayStore = 1 in {1861 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;1862 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;1863 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;1864 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;1865 }1866 1867 def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1868 "vmulesd $VD, $VA, $VB", IIC_VecGeneral,1869 [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA,1870 v2i64:$VB))]>;1871 def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1872 "vmuleud $VD, $VA, $VB", IIC_VecGeneral,1873 [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA,1874 v2i64:$VB))]>;1875 def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1876 "vmulosd $VD, $VA, $VB", IIC_VecGeneral,1877 [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA,1878 v2i64:$VB))]>;1879 def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1880 "vmuloud $VD, $VA, $VB", IIC_VecGeneral,1881 [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA,1882 v2i64:$VB))]>;1883 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),1884 "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral,1885 [(set v1i128:$RT, (int_ppc_altivec_vmsumcud1886 v2i64:$RA, v2i64:$RB, v1i128:$RC))]>;1887 def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1888 "vdivsq $VD, $VA, $VB", IIC_VecGeneral,1889 [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>;1890 def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1891 "vdivuq $VD, $VA, $VB", IIC_VecGeneral,1892 [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>;1893 def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1894 "vdivesq $VD, $VA, $VB", IIC_VecGeneral,1895 [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA,1896 v1i128:$VB))]>;1897 def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1898 "vdiveuq $VD, $VA, $VB", IIC_VecGeneral,1899 [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA,1900 v1i128:$VB))]>;1901 def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>;1902 def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>;1903 def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>;1904 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>;1905 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>;1906 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>;1907 def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1908 "vmodsq $VD, $VA, $VB", IIC_VecGeneral,1909 [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>;1910 def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),1911 "vmoduq $VD, $VA, $VB", IIC_VecGeneral,1912 [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>;1913 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB),1914 "vextsd2q $VD, $VB", IIC_VecGeneral,1915 [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>;1916 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),1917 "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>;1918 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),1919 "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>;1920 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",1921 [(set v1i128:$VD,1922 (int_ppc_altivec_vrlqnm v1i128:$VA,1923 v1i128:$VB))]>;1924 def VRLQMI : VXForm_1<69, (outs vrrc:$VD),1925 (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),1926 "vrlqmi $VD, $VA, $VB", IIC_VecFP,1927 [(set v1i128:$VD,1928 (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB,1929 v1i128:$VDi))]>,1930 RegConstraint<"$VDi = $VD">;1931 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;1932 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;1933 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", 1934 [(set v4i32:$VD, (PPCvsrq v4i32:$VA, v4i32:$VB))]>;1935 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;1936 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;1937 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;1938 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;1939 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;1940 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),1941 "lxvkq $XT, $UIM", IIC_VecGeneral, []>;1942}1943 1944let Predicates = [IsISA3_1, HasVSX] in {1945 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;1946 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;1947 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",1948 [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>;1949 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",1950 [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>;1951}1952 1953let Predicates = [IsISA3_1] in {1954 def WAITP10 : XForm_IMM2_IMM2<31, 30, (outs), (ins u2imm:$L, u2imm:$PL),1955 "wait $L $PL", IIC_LdStLoad, []>;1956 def SYNCP10 : XForm_IMM3_IMM2<31, 598, (outs), (ins u3imm:$L, u2imm:$SC),1957 "sync $L, $SC", IIC_LdStSync, []>;1958}1959 1960// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.1961// This is analogous to the CRNotPat multiclass but specifically for Power101962// and newer subtargets since the extended forms use Set Boolean instructions.1963// The first two anonymous patterns defined are actually a duplicate of those1964// in CRNotPat, but it is preferable to define both multiclasses as complete1965// ones rather than pulling that small common section out.1966multiclass P10ReverseSetBool<dag pattern, dag result> {1967 def : Pat<pattern, (crnot result)>;1968 def : Pat<(not pattern), result>;1969 1970 def : Pat<(i32 (zext pattern)),1971 (SETBCR result)>;1972 def : Pat<(i64 (zext pattern)),1973 (SETBCR8 result)>;1974 1975 def : Pat<(i32 (sext pattern)),1976 (SETNBCR result)>;1977 def : Pat<(i64 (sext pattern)),1978 (SETNBCR8 result)>;1979 1980 def : Pat<(i32 (anyext pattern)),1981 (SETBCR result)>;1982 def : Pat<(i64 (anyext pattern)),1983 (SETBCR8 result)>;1984}1985 1986multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,1987 ImmLeaf SExtTy, I Cmpi, I Cmpli,1988 I Cmp, I Cmpl> {1989 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),1990 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;1991 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),1992 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;1993 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),1994 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;1995 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),1996 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;1997 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),1998 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;1999 2000 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),2001 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;2002 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),2003 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;2004 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),2005 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;2006 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),2007 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;2008 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),2009 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;2010 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),2011 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;2012}2013 2014multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> {2015 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),2016 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;2017 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),2018 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;2019 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),2020 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;2021 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),2022 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;2023 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),2024 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;2025 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),2026 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;2027 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),2028 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;2029}2030 2031let Predicates = [IsISA3_1] in {2032 def : Pat<(i32 (zext i1:$in)),2033 (SETBC $in)>;2034 def : Pat<(i64 (zext i1:$in)),2035 (SETBC8 $in)>;2036 def : Pat<(i32 (sext i1:$in)),2037 (SETNBC $in)>;2038 def : Pat<(i64 (sext i1:$in)),2039 (SETNBC8 $in)>;2040 def : Pat<(i32 (anyext i1:$in)),2041 (SETBC $in)>;2042 def : Pat<(i64 (anyext i1:$in)),2043 (SETBC8 $in)>;2044 2045 // Instantiation of the set boolean reverse patterns for 32-bit integers.2046 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,2047 CMPWI, CMPLWI, CMPW, CMPLW>;2048 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),2049 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),2050 (LO16 imm:$imm)), sub_eq)>;2051 2052 // Instantiation of the set boolean reverse patterns for 64-bit integers.2053 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,2054 CMPDI, CMPLDI, CMPD, CMPLD>;2055 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),2056 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),2057 (LO16 imm:$imm)), sub_eq)>;2058}2059 2060// Instantiation of the set boolean reverse patterns for f32, f64, f128.2061let Predicates = [IsISA3_1, HasFPU] in {2062 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;2063 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;2064 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;2065}2066 2067//---------------------------- Anonymous Patterns ----------------------------//2068let Predicates = [IsISA3_1] in {2069 // Exploit vsrq instruction to optimize VSR(VSRO (input, vsro_byte_shift), vsr_bit_shift)2070 // to VSRQ(input, vsrq_bit_shift)2071 def : Pat<(VSRVSRO v4i32:$vA, v4i32:$vB), (VSRQ $vA, $vB)>;2072 // Exploit the vector multiply high instructions using intrinsics.2073 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),2074 (v4i32 (VMULHSW $vA, $vB))>;2075 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),2076 (v4i32 (VMULHUW $vA, $vB))>;2077 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),2078 (v2i64 (VMULHSD $vA, $vB))>;2079 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)),2080 (v2i64 (VMULHUD $vA, $vB))>;2081 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),2082 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;2083 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),2084 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;2085 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),2086 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;2087 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),2088 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;2089 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),2090 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;2091 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),2092 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;2093 def : Pat<(srl (bswap i32:$RS), (i32 16)),2094 (RLDICL_32 (BRH $RS), 0, 48)>;2095 def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))),2096 (RLDICL_32_64 (BRH $RS), 0, 48)>;2097 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),2098 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;2099 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),2100 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;2101 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),2102 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;2103 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),2104 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;2105 2106 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),2107 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;2108 2109 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),2110 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;2111}2112 2113let Predicates = [IsISA3_1, HasVSX] in {2114 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),2115 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;2116 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),2117 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;2118}2119 2120let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {2121 // Store element 0 of a VSX register to memory2122 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),2123 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>;2124 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),2125 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>;2126 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),2127 (STXVRWX $src, ForceXForm:$dst)>;2128 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),2129 (STXVRWX $src, ForceXForm:$dst)>;2130 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),2131 (STXVRDX $src, ForceXForm:$dst)>;2132 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),2133 (STXVRDX $src, ForceXForm:$dst)>;2134 // Load element 0 of a VSX register to memory2135 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))),2136 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>;2137 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))),2138 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>;2139 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src),2140 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;2141 }2142 2143let Predicates = [IsISA3_1, IsBigEndian] in {2144 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),2145 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;2146}2147 2148// FIXME: The swap is overkill when the shift amount is a constant.2149// We should just fix the constant in the DAG.2150let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {2151 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),2152 (v1i128 (VSLQ v1i128:$VRA,2153 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2154 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2155 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),2156 (v1i128 (VSLQ v1i128:$VRA,2157 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2158 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2159 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),2160 (v1i128 (VSRQ v1i128:$VRA,2161 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2162 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2163 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),2164 (v1i128 (VSRQ v1i128:$VRA,2165 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2166 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2167 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),2168 (v1i128 (VSRAQ v1i128:$VRA,2169 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2170 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2171 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),2172 (v1i128 (VSRAQ v1i128:$VRA,2173 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),2174 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;2175}2176 2177// =============================================================================2178// XXEVAL Instruction Pattern Definitions2179// =============================================================================2180//2181// XXEVAL instruction performs 256 different logical operations on three vector2182// operands using an 8-bit immediate value to select the operation.2183// Format: xxeval XT, XA, XB, XC, IMM2184// For example:2185// Equivalent function A?xor(B,C):and(B,C) is performed by2186// xxeval XT, XA, XB, XC, 222187//2188// REGISTER CLASS CONSTRAINTS:2189// - XXEVAL natively supports: VSRC register class [v4i32, v4f32, v2f64, v2i64]2190// - Other vector types [v16i8, v8i16] require COPY_TO_REGCLASS to/from VRRC2191// =============================================================================2192 2193class XXEvalPattern<ValueType Vt, dag InputPattern, bits<8> Imm>2194 : Pat<(Vt InputPattern),2195 !if(!or(!eq(Vt, v4i32), !eq(Vt, v2i64)),2196 // VSRC path: direct XXEVAL for v4i32 and v2i642197 (XXEVAL $vA, $vB, $vC, Imm),2198 // VRRC path: wrap with COPY_TO_REGCLASS for other types2199 (COPY_TO_REGCLASS(XXEVAL(COPY_TO_REGCLASS Vt:$vA, VSRC),2200 (COPY_TO_REGCLASS Vt:$vB, VSRC),2201 (COPY_TO_REGCLASS Vt:$vC, VSRC), Imm),2202 VRRC))> {}2203 2204// =============================================================================2205// PatFrags for Bitcast-Aware Vector bitwise Operations2206//2207// Each PatFrags defines TWO alternatives for pattern matcher to choose:2208// - Direct operation (for v4i32)2209// - Bitcast operation (for other types: v2i64, v16i8, v8i16)2210// =============================================================================2211 2212// Basic Binary Operations2213def VAnd2214 : PatFrags<(ops node:$a, node:$b), [(and node:$a, node:$b),2215 (bitconvert(and2216 (v4i32(bitconvert node:$a)),2217 (v4i32(bitconvert node:$b))))]>;2218 2219def VXor2220 : PatFrags<(ops node:$a, node:$b), [(xor node:$a, node:$b),2221 (bitconvert(xor2222 (v4i32(bitconvert node:$a)),2223 (v4i32(bitconvert node:$b))))]>;2224 2225def VOr : PatFrags<(ops node:$a, node:$b), [(or node:$a, node:$b),2226 (bitconvert(or2227 (v4i32(bitconvert node:$a)),2228 (v4i32(bitconvert node:$b))))]>;2229 2230def VNot2231 : PatFrags<(ops node:$a), [(vnot node:$a),2232 (bitconvert(vnot(v4i32(bitconvert node:$a))))]>;2233 2234// Derived bitwise operations2235// Vector NOR operation (not(or))2236def VNor2237 : PatFrags<(ops node:$a, node:$b), [(vnot(or node:$a, node:$b)),2238 (bitconvert(vnot(or2239 (v4i32(bitconvert node:$a)),2240 (v4i32(bitconvert node:$b)))))]>;2241 2242// Vector EQV operation (not(xor))2243def VEqv2244 : PatFrags<(ops node:$a, node:$b), [(vnot(xor node:$a, node:$b)),2245 (bitconvert(vnot(xor2246 (v4i32(bitconvert node:$a)),2247 (v4i32(bitconvert node:$b)))))]>;2248 2249// Vector NAND operation (not(and))2250def VNand2251 : PatFrags<(ops node:$a, node:$b), [(vnot(and node:$a, node:$b)),2252 (bitconvert(vnot(and2253 (v4i32(bitconvert node:$a)),2254 (v4i32(bitconvert node:$b)))))]>;2255 2256// =============================================================================2257// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectAnd2258// This class matches the equivalent Ternary Operation: A ? f(B,C) : AND(B,C)2259// and emit the corresponding xxeval instruction with the imm value.2260//2261// The patterns implement xxeval vector select operations where:2262// - A is the selector vector2263// - f(B,C) is the "true" case op on vectors B and C (XOR, NOR, EQV, or NOT)2264// - AND(B,C) is the "false" case op on vectors B and C2265// =============================================================================2266multiclass XXEvalTernarySelectAnd<ValueType Vt> {2267 // Pattern: A ? XOR(B,C) : AND(B,C) XXEVAL immediate value: 222268 def : XXEvalPattern<2269 Vt, (vselect Vt:$vA, (VXor Vt:$vB, Vt:$vC), (VAnd Vt:$vB, Vt:$vC)),2270 22>;2271 2272 // Pattern: A ? NOR(B,C) : AND(B,C) XXEVAL immediate value: 242273 def : XXEvalPattern<2274 Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), (VAnd Vt:$vB, Vt:$vC)),2275 24>;2276 2277 // Pattern: A ? EQV(B,C) : AND(B,C) XXEVAL immediate value: 252278 def : XXEvalPattern<2279 Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), (VAnd Vt:$vB, Vt:$vC)),2280 25>;2281 2282 // Pattern: A ? NOT(C) : AND(B,C) XXEVAL immediate value: 262283 def : XXEvalPattern<2284 Vt, (vselect Vt:$vA, (VNot Vt:$vC), (VAnd Vt:$vB, Vt:$vC)), 26>;2285 2286 // Pattern: A ? NOT(B) : AND(B,C) XXEVAL immediate value: 282287 def : XXEvalPattern<2288 Vt, (vselect Vt:$vA, (VNot Vt:$vB), (VAnd Vt:$vB, Vt:$vC)), 28>;2289}2290 2291// =============================================================================2292// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectB2293// This class matches the equivalent Ternary Operation: A ? f(B,C) : B2294// and emit the corresponding xxeval instruction with the imm value.2295//2296// The patterns implement xxeval vector select operations where:2297// - A is the selector vector2298// - f(B,C) is the "true" case op on vectors B and C (AND, NOR, EQV, NAND)2299// - B is the "false" case operand (vector B)2300//2301// Note: Patterns (A? C : B) and (A? not(C) : B) are not considered2302// for XXEVAL instruction (4 Cycle) as XXSEL (3 cycle) instruction performs 2303// better.2304// =============================================================================2305multiclass XXEvalTernarySelectB<ValueType Vt>{2306 // Pattern: (A ? AND(B,C) : B) XXEVAL immediate value: 492307 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), Vt:$vB), 49>;2308 // Pattern: (A ? NOR(B,C) : B) XXEVAL immediate value: 562309 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), Vt:$vB), 56>;2310 // Pattern: (A ? EQV(B,C) : B) XXEVAL immediate value: 572311 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), Vt:$vB), 57>;2312 // Pattern: (A ? NAND(B,C) : B) XXEVAL immediate value: 622313 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), Vt:$vB), 62>;2314}2315 2316// =============================================================================2317// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectC2318// This class matches the equivalent Ternary Operation: A ? f(B,C) : C2319// and emit the corresponding xxeval instruction with the imm value.2320//2321// The patterns implement xxeval vector select operations where:2322// - A is the selector vector2323// - f(B,C) is the "true" case op on vectors B and C (AND, NOR, EQV, NAND)2324// - C is the "false" case operand (vector C)2325//2326// Note: Patterns (A? B : C) and (A? not(B) : C) are not considered2327// for XXEVAL instruction (4 Cycle) as XXSEL (3 cycle) instruction performs 2328// better.2329// =============================================================================2330multiclass XXEvalTernarySelectC<ValueType Vt>{2331 // Pattern: (A ? AND(B,C) : C) XXEVAL immediate value: 812332 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), Vt:$vC), 81>;2333 // Pattern: (A ? NOR(B,C) : C) XXEVAL immediate value: 882334 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), Vt:$vC), 88>;2335 // Pattern: (A ? EQV(B,C) : C) XXEVAL immediate value: 892336 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), Vt:$vC), 89>;2337 // Pattern: (A ? NAND(B,C) : C) XXEVAL immediate value: 942338 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), Vt:$vC), 94>;2339}2340 2341// =============================================================================2342// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectXor2343// This class matches the equivalent Ternary Operation: A ? f(B,C) : XOR(B,C)2344// and emit the corresponding xxeval instruction with the imm value.2345//2346// The patterns implement xxeval vector select operations where:2347// - A is the selector vector2348// - f(B,C) is the "true" case op in set {B, C, AND(B,C), OR(B,C), NOR(B,C)} 2349// - XOR(B,C) is the "false" case op on vectors B and C2350// =============================================================================2351multiclass XXEvalTernarySelectXor<ValueType Vt> {2352 // Pattern: A ? AND(B,C) : XOR(B,C) XXEVAL immediate value: 972353 def : XXEvalPattern<2354 Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), (VXor Vt:$vB, Vt:$vC)),2355 97>;2356 2357 // Pattern: A ? B : XOR(B,C) XXEVAL immediate value: 992358 def : XXEvalPattern<2359 Vt, (vselect Vt:$vA, Vt:$vB, (VXor Vt:$vB, Vt:$vC)),2360 99>;2361 2362 // Pattern: A ? C : XOR(B,C) XXEVAL immediate value: 1012363 def : XXEvalPattern<2364 Vt, (vselect Vt:$vA, Vt:$vC, (VXor Vt:$vB, Vt:$vC)),2365 101>;2366 2367 // Pattern: A ? OR(B,C) : XOR(B,C) XXEVAL immediate value: 1032368 def : XXEvalPattern<2369 Vt, (vselect Vt:$vA, (VOr Vt:$vB, Vt:$vC), (VXor Vt:$vB, Vt:$vC)),2370 103>;2371 2372 // Pattern: A ? NOR(B,C) : XOR(B,C) XXEVAL immediate value: 1042373 def : XXEvalPattern<2374 Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), (VXor Vt:$vB, Vt:$vC)),2375 104>;2376}2377 2378// =============================================================================2379// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectOr2380// This class matches the equivalent Ternary Operation: A ? f(B,C) : OR(B,C)2381// and emit the corresponding xxeval instruction with the imm value.2382//2383// The patterns implement xxeval vector select operations where:2384// - A is the selector vector2385// - f(B,C) is the "true" case op in set {B, C, AND(B,C), EQV(B,C), NOT(B), 2386// NOT(C), NAND(B,C)} 2387// - OR(B,C) is the "false" case op on vectors B and C2388// =============================================================================2389multiclass XXEvalTernarySelectOr<ValueType Vt> {2390 // Pattern: A ? AND(B,C) : OR(B,C) XXEVAL immediate value: 1132391 def : XXEvalPattern<2392 Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), (VOr Vt:$vB, Vt:$vC)),2393 113>;2394 2395 // Pattern: A ? B : OR(B,C) XXEVAL immediate value: 1152396 def : XXEvalPattern<2397 Vt, (vselect Vt:$vA, Vt:$vB, (VOr Vt:$vB, Vt:$vC)),2398 115>;2399 2400 // Pattern: A ? C : OR(B,C) XXEVAL immediate value: 1172401 def : XXEvalPattern<2402 Vt, (vselect Vt:$vA, Vt:$vC, (VOr Vt:$vB, Vt:$vC)),2403 117>;2404 2405 // Pattern: A ? EQV(B,C) : OR(B,C) XXEVAL immediate value: 1212406 def : XXEvalPattern<2407 Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), (VOr Vt:$vB, Vt:$vC)),2408 121>;2409 2410 // Pattern: A ? NOT(C) : OR(B,C) XXEVAL immediate value: 1222411 def : XXEvalPattern<2412 Vt, (vselect Vt:$vA, (VNot Vt:$vC), (VOr Vt:$vB, Vt:$vC)),2413 122>;2414 2415 // Pattern: A ? NOT(B) : OR(B,C) XXEVAL immediate value: 1242416 def : XXEvalPattern<2417 Vt, (vselect Vt:$vA, (VNot Vt:$vB), (VOr Vt:$vB, Vt:$vC)),2418 124>;2419 2420 // Pattern: A ? NAND(B,C) : OR(B,C) XXEVAL immediate value: 1262421 def : XXEvalPattern<2422 Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), (VOr Vt:$vB, Vt:$vC)),2423 126>;2424}2425 2426// =============================================================================2427// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectNor2428// This class matches the equivalent Ternary Operation: A ? f(B,C) : NOR(B,C)2429// and emit the corresponding xxeval instruction with the imm value.2430//2431// The patterns implement xxeval vector select operations where:2432// - A is the selector vector2433// - f(B,C) is the "true" case op in set {B, C, AND(B,C), XOR(B,C), NOT(C),2434// NOT(B), NAND(B,C)}2435// - C is the "false" case op NOR(B,C)2436// =============================================================================2437multiclass XXEvalTernarySelectNor<ValueType Vt>{2438 // Pattern: (A ? AND(B,C) : NOR(B,C)) XXEVAL immediate value: 1292439 def : XXEvalPattern<2440 Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), (VNor Vt:$vB, Vt:$vC)),2441 129>;2442 2443 // Pattern: (A ? B : NOR(B,C)) XXEVAL immediate value: 1312444 def : XXEvalPattern<Vt, (vselect Vt:$vA, Vt:$vB, (VNor Vt:$vB, Vt:$vC)),131>;2445 2446 // Pattern: (A ? C : NOR(B,C)) XXEVAL immediate value: 1332447 def : XXEvalPattern<2448 Vt, (vselect Vt:$vA, Vt:$vC, (VNor Vt:$vB, Vt:$vC)),2449 133>;2450 2451 // Pattern: (A ? XOR(B,C) : NOR(B,C)) XXEVAL immediate value: 1342452 def : XXEvalPattern<2453 Vt, (vselect Vt:$vA, (VXor Vt:$vB, Vt:$vC), (VNor Vt:$vB, Vt:$vC)),2454 134>;2455 2456 // Pattern: (A ? NOT(C) : NOR(B,C)) XXEVAL immediate value: 1382457 def : XXEvalPattern<2458 Vt, (vselect Vt:$vA, (VNot Vt:$vC), (VNor Vt:$vB, Vt:$vC)),2459 138>;2460 2461 // Pattern: (A ? NOT(B) : NOR(B,C)) XXEVAL immediate value: 1402462 def : XXEvalPattern<2463 Vt, (vselect Vt:$vA, (VNot Vt:$vB), (VNor Vt:$vB, Vt:$vC)),2464 140>;2465 2466 // Pattern: (A ? NAND(B,C) : NOR(B,C)) XXEVAL immediate value: 1422467 def : XXEvalPattern<2468 Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), (VNor Vt:$vB, Vt:$vC)),2469 142>;2470}2471 2472// =============================================================================2473// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectEqv2474// This class matches the equivalent Ternary Operation: A ? f(B,C) : EQV(B,C)2475// and emit the corresponding xxeval instruction with the imm value.2476//2477// The patterns implement xxeval vector select operations where:2478// - A is the selector vector2479// - f(B,C) is the "true" case op in set {OR(B,C), NOR(B,C), NAND(B,C), NOT(B),2480// NOT(C)}2481// - C is the "false" case op EQV(B,C)2482// =============================================================================2483multiclass XXEvalTernarySelectEqv<ValueType Vt>{2484 // Pattern: (A ? OR(B,C) : EQV(B,C)) XXEVAL immediate value: 1512485 def : XXEvalPattern<2486 Vt, (vselect Vt:$vA, (VOr Vt:$vB, Vt:$vC), (VEqv Vt:$vB, Vt:$vC)),2487 151>;2488 2489 // Pattern: (A ? NOR(B,C) : EQV(B,C)) XXEVAL immediate value: 1522490 def : XXEvalPattern<2491 Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), (VEqv Vt:$vB, Vt:$vC)),2492 152>;2493 2494 // Pattern: (A ? NOT(C) : EQV(B,C)) XXEVAL immediate value: 1542495 def : XXEvalPattern<2496 Vt, (vselect Vt:$vA, (VNot Vt:$vC), (VEqv Vt:$vB, Vt:$vC)),2497 154>;2498 2499 // Pattern: (A ? NAND(B,C) : EQV(B,C)) XXEVAL immediate value: 1582500 def : XXEvalPattern<2501 Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), (VEqv Vt:$vB, Vt:$vC)),2502 158>;2503}2504 2505// =============================================================================2506// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectNotC2507// This class matches the equivalent Ternary Operation: A ? f(B,C) : NOT(C)2508// and emit the corresponding xxeval instruction with the imm value.2509//2510// The patterns implement xxeval vector select operations where:2511// - A is the selector vector2512// - f(B,C) is the "true" case op in set {AND(B,C), OR(B,C), XOR(B,C), NAND(B,C),2513// B, NOT(B)}2514// - C is the "false" case op NOT(C)2515// =============================================================================2516multiclass XXEvalTernarySelectNotC<ValueType Vt>{2517 // Pattern: (A ? AND(B,C) : NOT(C)) XXEVAL immediate value: 1612518 def : XXEvalPattern<2519 Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), (VNot Vt:$vC)), 161>;2520 2521 // Pattern: (A ? B : NOT(C)) XXEVAL immediate value: 1632522 def : XXEvalPattern<Vt, (vselect Vt:$vA, Vt:$vB, (VNot Vt:$vC)), 163>;2523 2524 // Pattern: (A ? XOR(B,C) : NOT(C)) XXEVAL immediate value: 1662525 def : XXEvalPattern<2526 Vt, (vselect Vt:$vA, (VXor Vt:$vB, Vt:$vC), (VNot Vt:$vC)), 166>;2527 2528 // Pattern: (A ? OR(B,C) : NOT(C)) XXEVAL immediate value: 1672529 def : XXEvalPattern<2530 Vt, (vselect Vt:$vA, (VOr Vt:$vB, Vt:$vC), (VNot Vt:$vC)), 167>;2531 2532 // Pattern: (A ? NOT(B) : NOT(C)) XXEVAL immediate value: 1722533 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNot Vt:$vB), (VNot Vt:$vC)), 172>;2534 2535 // Pattern: (A ? NAND(B,C) : NOT(C)) XXEVAL immediate value: 1742536 def : XXEvalPattern<2537 Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), (VNot Vt:$vC)), 174>;2538}2539 2540// =============================================================================2541// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectNotB2542// This class matches the equivalent Ternary Operation: A ? f(B,C) : NOT(B)2543// and emit the corresponding xxeval instruction with the imm value.2544//2545// The patterns implement xxeval vector select operations where:2546// - A is the selector vector2547// - f(B,C) is the "true" case op in set {AND(B,C), OR(B,C), XOR(B,C), NAND(B,C),2548// C, NOT(B)}2549// - C is the "false" case op NOT(B)2550// =============================================================================2551multiclass XXEvalTernarySelectNotB<ValueType Vt>{2552 // Pattern: (A ? AND(B,C) : NOT(B)) XXEVAL immediate value: 1932553 def : XXEvalPattern<2554 Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), (VNot Vt:$vB)), 193>;2555 2556 // Pattern: (A ? C : NOT(B)) XXEVAL immediate value: 1972557 def : XXEvalPattern<Vt, (vselect Vt:$vA, Vt:$vC, (VNot Vt:$vB)), 197>;2558 2559 // Pattern: (A ? XOR(B,C) : NOT(B)) XXEVAL immediate value: 1982560 def : XXEvalPattern<2561 Vt, (vselect Vt:$vA, (VXor Vt:$vB, Vt:$vC), (VNot Vt:$vB)), 198>;2562 2563 // Pattern: (A ? OR(B,C) : NOT(B)) XXEVAL immediate value: 1992564 def : XXEvalPattern<2565 Vt, (vselect Vt:$vA, (VOr Vt:$vB, Vt:$vC), (VNot Vt:$vB)), 199>;2566 2567 // Pattern: (A ? NOT(C) : NOT(B)) XXEVAL immediate value: 2022568 def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNot Vt:$vC), (VNot Vt:$vB)), 202>;2569 2570 // Pattern: (A ? NAND(B,C) : NOT(B)) XXEVAL immediate value: 2062571 def : XXEvalPattern<2572 Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), (VNot Vt:$vB)), 206>;2573}2574 2575// =============================================================================2576// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectNand2577// This class matches the equivalent Ternary Operation: A ? f(B,C) : NAND(B,C)2578// and emit the corresponding xxeval instruction with the imm value.2579//2580// The patterns implement xxeval vector select operations where:2581// - A is the selector vector2582// - f(B,C) is the "true" case op in set {B, C, XOR(B,C), OR(B,C), EQV(B,C)}2583// - C is the "false" case op NAND(B,C)2584// =============================================================================2585multiclass XXEvalTernarySelectNand<ValueType Vt>{2586 // Pattern: (A ? B : NAND(B,C)) XXEVAL immediate value: 2272587 def : XXEvalPattern<2588 Vt, (vselect Vt:$vA, Vt:$vB, (VNand Vt:$vB, Vt:$vC)), 227>;2589 2590 // Pattern: (A ? C : NAND(B,C)) XXEVAL immediate value: 2292591 def : XXEvalPattern<2592 Vt, (vselect Vt:$vA, Vt:$vC, (VNand Vt:$vB, Vt:$vC)), 229>;2593 2594 // Pattern: (A ? XOR(B,C) : NAND(B,C)) XXEVAL immediate value: 2302595 def : XXEvalPattern<2596 Vt, (vselect Vt:$vA, (VXor Vt:$vB, Vt:$vC), (VNand Vt:$vB, Vt:$vC)),2597 230>;2598 2599 // Pattern: (A ? OR(B,C) : NAND(B,C)) XXEVAL immediate value: 2312600 def : XXEvalPattern<2601 Vt, (vselect Vt:$vA, (VOr Vt:$vB, Vt:$vC), (VNand Vt:$vB, Vt:$vC)),2602 231>;2603 2604 // Pattern: (A ? EQV(B,C) : NAND(B,C)) XXEVAL immediate value: 2332605 def : XXEvalPattern<2606 Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), (VNand Vt:$vB, Vt:$vC)),2607 233>;2608}2609 2610let Predicates = [PrefixInstrs, HasP10Vector] in {2611 let AddedComplexity = 400 in {2612 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,2613 i32immNonAllOneNonZero:$A,2614 i32immNonAllOneNonZero:$A,2615 i32immNonAllOneNonZero:$A)),2616 (v4i32 (XXSPLTIW imm:$A))>;2617 def : Pat<(f32 nzFPImmAsi32:$A),2618 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),2619 VSFRC)>;2620 def : Pat<(f64 nzFPImmAsi32:$A),2621 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),2622 VSFRC)>;2623 2624 // To replace constant pool with XXSPLTI32DX for scalars.2625 def : Pat<(f32 nzFPImmAsi64:$A),2626 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,2627 (getFPAs64BitIntHi $A)),2628 1, (getFPAs64BitIntLo $A)),2629 VSSRC)>;2630 2631 def : Pat<(f64 nzFPImmAsi64:$A),2632 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,2633 (getFPAs64BitIntHi $A)),2634 1, (getFPAs64BitIntLo $A)),2635 VSFRC)>;2636 2637 // Anonymous patterns for XXEVAL2638 // AND2639 // and(A, B, C)2640 def : XXEvalPattern<v4i32, (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;2641 // and(A, xor(B, C))2642 def : XXEvalPattern<v4i32, (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;2643 // and(A, or(B, C))2644 def : XXEvalPattern<v4i32, (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;2645 // and(A, nor(B, C))2646 def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;2647 // and(A, eqv(B, C))2648 def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;2649 // and(A, nand(B, C))2650 def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;2651 2652 // NAND2653 // nand(A, B, C)2654 def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),2655 !sub(255, 1)>;2656 // nand(A, xor(B, C))2657 def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),2658 !sub(255, 6)>;2659 // nand(A, or(B, C))2660 def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),2661 !sub(255, 7)>;2662 // nand(A, nor(B, C))2663 def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),2664 !sub(255, 8)>;2665 // nand(A, eqv(B, C))2666 def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),2667 !sub(255, 9)>;2668 // nand(A, nand(B, C))2669 def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),2670 !sub(255, 14)>;2671 2672 // EQV2673 // (eqv A, B, C)2674 def : XXEvalPattern<v4i32, (or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),2675 (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),2676 150>;2677 // (eqv A, (and B, C))2678 def : XXEvalPattern<v4i32, (vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;2679 // (eqv A, (or B, C))2680 def : XXEvalPattern<v4i32, (vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;2681 2682 // NOR2683 // (nor A, B, C)2684 def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;2685 // (nor A, (and B, C))2686 def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;2687 // (nor A, (eqv B, C))2688 def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;2689 // (nor A, (nand B, C))2690 def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;2691 // (nor A, (nor B, C))2692 def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;2693 // (nor A, (xor B, C))2694 def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;2695 2696 // OR2697 // (or A, B, C)2698 def : XXEvalPattern<v4i32, (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;2699 // (or A, (and B, C))2700 def : XXEvalPattern<v4i32, (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;2701 // (or A, (eqv B, C))2702 def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;2703 // (or A, (nand B, C))2704 def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;2705 // (or A, (nor B, C))2706 def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;2707 // (or A, (xor B, C))2708 def : XXEvalPattern<v4i32, (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;2709 2710 // XOR2711 // (xor A, B, C)2712 def : XXEvalPattern<v4i32, (xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;2713 // (xor A, (and B, C))2714 def : XXEvalPattern<v4i32, (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;2715 // (xor A, (or B, C))2716 def : XXEvalPattern<v4i32, (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;2717 2718 // XXEval Patterns for ternary Operations.2719 foreach Ty = [v4i32, v2i64, v8i16, v16i8] in {2720 defm : XXEvalTernarySelectAnd<Ty>;2721 defm : XXEvalTernarySelectB<Ty>;2722 defm : XXEvalTernarySelectC<Ty>;2723 defm : XXEvalTernarySelectXor<Ty>;2724 defm : XXEvalTernarySelectOr<Ty>;2725 defm : XXEvalTernarySelectNor<Ty>;2726 defm : XXEvalTernarySelectEqv<Ty>;2727 defm : XXEvalTernarySelectNotC<Ty>;2728 defm : XXEvalTernarySelectNotB<Ty>;2729 defm : XXEvalTernarySelectNand<Ty>;2730 }2731 2732 // Anonymous patterns to select prefixed VSX loads and stores.2733 // Load / Store f1282734 def : Pat<(f128 (load PDForm:$src)),2735 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>;2736 def : Pat<(store f128:$XS, PDForm:$dst),2737 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>;2738 2739 // Load / Store v4i322740 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>;2741 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;2742 2743 // Load / Store v2i642744 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>;2745 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;2746 2747 // Load / Store v4f322748 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>;2749 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;2750 2751 // Load / Store v2f642752 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;2753 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;2754 2755 // Cases For PPCstore_scal_int_from_vsr2756 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8),2757 (PSTXSD $src, PDForm:$dst)>;2758 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8),2759 (PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>;2760 }2761 2762 2763 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;2764 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;2765 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),2766 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),2767 (COPY_TO_REGCLASS $B, VSRC),2768 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;2769 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),2770 (COPY_TO_REGCLASS2771 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),2772 (COPY_TO_REGCLASS $B, VSRC),2773 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;2774 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),2775 (COPY_TO_REGCLASS2776 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),2777 (COPY_TO_REGCLASS $B, VSRC),2778 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;2779 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),2780 (XXBLENDVW $A, $B, $C)>;2781 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),2782 (XXBLENDVD $A, $B, $C)>;2783}2784 2785let Predicates = [PrefixInstrs] in {2786 // Anonymous patterns to select prefixed loads and stores.2787 // Load i322788 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;2789 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>;2790 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>;2791 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>;2792 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>;2793 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>;2794 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>;2795 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>;2796 2797 // Store i322798 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>;2799 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>;2800 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>;2801 2802 // Load i642803 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;2804 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;2805 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;2806 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;2807 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;2808 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;2809 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>;2810 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;2811 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;2812 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>;2813 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>;2814 2815 // Store i642816 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>;2817 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;2818 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;2819 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;2820 2821 // Atomic Load2822 def : Pat<(i32 (atomic_load_azext_8 PDForm:$src)), (PLBZ memri34:$src)>;2823 def : Pat<(i32 (atomic_load_azext_16 PDForm:$src)), (PLHZ memri34:$src)>;2824 def : Pat<(i32 (atomic_load_nonext_32 PDForm:$src)), (PLWZ memri34:$src)>;2825 def : Pat<(i64 (atomic_load_nonext_64 PDForm:$src)), (PLD memri34:$src)>;2826 2827 // Atomic Store2828 def : Pat<(atomic_store_8 i32:$RS, PDForm:$dst), (PSTB $RS, memri34:$dst)>;2829 def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>;2830 def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>;2831 def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>;2832}2833 2834let Predicates = [PrefixInstrs, HasFPU] in {2835 // Load / Store f322836 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;2837 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;2838 2839 // Load / Store f642840 def : Pat<(f64 (extloadf32 PDForm:$src)),2841 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;2842 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;2843 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;2844 // Prefixed fpext to v2f642845 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),2846 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;2847 2848}2849 2850def InsertEltShift {2851 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32));2852 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);2853 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);2854 dag Left1 = (RLWINM $rB, 1, 0, 30);2855 dag Left2 = (RLWINM $rB, 2, 0, 29);2856 dag Left3 = (RLWINM8 $rB, 3, 0, 28);2857}2858 2859let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {2860 // Indexed vector insert element2861 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),2862 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>;2863 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),2864 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;2865 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),2866 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;2867 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),2868 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;2869 2870 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),2871 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;2872 2873 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)),2874 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;2875 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),2876 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;2877 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),2878 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;2879 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),2880 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;2881 let AddedComplexity = 400 in {2882 // Immediate vector insert element2883 foreach Idx = [0, 1, 2, 3] in {2884 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)),2885 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>;2886 }2887 foreach i = [0, 1] in2888 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))),2889 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;2890 }2891}2892 2893let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {2894 // Indexed vector insert element2895 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)),2896 (VINSBLX $vDi, $rB, $rA)>;2897 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)),2898 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>;2899 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)),2900 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>;2901 2902 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)),2903 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>;2904}2905 2906let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {2907 // Indexed vector insert element2908 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),2909 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>;2910 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),2911 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;2912 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),2913 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;2914 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),2915 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;2916 2917 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),2918 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;2919 2920 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)),2921 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;2922 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),2923 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;2924 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),2925 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;2926 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),2927 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;2928}2929 2930let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {2931 // Immediate vector insert element2932 foreach Ty = [i32, i64] in {2933 foreach Idx = [0, 1, 2, 3] in {2934 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))),2935 (VINSW $vDi, !mul(Idx, 4), $rA)>;2936 }2937 }2938 2939 foreach Idx = [0, 1] in2940 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),2941 (VINSD $vDi, !mul(Idx, 8), $rA)>;2942}2943 2944 2945//===----------------------------------------------------------------------===//2946// PowerPC ISA 3.1 Extended Mnemonics.2947//2948 2949let Predicates = [IsISA3_1] in {2950 def : InstAlias<"wait", (WAITP10 0, 0)>;2951 def : InstAlias<"wait 0", (WAITP10 0, 0), 0>;2952 def : InstAlias<"wait 1", (WAITP10 1, 0), 0>;2953 def : InstAlias<"waitrsv", (WAITP10 1, 0)>;2954 def : InstAlias<"pause_short", (WAITP10 2, 0), 0>;2955 2956 def : InstAlias<"sync", (SYNCP10 0, 0)>;2957 def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>;2958 def : InstAlias<"wsync", (SYNCP10 1, 0), 0>;2959 def : InstAlias<"ptesync", (SYNCP10 2, 0)>;2960 def : InstAlias<"phwsync", (SYNCP10 4, 0)>;2961 def : InstAlias<"plwsync", (SYNCP10 5, 0)>;2962 def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>;2963 def : InstAlias<"stncisync", (SYNCP10 1, 1)>;2964 def : InstAlias<"stcisync", (SYNCP10 0, 2)>;2965 def : InstAlias<"stsync", (SYNCP10 0, 3)>;2966 2967 def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;2968}2969 2970let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {2971 let Interpretation64Bit = 1 in {2972 def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),2973 (ins g8rc_nox0:$RA, s34imm:$SI),2974 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;2975 def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),2976 (ins s34imm_pcrel:$SI),2977 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel;2978 }2979 2980 def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI",2981 (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;2982 2983 def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),2984 (ins gprc_nor0:$RA, s34imm:$SI),2985 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;2986 def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),2987 (ins s34imm_pcrel:$SI),2988 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel;2989}2990