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1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the VSX extension to the PowerPC instruction set.10//11//===----------------------------------------------------------------------===//12 13// *********************************** NOTE ***********************************14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **15// ** which VMX and VSX instructions are lane-sensitive and which are not. **16// ** A lane-sensitive instruction relies, implicitly or explicitly, on **17// ** whether lanes are numbered from left to right. An instruction like **18// ** VADDFP is not lane-sensitive, because each lane of the result vector **19// ** relies only on the corresponding lane of the source vectors. However, **20// ** an instruction like VMULESB is lane-sensitive, because "even" and **21// ** "odd" lanes are different for big-endian and little-endian numbering. **22// ** **23// ** When adding new VMX and VSX instructions, please consider whether they **24// ** are lane-sensitive. If so, they must be added to a switch statement **25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **26// ****************************************************************************27 28// *********************************** NOTE ***********************************29// ** When adding new anonymous patterns to this file, please add them to **30// ** the section titled Anonymous Patterns. Chances are that the existing **31// ** predicate blocks already contain a combination of features that you **32// ** are after. There is a list of blocks at the top of the section. If **33// ** you definitely need a new combination of predicates, please add that **34// ** combination to the list. **35// ** File Structure: **36// ** - Custom PPCISD node definitions **37// ** - Predicate definitions: predicates to specify the subtargets for **38// ** which an instruction or pattern can be emitted. **39// ** - Instruction formats: classes instantiated by the instructions. **40// ** These generally correspond to instruction formats in section 1.6 of **41// ** the ISA document. **42// ** - Instruction definitions: the actual definitions of the instructions **43// ** often including input patterns that they match. **44// ** - Helper DAG definitions: We define a number of dag objects to use as **45// ** input or output patterns for consciseness of the code. **46// ** - Anonymous patterns: input patterns that an instruction matches can **47// ** often not be specified as part of the instruction definition, so an **48// ** anonymous pattern must be specified mapping an input pattern to an **49// ** output pattern. These are generally guarded by subtarget predicates. **50// ** - Instruction aliases: used to define extended mnemonics for assembly **51// ** printing (for example: xxswapd for xxpermdi with 0x2 as the imm). **52// ****************************************************************************53 54def SDT_PPCldvsxlh : SDTypeProfile<1, 1, [55 SDTCisVT<0, v4f32>, SDTCisPtrTy<1>56]>;57 58def SDT_PPCfpexth : SDTypeProfile<1, 2, [59 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>60]>;61 62def SDT_PPCldsplat : SDTypeProfile<1, 1, [63 SDTCisVec<0>, SDTCisPtrTy<1>64]>;65 66// Little-endian-specific nodes.67def SDT_PPClxvd2x : SDTypeProfile<1, 1, [68 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>69]>;70def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [71 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>72]>;73def SDT_PPCxxswapd : SDTypeProfile<1, 1, [74 SDTCisSameAs<0, 1>75]>;76def SDTVecConv : SDTypeProfile<1, 2, [77 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>78]>;79def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [80 SDTCisVec<0>, SDTCisPtrTy<1>81]>;82def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [83 SDTCisVec<0>, SDTCisPtrTy<1>84]>;85 86def SDT_PPCxxperm : SDTypeProfile<1, 3, [87 SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>,88 SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>;89//--------------------------- Custom PPC nodes -------------------------------//90 91// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.92// Maps directly to an lxvd2x instruction that will be followed by93// an xxswapd.94def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,95 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;96 97// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.98// Maps directly to an stxvd2x instruction that will be preceded by99// an xxswapd.100def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,101 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;102 103// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.104// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on105// the vector type to load vector in big-endian element order.106def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;108 109// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.110// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on111// the vector type to store vector in big-endian element order.112def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,113 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;114 115// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little116// endian. Maps to an xxswapd instruction that corrects an lxvd2x117// or stxvd2x instruction. The chain is necessary because the118// sequence replaces a load and needs to provide the same number119// of outputs.120def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;121 122// Direct move from a VSX register to a GPR123def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;124 125// Direct move from a GPR to a VSX register (algebraic)126def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;127 128// Direct move from a GPR to a VSX register (zero)129def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;130 131// Extract a subvector from signed integer vector and convert to FP.132// It is primarily used to convert a (widened) illegal integer vector133// type to a legal floating point vector type.134// For example v2i32 -> widened to v4i32 -> v2f64135def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;136 137// Extract a subvector from unsigned integer vector and convert to FP.138// As with SINT_VEC_TO_FP, used for converting illegal types.139def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;140 141// An SDNode for swaps that are not associated with any loads/stores142// and thereby have no chain.143def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;144 145// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or146// lower (IDX=1) half of v4f32 to v2f64.147def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;148 149// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a150// v2f32 value into the lower half of a VSR register.151def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,152 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;153 154// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory155// instructions such as LXVDSX, LXVWSX.156def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,157 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;158 159// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory160// that zero-extends.161def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat,162 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;163 164// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory165// that sign-extends.166def PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat,167 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;168 169// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to170// place the value into the least significant element of the most171// significant doubleword in the vector. This is not element zero for172// anything smaller than a doubleword on either endianness. This node has173// the same semantics as SCALAR_TO_VECTOR except that the value remains in174// the aforementioned location in the vector register.175def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",176 SDTypeProfile<1, 1, []>, []>;177 178def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>;179 180def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{181 return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&182 isOffsetMultipleOf(N, 16);183}]>;184 185//--------------------- VSX-specific instruction formats ---------------------//186// By default, all VSX instructions are to be selected over their Altivec187// counter parts and they do not have unmodeled sideeffects.188let AddedComplexity = 400, hasSideEffects = 0 in {189multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,190 string asmstr, InstrItinClass itin, Intrinsic Int,191 ValueType OutTy, ValueType InTy> {192 let BaseName = asmbase in {193 def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),194 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,195 [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>;196 let Defs = [CR6] in197 def _rec : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),198 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,199 [(set InTy:$XT,200 (InTy (PPCvcmp_rec InTy:$XA, InTy:$XB, xo)))]>,201 isRecordForm;202 }203}204 205// Instruction form with a single input register for instructions such as206// XXPERMDI. The reason for defining this is that specifying multiple chained207// operands (such as loads) to an instruction will perform both chained208// operations rather than coalescing them into a single register - even though209// the source memory location is the same. This simply forces the instruction210// to use the same register for both inputs.211// For example, an output DAG such as this:212// (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0))213// would result in two load instructions emitted and used as separate inputs214// to the XXPERMDI instruction.215class XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,216 InstrItinClass itin, list<dag> pattern>217 : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> {218 let XB = XA;219}220 221let Predicates = [HasVSX, HasP9Vector] in {222class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,223 list<dag> pattern>224 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vrrc:$RB),225 !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;226 227// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]228class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,229 list<dag> pattern>230 : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm;231 232// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),233// So we use different operand class for VRB234class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,235 RegisterOperand vbtype, list<dag> pattern>236 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vbtype:$RB),237 !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;238 239// [PO VRT XO VRB XO /]240class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,241 list<dag> pattern>242 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$RST), (ins vrrc:$RB),243 !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;244 245// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]246class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,247 list<dag> pattern>248 : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm;249 250// [PO T XO B XO BX /]251class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,252 list<dag> pattern>253 : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$RT), (ins vsfrc:$XB),254 !strconcat(opc, " $RT, $XB"), IIC_VecFP, pattern>;255 256// [PO T XO B XO BX TX]257class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,258 RegisterOperand vtype, list<dag> pattern>259 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),260 !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;261 262// [PO T A B XO AX BX TX], src and dest register use different operand class263class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,264 RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,265 InstrItinClass itin, list<dag> pattern>266 : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),267 !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;268 269// [PO VRT VRA VRB XO /]270class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,271 list<dag> pattern>272 : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RA, vrrc:$RB),273 !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>;274 275// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]276class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,277 list<dag> pattern>278 : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm;279 280// [PO VRT VRA VRB XO /]281class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,282 list<dag> pattern>283 : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RSTi, vrrc:$RA, vrrc:$RB),284 !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>,285 RegConstraint<"$RSTi = $RST">;286 287// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]288class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,289 list<dag> pattern>290 : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm;291 292class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,293 list<dag> pattern>294 : Z23Form_8<opcode, xo,295 (outs vrrc:$VRT), (ins u1imm:$R, vrrc:$VRB, u2imm:$idx),296 !strconcat(opc, " $R, $VRT, $VRB, $idx"), IIC_VecFP, pattern> {297 let RC = ex;298}299 300// [PO BF // VRA VRB XO /]301class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,302 list<dag> pattern>303 : XForm_17<opcode, xo, (outs crrc:$BF), (ins vrrc:$RA, vrrc:$RB),304 !strconcat(opc, " $BF, $RA, $RB"), IIC_FPCompare> {305 let Pattern = pattern;306}307 308// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different309// "out" and "in" dag310class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,311 RegisterOperand vtype, list<dag> pattern>312 : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins (memrr $RA, $RB):$addr),313 !strconcat(opc, " $XT, $addr"), IIC_LdStLFD, pattern>;314 315// [PO S RA RB XO SX]316class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,317 RegisterOperand vtype, list<dag> pattern>318 : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, (memrr $RA, $RB):$addr),319 !strconcat(opc, " $XT, $addr"), IIC_LdStSTFD, pattern>;320} // Predicates = HasP9Vector321} // AddedComplexity = 400, hasSideEffects = 0322 323multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> {324 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;325 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;326}327 328//-------------------------- Instruction definitions -------------------------//329// VSX instructions require the VSX feature, they are to be selected over330// equivalent Altivec patterns (as they address a larger register set) and331// they do not have unmodeled side effects.332let Predicates = [HasVSX], AddedComplexity = 400 in {333let hasSideEffects = 0 in {334 335 // Load indexed instructions336 let mayLoad = 1, mayStore = 0 in {337 let CodeSize = 3 in338 def LXSDX : XX1Form_memOp<31, 588,339 (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),340 "lxsdx $XT, $addr", IIC_LdStLFD,341 []>;342 343 // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later344 let CodeSize = 3 in345 def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),346 "#XFLOADf64",347 [(set f64:$XT, (load XForm:$addr))]>;348 349 let Predicates = [HasVSX, HasOnlySwappingMemOps] in350 def LXVD2X : XX1Form_memOp<31, 844,351 (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),352 "lxvd2x $XT, $addr", IIC_LdStLFD,353 []>;354 355 def LXVDSX : XX1Form_memOp<31, 332,356 (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),357 "lxvdsx $XT, $addr", IIC_LdStLFD, []>;358 359 let Predicates = [HasVSX, HasOnlySwappingMemOps] in360 def LXVW4X : XX1Form_memOp<31, 780,361 (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),362 "lxvw4x $XT, $addr", IIC_LdStLFD,363 []>;364 } // mayLoad365 366 // Store indexed instructions367 let mayStore = 1, mayLoad = 0 in {368 let CodeSize = 3 in369 def STXSDX : XX1Form_memOp<31, 716,370 (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),371 "stxsdx $XT, $addr", IIC_LdStSTFD,372 []>;373 374 // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later375 let CodeSize = 3 in376 def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),377 "#XFSTOREf64",378 [(store f64:$XT, XForm:$addr)]>;379 380 let Predicates = [HasVSX, HasOnlySwappingMemOps] in {381 // The behaviour of this instruction is endianness-specific so we provide no382 // pattern to match it without considering endianness.383 def STXVD2X : XX1Form_memOp<31, 972,384 (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr),385 "stxvd2x $XT, $addr", IIC_LdStSTFD,386 []>;387 388 def STXVW4X : XX1Form_memOp<31, 908,389 (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr),390 "stxvw4x $XT, $addr", IIC_LdStSTFD,391 []>;392 }393 } // mayStore394 395 let mayRaiseFPException = 1 in {396 let Uses = [RM] in {397 // Add/Mul Instructions398 let isCommutable = 1 in {399 def XSADDDP : XX3Form<60, 32,400 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),401 "xsadddp $XT, $XA, $XB", IIC_VecFP,402 [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>;403 def XSMULDP : XX3Form<60, 48,404 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),405 "xsmuldp $XT, $XA, $XB", IIC_VecFP,406 [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>;407 408 def XVADDDP : XX3Form<60, 96,409 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),410 "xvadddp $XT, $XA, $XB", IIC_VecFP,411 [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>;412 413 def XVADDSP : XX3Form<60, 64,414 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),415 "xvaddsp $XT, $XA, $XB", IIC_VecFP,416 [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>;417 418 def XVMULDP : XX3Form<60, 112,419 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),420 "xvmuldp $XT, $XA, $XB", IIC_VecFP,421 [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>;422 423 def XVMULSP : XX3Form<60, 80,424 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),425 "xvmulsp $XT, $XA, $XB", IIC_VecFP,426 [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>;427 }428 429 // Subtract Instructions430 def XSSUBDP : XX3Form<60, 40,431 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),432 "xssubdp $XT, $XA, $XB", IIC_VecFP,433 [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>;434 435 def XVSUBDP : XX3Form<60, 104,436 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),437 "xvsubdp $XT, $XA, $XB", IIC_VecFP,438 [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>;439 def XVSUBSP : XX3Form<60, 72,440 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),441 "xvsubsp $XT, $XA, $XB", IIC_VecFP,442 [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>;443 444 // FMA Instructions445 let BaseName = "XSMADDADP" in {446 let isCommutable = 1 in447 def XSMADDADP : XX3Form<60, 33,448 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),449 "xsmaddadp $XT, $XA, $XB", IIC_VecFP,450 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,451 RegConstraint<"$XTi = $XT">,452 AltVSXFMARel;453 let IsVSXFMAAlt = 1 in454 def XSMADDMDP : XX3Form<60, 41,455 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),456 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,457 RegConstraint<"$XTi = $XT">,458 AltVSXFMARel;459 }460 461 let BaseName = "XSMSUBADP" in {462 let isCommutable = 1 in463 def XSMSUBADP : XX3Form<60, 49,464 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),465 "xsmsubadp $XT, $XA, $XB", IIC_VecFP,466 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,467 RegConstraint<"$XTi = $XT">,468 AltVSXFMARel;469 let IsVSXFMAAlt = 1 in470 def XSMSUBMDP : XX3Form<60, 57,471 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),472 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,473 RegConstraint<"$XTi = $XT">,474 AltVSXFMARel;475 }476 477 let BaseName = "XSNMADDADP" in {478 let isCommutable = 1 in479 def XSNMADDADP : XX3Form<60, 161,480 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),481 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,482 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,483 RegConstraint<"$XTi = $XT">,484 AltVSXFMARel;485 let IsVSXFMAAlt = 1 in486 def XSNMADDMDP : XX3Form<60, 169,487 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),488 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,489 RegConstraint<"$XTi = $XT">,490 AltVSXFMARel;491 }492 493 let BaseName = "XSNMSUBADP" in {494 let isCommutable = 1 in495 def XSNMSUBADP : XX3Form<60, 177,496 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),497 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,498 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,499 RegConstraint<"$XTi = $XT">,500 AltVSXFMARel;501 let IsVSXFMAAlt = 1 in502 def XSNMSUBMDP : XX3Form<60, 185,503 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),504 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,505 RegConstraint<"$XTi = $XT">,506 AltVSXFMARel;507 }508 509 let BaseName = "XVMADDADP" in {510 let isCommutable = 1 in511 def XVMADDADP : XX3Form<60, 97,512 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),513 "xvmaddadp $XT, $XA, $XB", IIC_VecFP,514 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,515 RegConstraint<"$XTi = $XT">,516 AltVSXFMARel;517 let IsVSXFMAAlt = 1 in518 def XVMADDMDP : XX3Form<60, 105,519 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),520 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,521 RegConstraint<"$XTi = $XT">,522 AltVSXFMARel;523 }524 525 let BaseName = "XVMADDASP" in {526 let isCommutable = 1 in527 def XVMADDASP : XX3Form<60, 65,528 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),529 "xvmaddasp $XT, $XA, $XB", IIC_VecFP,530 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,531 RegConstraint<"$XTi = $XT">,532 AltVSXFMARel;533 let IsVSXFMAAlt = 1 in534 def XVMADDMSP : XX3Form<60, 73,535 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),536 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,537 RegConstraint<"$XTi = $XT">,538 AltVSXFMARel;539 }540 541 let BaseName = "XVMSUBADP" in {542 let isCommutable = 1 in543 def XVMSUBADP : XX3Form<60, 113,544 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),545 "xvmsubadp $XT, $XA, $XB", IIC_VecFP,546 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,547 RegConstraint<"$XTi = $XT">,548 AltVSXFMARel;549 let IsVSXFMAAlt = 1 in550 def XVMSUBMDP : XX3Form<60, 121,551 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),552 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,553 RegConstraint<"$XTi = $XT">,554 AltVSXFMARel;555 }556 557 let BaseName = "XVMSUBASP" in {558 let isCommutable = 1 in559 def XVMSUBASP : XX3Form<60, 81,560 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),561 "xvmsubasp $XT, $XA, $XB", IIC_VecFP,562 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,563 RegConstraint<"$XTi = $XT">,564 AltVSXFMARel;565 let IsVSXFMAAlt = 1 in566 def XVMSUBMSP : XX3Form<60, 89,567 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),568 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,569 RegConstraint<"$XTi = $XT">,570 AltVSXFMARel;571 }572 573 let BaseName = "XVNMADDADP" in {574 let isCommutable = 1 in575 def XVNMADDADP : XX3Form<60, 225,576 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),577 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,578 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,579 RegConstraint<"$XTi = $XT">,580 AltVSXFMARel;581 let IsVSXFMAAlt = 1 in582 def XVNMADDMDP : XX3Form<60, 233,583 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),584 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,585 RegConstraint<"$XTi = $XT">,586 AltVSXFMARel;587 }588 589 let BaseName = "XVNMADDASP" in {590 let isCommutable = 1 in591 def XVNMADDASP : XX3Form<60, 193,592 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),593 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,594 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,595 RegConstraint<"$XTi = $XT">,596 AltVSXFMARel;597 let IsVSXFMAAlt = 1 in598 def XVNMADDMSP : XX3Form<60, 201,599 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),600 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,601 RegConstraint<"$XTi = $XT">,602 AltVSXFMARel;603 }604 605 let BaseName = "XVNMSUBADP" in {606 let isCommutable = 1 in607 def XVNMSUBADP : XX3Form<60, 241,608 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),609 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,610 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,611 RegConstraint<"$XTi = $XT">,612 AltVSXFMARel;613 let IsVSXFMAAlt = 1 in614 def XVNMSUBMDP : XX3Form<60, 249,615 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),616 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,617 RegConstraint<"$XTi = $XT">,618 AltVSXFMARel;619 }620 621 let BaseName = "XVNMSUBASP" in {622 let isCommutable = 1 in623 def XVNMSUBASP : XX3Form<60, 209,624 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),625 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,626 [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,627 RegConstraint<"$XTi = $XT">,628 AltVSXFMARel;629 let IsVSXFMAAlt = 1 in630 def XVNMSUBMSP : XX3Form<60, 217,631 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),632 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,633 RegConstraint<"$XTi = $XT">,634 AltVSXFMARel;635 }636 637 // Division Instructions638 def XSDIVDP : XX3Form<60, 56,639 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),640 "xsdivdp $XT, $XA, $XB", IIC_FPDivD,641 [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>;642 def XSSQRTDP : XX2Form<60, 75,643 (outs vsfrc:$XT), (ins vsfrc:$XB),644 "xssqrtdp $XT, $XB", IIC_FPSqrtD,645 [(set f64:$XT, (any_fsqrt f64:$XB))]>;646 647 def XSREDP : XX2Form<60, 90,648 (outs vsfrc:$XT), (ins vsfrc:$XB),649 "xsredp $XT, $XB", IIC_VecFP,650 [(set f64:$XT, (PPCfre f64:$XB))]>;651 def XSRSQRTEDP : XX2Form<60, 74,652 (outs vsfrc:$XT), (ins vsfrc:$XB),653 "xsrsqrtedp $XT, $XB", IIC_VecFP,654 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;655 656 let mayRaiseFPException = 0 in {657 def XSTDIVDP : XX3Form_1<60, 61,658 (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),659 "xstdivdp $CR, $XA, $XB", IIC_FPCompare, []>;660 def XSTSQRTDP : XX2Form_1<60, 106,661 (outs crrc:$CR), (ins vsfrc:$XB),662 "xstsqrtdp $CR, $XB", IIC_FPCompare,663 [(set i32:$CR, (PPCftsqrt f64:$XB))]>;664 def XVTDIVDP : XX3Form_1<60, 125,665 (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB),666 "xvtdivdp $CR, $XA, $XB", IIC_FPCompare, []>;667 def XVTDIVSP : XX3Form_1<60, 93,668 (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB),669 "xvtdivsp $CR, $XA, $XB", IIC_FPCompare, []>;670 671 def XVTSQRTDP : XX2Form_1<60, 234,672 (outs crrc:$CR), (ins vsrc:$XB),673 "xvtsqrtdp $CR, $XB", IIC_FPCompare,674 [(set i32:$CR, (PPCftsqrt v2f64:$XB))]>;675 def XVTSQRTSP : XX2Form_1<60, 170,676 (outs crrc:$CR), (ins vsrc:$XB),677 "xvtsqrtsp $CR, $XB", IIC_FPCompare,678 [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>;679 }680 681 def XVDIVDP : XX3Form<60, 120,682 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),683 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,684 [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>;685 def XVDIVSP : XX3Form<60, 88,686 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),687 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,688 [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>;689 690 def XVSQRTDP : XX2Form<60, 203,691 (outs vsrc:$XT), (ins vsrc:$XB),692 "xvsqrtdp $XT, $XB", IIC_FPSqrtD,693 [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>;694 def XVSQRTSP : XX2Form<60, 139,695 (outs vsrc:$XT), (ins vsrc:$XB),696 "xvsqrtsp $XT, $XB", IIC_FPSqrtS,697 [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>;698 699 def XVREDP : XX2Form<60, 218,700 (outs vsrc:$XT), (ins vsrc:$XB),701 "xvredp $XT, $XB", IIC_VecFP,702 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;703 def XVRESP : XX2Form<60, 154,704 (outs vsrc:$XT), (ins vsrc:$XB),705 "xvresp $XT, $XB", IIC_VecFP,706 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;707 708 def XVRSQRTEDP : XX2Form<60, 202,709 (outs vsrc:$XT), (ins vsrc:$XB),710 "xvrsqrtedp $XT, $XB", IIC_VecFP,711 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;712 def XVRSQRTESP : XX2Form<60, 138,713 (outs vsrc:$XT), (ins vsrc:$XB),714 "xvrsqrtesp $XT, $XB", IIC_VecFP,715 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;716 717 // Compare Instructions718 def XSCMPODP : XX3Form_1<60, 43,719 (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),720 "xscmpodp $CR, $XA, $XB", IIC_FPCompare, []>;721 def XSCMPUDP : XX3Form_1<60, 35,722 (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),723 "xscmpudp $CR, $XA, $XB", IIC_FPCompare, []>;724 725 defm XVCMPEQDP : XX3Form_Rcr<60, 99,726 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,727 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;728 defm XVCMPEQSP : XX3Form_Rcr<60, 67,729 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,730 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;731 defm XVCMPGEDP : XX3Form_Rcr<60, 115,732 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare,733 int_ppc_vsx_xvcmpgedp, v2i64, v2f64>;734 defm XVCMPGESP : XX3Form_Rcr<60, 83,735 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare,736 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;737 defm XVCMPGTDP : XX3Form_Rcr<60, 107,738 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare,739 int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>;740 defm XVCMPGTSP : XX3Form_Rcr<60, 75,741 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare,742 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;743 744 // Move Instructions745 let mayRaiseFPException = 0 in {746 def XSABSDP : XX2Form<60, 345,747 (outs vsfrc:$XT), (ins vsfrc:$XB),748 "xsabsdp $XT, $XB", IIC_VecFP,749 [(set f64:$XT, (fabs f64:$XB))]>;750 def XSNABSDP : XX2Form<60, 361,751 (outs vsfrc:$XT), (ins vsfrc:$XB),752 "xsnabsdp $XT, $XB", IIC_VecFP,753 [(set f64:$XT, (fneg (fabs f64:$XB)))]>;754 let isCodeGenOnly = 1 in755 def XSNABSDPs : XX2Form<60, 361,756 (outs vssrc:$XT), (ins vssrc:$XB),757 "xsnabsdp $XT, $XB", IIC_VecFP,758 [(set f32:$XT, (fneg (fabs f32:$XB)))]>;759 def XSNEGDP : XX2Form<60, 377,760 (outs vsfrc:$XT), (ins vsfrc:$XB),761 "xsnegdp $XT, $XB", IIC_VecFP,762 [(set f64:$XT, (fneg f64:$XB))]>;763 def XSCPSGNDP : XX3Form<60, 176,764 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),765 "xscpsgndp $XT, $XA, $XB", IIC_VecFP,766 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;767 768 def XVABSDP : XX2Form<60, 473,769 (outs vsrc:$XT), (ins vsrc:$XB),770 "xvabsdp $XT, $XB", IIC_VecFP,771 [(set v2f64:$XT, (fabs v2f64:$XB))]>;772 773 def XVABSSP : XX2Form<60, 409,774 (outs vsrc:$XT), (ins vsrc:$XB),775 "xvabssp $XT, $XB", IIC_VecFP,776 [(set v4f32:$XT, (fabs v4f32:$XB))]>;777 778 def XVCPSGNDP : XX3Form<60, 240,779 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),780 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,781 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;782 def XVCPSGNSP : XX3Form<60, 208,783 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),784 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,785 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;786 787 def XVNABSDP : XX2Form<60, 489,788 (outs vsrc:$XT), (ins vsrc:$XB),789 "xvnabsdp $XT, $XB", IIC_VecFP,790 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;791 def XVNABSSP : XX2Form<60, 425,792 (outs vsrc:$XT), (ins vsrc:$XB),793 "xvnabssp $XT, $XB", IIC_VecFP,794 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;795 796 def XVNEGDP : XX2Form<60, 505,797 (outs vsrc:$XT), (ins vsrc:$XB),798 "xvnegdp $XT, $XB", IIC_VecFP,799 [(set v2f64:$XT, (fneg v2f64:$XB))]>;800 def XVNEGSP : XX2Form<60, 441,801 (outs vsrc:$XT), (ins vsrc:$XB),802 "xvnegsp $XT, $XB", IIC_VecFP,803 [(set v4f32:$XT, (fneg v4f32:$XB))]>;804 }805 806 // Conversion Instructions807 def XSCVDPSP : XX2Form<60, 265,808 (outs vsfrc:$XT), (ins vsfrc:$XB),809 "xscvdpsp $XT, $XB", IIC_VecFP, []>;810 def XSCVDPSXDS : XX2Form<60, 344,811 (outs vsfrc:$XT), (ins vsfrc:$XB),812 "xscvdpsxds $XT, $XB", IIC_VecFP,813 [(set f64:$XT, (PPCany_fctidz f64:$XB))]>;814 let isCodeGenOnly = 1 in815 def XSCVDPSXDSs : XX2Form<60, 344,816 (outs vssrc:$XT), (ins vssrc:$XB),817 "xscvdpsxds $XT, $XB", IIC_VecFP,818 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>;819 def XSCVDPSXWS : XX2Form<60, 88,820 (outs vsfrc:$XT), (ins vsfrc:$XB),821 "xscvdpsxws $XT, $XB", IIC_VecFP,822 [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>;823 let isCodeGenOnly = 1 in824 def XSCVDPSXWSs : XX2Form<60, 88,825 (outs vssrc:$XT), (ins vssrc:$XB),826 "xscvdpsxws $XT, $XB", IIC_VecFP,827 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;828 def XSCVDPUXDS : XX2Form<60, 328,829 (outs vsfrc:$XT), (ins vsfrc:$XB),830 "xscvdpuxds $XT, $XB", IIC_VecFP,831 [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>;832 let isCodeGenOnly = 1 in833 def XSCVDPUXDSs : XX2Form<60, 328,834 (outs vssrc:$XT), (ins vssrc:$XB),835 "xscvdpuxds $XT, $XB", IIC_VecFP,836 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;837 def XSCVDPUXWS : XX2Form<60, 72,838 (outs vsfrc:$XT), (ins vsfrc:$XB),839 "xscvdpuxws $XT, $XB", IIC_VecFP,840 [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>;841 let isCodeGenOnly = 1 in842 def XSCVDPUXWSs : XX2Form<60, 72,843 (outs vssrc:$XT), (ins vssrc:$XB),844 "xscvdpuxws $XT, $XB", IIC_VecFP,845 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;846 def XSCVSPDP : XX2Form<60, 329,847 (outs vsfrc:$XT), (ins vsfrc:$XB),848 "xscvspdp $XT, $XB", IIC_VecFP, []>;849 def XSCVSXDDP : XX2Form<60, 376,850 (outs vsfrc:$XT), (ins vsfrc:$XB),851 "xscvsxddp $XT, $XB", IIC_VecFP,852 [(set f64:$XT, (PPCany_fcfid f64:$XB))]>;853 def XSCVUXDDP : XX2Form<60, 360,854 (outs vsfrc:$XT), (ins vsfrc:$XB),855 "xscvuxddp $XT, $XB", IIC_VecFP,856 [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>;857 858 def XVCVDPSP : XX2Form<60, 393,859 (outs vsrc:$XT), (ins vsrc:$XB),860 "xvcvdpsp $XT, $XB", IIC_VecFP,861 [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;862 def XVCVDPSXDS : XX2Form<60, 472,863 (outs vsrc:$XT), (ins vsrc:$XB),864 "xvcvdpsxds $XT, $XB", IIC_VecFP,865 [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>;866 def XVCVDPSXWS : XX2Form<60, 216,867 (outs vsrc:$XT), (ins vsrc:$XB),868 "xvcvdpsxws $XT, $XB", IIC_VecFP,869 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;870 def XVCVDPUXDS : XX2Form<60, 456,871 (outs vsrc:$XT), (ins vsrc:$XB),872 "xvcvdpuxds $XT, $XB", IIC_VecFP,873 [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>;874 def XVCVDPUXWS : XX2Form<60, 200,875 (outs vsrc:$XT), (ins vsrc:$XB),876 "xvcvdpuxws $XT, $XB", IIC_VecFP,877 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;878 879 def XVCVSPDP : XX2Form<60, 457,880 (outs vsrc:$XT), (ins vsrc:$XB),881 "xvcvspdp $XT, $XB", IIC_VecFP,882 [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;883 def XVCVSPSXDS : XX2Form<60, 408,884 (outs vsrc:$XT), (ins vsrc:$XB),885 "xvcvspsxds $XT, $XB", IIC_VecFP,886 [(set v2i64:$XT, (int_ppc_vsx_xvcvspsxds v4f32:$XB))]>;887 def XVCVSPSXWS : XX2Form<60, 152,888 (outs vsrc:$XT), (ins vsrc:$XB),889 "xvcvspsxws $XT, $XB", IIC_VecFP,890 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;891 def XVCVSPUXDS : XX2Form<60, 392,892 (outs vsrc:$XT), (ins vsrc:$XB),893 "xvcvspuxds $XT, $XB", IIC_VecFP,894 [(set v2i64:$XT, (int_ppc_vsx_xvcvspuxds v4f32:$XB))]>;895 def XVCVSPUXWS : XX2Form<60, 136,896 (outs vsrc:$XT), (ins vsrc:$XB),897 "xvcvspuxws $XT, $XB", IIC_VecFP,898 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;899 def XVCVSXDDP : XX2Form<60, 504,900 (outs vsrc:$XT), (ins vsrc:$XB),901 "xvcvsxddp $XT, $XB", IIC_VecFP,902 [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>;903 def XVCVSXDSP : XX2Form<60, 440,904 (outs vsrc:$XT), (ins vsrc:$XB),905 "xvcvsxdsp $XT, $XB", IIC_VecFP,906 [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;907 def XVCVSXWSP : XX2Form<60, 184,908 (outs vsrc:$XT), (ins vsrc:$XB),909 "xvcvsxwsp $XT, $XB", IIC_VecFP,910 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;911 def XVCVUXDDP : XX2Form<60, 488,912 (outs vsrc:$XT), (ins vsrc:$XB),913 "xvcvuxddp $XT, $XB", IIC_VecFP,914 [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>;915 def XVCVUXDSP : XX2Form<60, 424,916 (outs vsrc:$XT), (ins vsrc:$XB),917 "xvcvuxdsp $XT, $XB", IIC_VecFP,918 [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;919 def XVCVUXWSP : XX2Form<60, 168,920 (outs vsrc:$XT), (ins vsrc:$XB),921 "xvcvuxwsp $XT, $XB", IIC_VecFP,922 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;923 924 let mayRaiseFPException = 0 in {925 def XVCVSXWDP : XX2Form<60, 248,926 (outs vsrc:$XT), (ins vsrc:$XB),927 "xvcvsxwdp $XT, $XB", IIC_VecFP,928 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;929 def XVCVUXWDP : XX2Form<60, 232,930 (outs vsrc:$XT), (ins vsrc:$XB),931 "xvcvuxwdp $XT, $XB", IIC_VecFP,932 [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;933 }934 935 // Rounding Instructions respecting current rounding mode936 def XSRDPIC : XX2Form<60, 107,937 (outs vsfrc:$XT), (ins vsfrc:$XB),938 "xsrdpic $XT, $XB", IIC_VecFP, []>;939 def XVRDPIC : XX2Form<60, 235,940 (outs vsrc:$XT), (ins vsrc:$XB),941 "xvrdpic $XT, $XB", IIC_VecFP, []>;942 def XVRSPIC : XX2Form<60, 171,943 (outs vsrc:$XT), (ins vsrc:$XB),944 "xvrspic $XT, $XB", IIC_VecFP, []>;945 // Max/Min Instructions946 let isCommutable = 1 in {947 def XSMAXDP : XX3Form<60, 160,948 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),949 "xsmaxdp $XT, $XA, $XB", IIC_VecFP,950 [(set vsfrc:$XT,951 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;952 def XSMINDP : XX3Form<60, 168,953 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),954 "xsmindp $XT, $XA, $XB", IIC_VecFP,955 [(set vsfrc:$XT,956 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;957 958 def XVMAXDP : XX3Form<60, 224,959 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),960 "xvmaxdp $XT, $XA, $XB", IIC_VecFP,961 [(set vsrc:$XT,962 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;963 def XVMINDP : XX3Form<60, 232,964 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),965 "xvmindp $XT, $XA, $XB", IIC_VecFP,966 [(set vsrc:$XT,967 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;968 969 def XVMAXSP : XX3Form<60, 192,970 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),971 "xvmaxsp $XT, $XA, $XB", IIC_VecFP,972 [(set vsrc:$XT,973 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;974 def XVMINSP : XX3Form<60, 200,975 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),976 "xvminsp $XT, $XA, $XB", IIC_VecFP,977 [(set vsrc:$XT,978 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;979 } // isCommutable980 } // Uses = [RM]981 982 // Rounding Instructions with static direction.983 def XSRDPI : XX2Form<60, 73,984 (outs vsfrc:$XT), (ins vsfrc:$XB),985 "xsrdpi $XT, $XB", IIC_VecFP,986 [(set f64:$XT, (any_fround f64:$XB))]>;987 def XSRDPIM : XX2Form<60, 121,988 (outs vsfrc:$XT), (ins vsfrc:$XB),989 "xsrdpim $XT, $XB", IIC_VecFP,990 [(set f64:$XT, (any_ffloor f64:$XB))]>;991 def XSRDPIP : XX2Form<60, 105,992 (outs vsfrc:$XT), (ins vsfrc:$XB),993 "xsrdpip $XT, $XB", IIC_VecFP,994 [(set f64:$XT, (any_fceil f64:$XB))]>;995 def XSRDPIZ : XX2Form<60, 89,996 (outs vsfrc:$XT), (ins vsfrc:$XB),997 "xsrdpiz $XT, $XB", IIC_VecFP,998 [(set f64:$XT, (any_ftrunc f64:$XB))]>;999 1000 def XVRDPI : XX2Form<60, 201,1001 (outs vsrc:$XT), (ins vsrc:$XB),1002 "xvrdpi $XT, $XB", IIC_VecFP,1003 [(set v2f64:$XT, (any_fround v2f64:$XB))]>;1004 def XVRDPIM : XX2Form<60, 249,1005 (outs vsrc:$XT), (ins vsrc:$XB),1006 "xvrdpim $XT, $XB", IIC_VecFP,1007 [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>;1008 def XVRDPIP : XX2Form<60, 233,1009 (outs vsrc:$XT), (ins vsrc:$XB),1010 "xvrdpip $XT, $XB", IIC_VecFP,1011 [(set v2f64:$XT, (any_fceil v2f64:$XB))]>;1012 def XVRDPIZ : XX2Form<60, 217,1013 (outs vsrc:$XT), (ins vsrc:$XB),1014 "xvrdpiz $XT, $XB", IIC_VecFP,1015 [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>;1016 1017 def XVRSPI : XX2Form<60, 137,1018 (outs vsrc:$XT), (ins vsrc:$XB),1019 "xvrspi $XT, $XB", IIC_VecFP,1020 [(set v4f32:$XT, (any_fround v4f32:$XB))]>;1021 def XVRSPIM : XX2Form<60, 185,1022 (outs vsrc:$XT), (ins vsrc:$XB),1023 "xvrspim $XT, $XB", IIC_VecFP,1024 [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>;1025 def XVRSPIP : XX2Form<60, 169,1026 (outs vsrc:$XT), (ins vsrc:$XB),1027 "xvrspip $XT, $XB", IIC_VecFP,1028 [(set v4f32:$XT, (any_fceil v4f32:$XB))]>;1029 def XVRSPIZ : XX2Form<60, 153,1030 (outs vsrc:$XT), (ins vsrc:$XB),1031 "xvrspiz $XT, $XB", IIC_VecFP,1032 [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>;1033 } // mayRaiseFPException1034 1035 // Logical Instructions1036 let isCommutable = 1 in1037 def XXLAND : XX3Form<60, 130,1038 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1039 "xxland $XT, $XA, $XB", IIC_VecGeneral,1040 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;1041 def XXLANDC : XX3Form<60, 138,1042 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1043 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,1044 [(set v4i32:$XT, (and v4i32:$XA,1045 (vnot v4i32:$XB)))]>;1046 let isCommutable = 1 in {1047 def XXLNOR : XX3Form<60, 162,1048 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1049 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,1050 [(set v4i32:$XT, (vnot (or v4i32:$XA,1051 v4i32:$XB)))]>;1052 def XXLOR : XX3Form<60, 146,1053 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1054 "xxlor $XT, $XA, $XB", IIC_VecGeneral,1055 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;1056 let isCodeGenOnly = 1 in1057 def XXLORf: XX3Form<60, 146,1058 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),1059 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;1060 def XXLXOR : XX3Form<60, 154,1061 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1062 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,1063 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;1064 } // isCommutable1065 1066 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,1067 isReMaterializable = 1 in {1068 def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins),1069 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,1070 [(set v4i32:$XT, (v4i32 immAllZerosV))]>;1071 def XXLXORdpz : XX3Form_SameOp<60, 154,1072 (outs vsfrc:$XT), (ins),1073 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,1074 [(set f64:$XT, (fpimm0))]>;1075 def XXLXORspz : XX3Form_SameOp<60, 154,1076 (outs vssrc:$XT), (ins),1077 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,1078 [(set f32:$XT, (fpimm0))]>;1079 }1080 1081 // Permutation Instructions1082 def XXMRGHW : XX3Form<60, 18,1083 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1084 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;1085 def XXMRGLW : XX3Form<60, 50,1086 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1087 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;1088 1089 def XXPERMDI : XX3Form_2<60, 10,1090 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D),1091 "xxpermdi $XT, $XA, $XB, $D", IIC_VecPerm,1092 [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,1093 imm32SExt16:$D))]>;1094 let isCodeGenOnly = 1 in1095 // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which1096 // is not the same with the input register class(`vsrc`) of XXPERMDI instruction.1097 // We did this on purpose because:1098 // 1: The input is primarily for loads that load a partial vector(LFIWZX,1099 // etc.), no need for SUBREG_TO_REG.1100 // 2: With `vsfrc` register class, in the final assembly, float registers1101 // like `f0` are used instead of vector scalar register like `vs0`. This1102 // helps readability.1103 def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D),1104 "xxpermdi $XT, $XA, $XA, $D", IIC_VecPerm, []>;1105 def XXSEL : XX4Form<60, 3,1106 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),1107 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;1108 1109 def XXSLDWI : XX3Form_2<60, 2,1110 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D),1111 "xxsldwi $XT, $XA, $XB, $D", IIC_VecPerm,1112 [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,1113 imm32SExt16:$D))]>;1114 1115 let isCodeGenOnly = 1 in1116 def XXSLDWIs : XX3Form_2s<60, 2,1117 (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D),1118 "xxsldwi $XT, $XA, $XA, $D", IIC_VecPerm, []>;1119 1120 def XXSPLTW : XX2Form_2<60, 164,1121 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$D),1122 "xxspltw $XT, $XB, $D", IIC_VecPerm,1123 [(set v4i32:$XT,1124 (PPCxxsplt v4i32:$XB, imm32SExt16:$D))]>;1125 let isCodeGenOnly = 1 in1126 def XXSPLTWs : XX2Form_2<60, 164,1127 (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$D),1128 "xxspltw $XT, $XB, $D", IIC_VecPerm, []>;1129 1130// The following VSX instructions were introduced in Power ISA 2.071131let Predicates = [HasVSX, HasP8Vector] in {1132 let isCommutable = 1 in {1133 def XXLEQV : XX3Form<60, 186,1134 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1135 "xxleqv $XT, $XA, $XB", IIC_VecGeneral,1136 [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>;1137 def XXLNAND : XX3Form<60, 178,1138 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1139 "xxlnand $XT, $XA, $XB", IIC_VecGeneral,1140 [(set v4i32:$XT, (vnot (and v4i32:$XA, v4i32:$XB)))]>;1141 } // isCommutable1142 1143 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,1144 isReMaterializable = 1 in {1145 def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),1146 "xxleqv $XT, $XT, $XT", IIC_VecGeneral,1147 [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;1148 }1149 1150 def XXLORC : XX3Form<60, 170,1151 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),1152 "xxlorc $XT, $XA, $XB", IIC_VecGeneral,1153 [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>;1154 1155 // VSX scalar loads introduced in ISA 2.071156 let mayLoad = 1, mayStore = 0 in {1157 let CodeSize = 3 in1158 def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins (memrr $RA, $RB):$addr),1159 "lxsspx $XT, $addr", IIC_LdStLFD, []>;1160 def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),1161 "lxsiwax $XT, $addr", IIC_LdStLFD, []>;1162 def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),1163 "lxsiwzx $XT, $addr", IIC_LdStLFD, []>;1164 1165 // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later1166 let CodeSize = 3 in1167 def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),1168 "#XFLOADf32",1169 [(set f32:$XT, (load XForm:$src))]>;1170 // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later1171 def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),1172 "#LIWAX",1173 [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>;1174 // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later1175 def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),1176 "#LIWZX",1177 [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>;1178 } // mayLoad1179 1180 // VSX scalar stores introduced in ISA 2.071181 let mayStore = 1, mayLoad = 0 in {1182 let CodeSize = 3 in1183 def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, (memrr $RA, $RB):$addr),1184 "stxsspx $XT, $addr", IIC_LdStSTFD, []>;1185 def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),1186 "stxsiwx $XT, $addr", IIC_LdStSTFD, []>;1187 1188 // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later1189 let CodeSize = 3 in1190 def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),1191 "#XFSTOREf32",1192 [(store f32:$XT, XForm:$dst)]>;1193 // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later1194 def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),1195 "#STIWX",1196 [(PPCstfiwx f64:$XT, ForceXForm:$dst)]>;1197 } // mayStore1198 1199 // VSX Elementary Scalar FP arithmetic (SP)1200 let mayRaiseFPException = 1 in {1201 let isCommutable = 1 in {1202 def XSADDSP : XX3Form<60, 0,1203 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),1204 "xsaddsp $XT, $XA, $XB", IIC_VecFP,1205 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>;1206 def XSMULSP : XX3Form<60, 16,1207 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),1208 "xsmulsp $XT, $XA, $XB", IIC_VecFP,1209 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>;1210 } // isCommutable1211 1212 def XSSUBSP : XX3Form<60, 8,1213 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),1214 "xssubsp $XT, $XA, $XB", IIC_VecFP,1215 [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>;1216 def XSDIVSP : XX3Form<60, 24,1217 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),1218 "xsdivsp $XT, $XA, $XB", IIC_FPDivS,1219 [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>;1220 1221 def XSRESP : XX2Form<60, 26,1222 (outs vssrc:$XT), (ins vssrc:$XB),1223 "xsresp $XT, $XB", IIC_VecFP,1224 [(set f32:$XT, (PPCfre f32:$XB))]>;1225 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1226 let hasSideEffects = 1 in1227 def XSRSP : XX2Form<60, 281,1228 (outs vssrc:$XT), (ins vsfrc:$XB),1229 "xsrsp $XT, $XB", IIC_VecFP,1230 [(set f32:$XT, (any_fpround f64:$XB))]>;1231 def XSSQRTSP : XX2Form<60, 11,1232 (outs vssrc:$XT), (ins vssrc:$XB),1233 "xssqrtsp $XT, $XB", IIC_FPSqrtS,1234 [(set f32:$XT, (any_fsqrt f32:$XB))]>;1235 def XSRSQRTESP : XX2Form<60, 10,1236 (outs vssrc:$XT), (ins vssrc:$XB),1237 "xsrsqrtesp $XT, $XB", IIC_VecFP,1238 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;1239 1240 // FMA Instructions1241 let BaseName = "XSMADDASP" in {1242 let isCommutable = 1 in1243 def XSMADDASP : XX3Form<60, 1,1244 (outs vssrc:$XT),1245 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1246 "xsmaddasp $XT, $XA, $XB", IIC_VecFP,1247 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,1248 RegConstraint<"$XTi = $XT">,1249 AltVSXFMARel;1250 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1251 let IsVSXFMAAlt = 1, hasSideEffects = 1 in1252 def XSMADDMSP : XX3Form<60, 9,1253 (outs vssrc:$XT),1254 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1255 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,1256 RegConstraint<"$XTi = $XT">,1257 AltVSXFMARel;1258 }1259 1260 let BaseName = "XSMSUBASP" in {1261 let isCommutable = 1 in1262 def XSMSUBASP : XX3Form<60, 17,1263 (outs vssrc:$XT),1264 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1265 "xsmsubasp $XT, $XA, $XB", IIC_VecFP,1266 [(set f32:$XT, (any_fma f32:$XA, f32:$XB,1267 (fneg f32:$XTi)))]>,1268 RegConstraint<"$XTi = $XT">,1269 AltVSXFMARel;1270 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1271 let IsVSXFMAAlt = 1, hasSideEffects = 1 in1272 def XSMSUBMSP : XX3Form<60, 25,1273 (outs vssrc:$XT),1274 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1275 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,1276 RegConstraint<"$XTi = $XT">,1277 AltVSXFMARel;1278 }1279 1280 let BaseName = "XSNMADDASP" in {1281 let isCommutable = 1 in1282 def XSNMADDASP : XX3Form<60, 129,1283 (outs vssrc:$XT),1284 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1285 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,1286 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,1287 f32:$XTi)))]>,1288 RegConstraint<"$XTi = $XT">,1289 AltVSXFMARel;1290 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1291 let IsVSXFMAAlt = 1, hasSideEffects = 1 in1292 def XSNMADDMSP : XX3Form<60, 137,1293 (outs vssrc:$XT),1294 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1295 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,1296 RegConstraint<"$XTi = $XT">,1297 AltVSXFMARel;1298 }1299 1300 let BaseName = "XSNMSUBASP" in {1301 let isCommutable = 1 in1302 def XSNMSUBASP : XX3Form<60, 145,1303 (outs vssrc:$XT),1304 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1305 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,1306 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,1307 (fneg f32:$XTi))))]>,1308 RegConstraint<"$XTi = $XT">,1309 AltVSXFMARel;1310 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1311 let IsVSXFMAAlt = 1, hasSideEffects = 1 in1312 def XSNMSUBMSP : XX3Form<60, 153,1313 (outs vssrc:$XT),1314 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),1315 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,1316 RegConstraint<"$XTi = $XT">,1317 AltVSXFMARel;1318 }1319 1320 // Single Precision Conversions (FP <-> INT)1321 def XSCVSXDSP : XX2Form<60, 312,1322 (outs vssrc:$XT), (ins vsfrc:$XB),1323 "xscvsxdsp $XT, $XB", IIC_VecFP,1324 [(set f32:$XT, (PPCany_fcfids f64:$XB))]>;1325 def XSCVUXDSP : XX2Form<60, 296,1326 (outs vssrc:$XT), (ins vsfrc:$XB),1327 "xscvuxdsp $XT, $XB", IIC_VecFP,1328 [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>;1329 } // mayRaiseFPException1330 1331 // Conversions between vector and scalar single precision1332 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),1333 "xscvdpspn $XT, $XB", IIC_VecFP, []>;1334 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),1335 "xscvspdpn $XT, $XB", IIC_VecFP, []>;1336 1337 let Predicates = [HasVSX, HasDirectMove] in {1338 // VSX direct move instructions1339 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT),1340 "mfvsrd $RA, $XT", IIC_VecGeneral,1341 [(set i64:$RA, (PPCmfvsr f64:$XT))]>,1342 Requires<[IsPPC64]>;1343 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1344 let isCodeGenOnly = 1, hasSideEffects = 1 in1345 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT),1346 "mfvsrd $RA, $XT", IIC_VecGeneral,1347 []>,1348 Requires<[IsPPC64]>;1349 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT),1350 "mfvsrwz $RA, $XT", IIC_VecGeneral,1351 [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64;1352 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1353 let isCodeGenOnly = 1, hasSideEffects = 1 in1354 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsrc:$XT),1355 "mfvsrwz $RA, $XT", IIC_VecGeneral,1356 []>;1357 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA),1358 "mtvsrd $XT, $RA", IIC_VecGeneral,1359 [(set f64:$XT, (PPCmtvsra i64:$RA))]>,1360 Requires<[IsPPC64]>;1361 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1362 let isCodeGenOnly = 1, hasSideEffects = 1 in1363 def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA),1364 "mtvsrd $XT, $RA", IIC_VecGeneral,1365 []>,1366 Requires<[IsPPC64]>;1367 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA),1368 "mtvsrwa $XT, $RA", IIC_VecGeneral,1369 [(set f64:$XT, (PPCmtvsra i32:$RA))]>;1370 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1371 let isCodeGenOnly = 1, hasSideEffects = 1 in1372 def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$RA),1373 "mtvsrwa $XT, $RA", IIC_VecGeneral,1374 []>;1375 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$RA),1376 "mtvsrwz $XT, $RA", IIC_VecGeneral,1377 [(set f64:$XT, (PPCmtvsrz i32:$RA))]>;1378 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1379 let isCodeGenOnly = 1, hasSideEffects = 1 in1380 def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$RA),1381 "mtvsrwz $XT, $RA", IIC_VecGeneral,1382 []>;1383 } // HasDirectMove1384 1385} // HasVSX, HasP8Vector1386 1387let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in {1388def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA),1389 "mtvsrws $XT, $RA", IIC_VecGeneral, []>;1390 1391def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB),1392 "mtvsrdd $XT, $RA, $RB", IIC_VecGeneral,1393 []>, Requires<[IsPPC64]>;1394 1395def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT),1396 "mfvsrld $RA, $XT", IIC_VecGeneral,1397 []>, Requires<[IsPPC64]>;1398 1399} // HasVSX, IsISA3_0, HasDirectMove1400 1401let Predicates = [HasVSX, HasP9Vector] in {1402 // Quad-Precision Scalar Move Instructions:1403 // Copy Sign1404 def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",1405 [(set f128:$RST,1406 (fcopysign f128:$RB, f128:$RA))]>;1407 1408 // Absolute/Negative-Absolute/Negate1409 def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp",1410 [(set f128:$RST, (fabs f128:$RB))]>;1411 def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp",1412 [(set f128:$RST, (fneg (fabs f128:$RB)))]>;1413 def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",1414 [(set f128:$RST, (fneg f128:$RB))]>;1415 1416 //===--------------------------------------------------------------------===//1417 // Quad-Precision Scalar Floating-Point Arithmetic Instructions:1418 1419 // Add/Divide/Multiply/Subtract1420 let mayRaiseFPException = 1 in {1421 let isCommutable = 1 in {1422 def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp",1423 [(set f128:$RST, (any_fadd f128:$RA, f128:$RB))]>;1424 def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp",1425 [(set f128:$RST, (any_fmul f128:$RA, f128:$RB))]>;1426 }1427 def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" ,1428 [(set f128:$RST, (any_fsub f128:$RA, f128:$RB))]>;1429 def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp",1430 [(set f128:$RST, (any_fdiv f128:$RA, f128:$RB))]>;1431 // Square-Root1432 def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp",1433 [(set f128:$RST, (any_fsqrt f128:$RB))]>;1434 // (Negative) Multiply-{Add/Subtract}1435 def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",1436 [(set f128:$RST,1437 (any_fma f128:$RA, f128:$RB, f128:$RSTi))]>;1438 def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" ,1439 [(set f128:$RST,1440 (any_fma f128:$RA, f128:$RB,1441 (fneg f128:$RSTi)))]>;1442 def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",1443 [(set f128:$RST,1444 (fneg (any_fma f128:$RA, f128:$RB,1445 f128:$RSTi)))]>;1446 def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",1447 [(set f128:$RST,1448 (fneg (any_fma f128:$RA, f128:$RB,1449 (fneg f128:$RSTi))))]>;1450 1451 let isCommutable = 1 in {1452 def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo",1453 [(set f128:$RST,1454 (int_ppc_addf128_round_to_odd1455 f128:$RA, f128:$RB))]>;1456 def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo",1457 [(set f128:$RST,1458 (int_ppc_mulf128_round_to_odd1459 f128:$RA, f128:$RB))]>;1460 }1461 def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo",1462 [(set f128:$RST,1463 (int_ppc_subf128_round_to_odd1464 f128:$RA, f128:$RB))]>;1465 def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo",1466 [(set f128:$RST,1467 (int_ppc_divf128_round_to_odd1468 f128:$RA, f128:$RB))]>;1469 def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo",1470 [(set f128:$RST,1471 (int_ppc_sqrtf128_round_to_odd f128:$RB))]>;1472 1473 1474 def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo",1475 [(set f128:$RST,1476 (int_ppc_fmaf128_round_to_odd1477 f128:$RA,f128:$RB,f128:$RSTi))]>;1478 1479 def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" ,1480 [(set f128:$RST,1481 (int_ppc_fmaf128_round_to_odd1482 f128:$RA, f128:$RB, (fneg f128:$RSTi)))]>;1483 def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo",1484 [(set f128:$RST,1485 (fneg (int_ppc_fmaf128_round_to_odd1486 f128:$RA, f128:$RB, f128:$RSTi)))]>;1487 def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo",1488 [(set f128:$RST,1489 (fneg (int_ppc_fmaf128_round_to_odd1490 f128:$RA, f128:$RB, (fneg f128:$RSTi))))]>;1491 } // mayRaiseFPException1492 1493 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1494 // QP Compare Ordered/Unordered1495 let hasSideEffects = 1 in {1496 // DP/QP Compare Exponents1497 def XSCMPEXPDP : XX3Form_1<60, 59,1498 (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),1499 "xscmpexpdp $CR, $XA, $XB", IIC_FPCompare, []>;1500 def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;1501 1502 let mayRaiseFPException = 1 in {1503 def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>;1504 def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>;1505 1506 // DP Compare ==, >=, >, !=1507 // Use vsrc for XT, because the entire register of XT is set.1508 // XT.dword[1] = 0x0000_0000_0000_00001509 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc,1510 IIC_FPCompare, []>;1511 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,1512 IIC_FPCompare, []>;1513 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,1514 IIC_FPCompare, []>;1515 }1516 }1517 1518 //===--------------------------------------------------------------------===//1519 // Quad-Precision Floating-Point Conversion Instructions:1520 1521 let mayRaiseFPException = 1 in {1522 // Convert DP -> QP1523 def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,1524 [(set f128:$RST, (any_fpextend f64:$RB))]>;1525 1526 // Round & Convert QP -> DP (dword[1] is set to zero)1527 def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;1528 def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",1529 [(set f64:$RST,1530 (int_ppc_truncf128_round_to_odd1531 f128:$RB))]>;1532 }1533 1534 // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)1535 let mayRaiseFPException = 1 in {1536 def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz",1537 [(set f128:$RST, (PPCany_fctidz f128:$RB))]>;1538 def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz",1539 [(set f128:$RST, (PPCany_fctiwz f128:$RB))]>;1540 def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz",1541 [(set f128:$RST, (PPCany_fctiduz f128:$RB))]>;1542 def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz",1543 [(set f128:$RST, (PPCany_fctiwuz f128:$RB))]>;1544 }1545 1546 // Convert (Un)Signed DWord -> QP.1547 def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;1548 def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;1549 1550 // (Round &) Convert DP <-> HP1551 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use1552 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,1553 // but we still use vsfrc for it.1554 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1555 let hasSideEffects = 1, mayRaiseFPException = 1 in {1556 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>;1557 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>;1558 }1559 1560 let mayRaiseFPException = 1 in {1561 // Vector HP -> SP1562 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1563 let hasSideEffects = 1 in1564 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>;1565 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc,1566 [(set v4f32:$XT,1567 (int_ppc_vsx_xvcvsphp v4f32:$XB))]>;1568 1569 // Round to Quad-Precision Integer [with Inexact]1570 def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>;1571 def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>;1572 1573 // Round Quad-Precision to Double-Extended Precision (fp80)1574 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1575 let hasSideEffects = 1 in1576 def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;1577 }1578 1579 //===--------------------------------------------------------------------===//1580 // Insert/Extract Instructions1581 1582 // Insert Exponent DP/QP1583 // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU1584 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$RA, g8rc:$RB),1585 "xsiexpdp $XT, $RA, $RB", IIC_VecFP, []>;1586 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1587 let hasSideEffects = 1 in {1588 // vB NOTE: only vB.dword[0] is used, that's why we don't use1589 // X_VT5_VA5_VB5 form1590 def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$FRT), (ins vrrc:$FRA, vsfrc:$FRB),1591 "xsiexpqp $FRT, $FRA, $FRB", IIC_VecFP, []>;1592 }1593 1594 // Extract Exponent/Significand DP/QP1595 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>;1596 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>;1597 1598 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1599 let hasSideEffects = 1 in {1600 def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>;1601 def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>;1602 }1603 1604 // Vector Insert Word1605 // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.1606 def XXINSERTW :1607 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),1608 (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM5),1609 "xxinsertw $XT, $XB, $UIM5", IIC_VecFP,1610 [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,1611 imm32SExt16:$UIM5))]>,1612 RegConstraint<"$XTi = $XT">;1613 1614 // Vector Extract Unsigned Word1615 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1616 let hasSideEffects = 1 in1617 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,1618 (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIM5),1619 "xxextractuw $XT, $XB, $UIM5", IIC_VecFP, []>;1620 1621 // Vector Insert Exponent DP/SP1622 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,1623 IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;1624 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,1625 IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;1626 1627 // Vector Extract Exponent/Significand DP/SP1628 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc,1629 [(set v2i64: $XT,1630 (int_ppc_vsx_xvxexpdp v2f64:$XB))]>;1631 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc,1632 [(set v4i32: $XT,1633 (int_ppc_vsx_xvxexpsp v4f32:$XB))]>;1634 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc,1635 [(set v2i64: $XT,1636 (int_ppc_vsx_xvxsigdp v2f64:$XB))]>;1637 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc,1638 [(set v4i32: $XT,1639 (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;1640 1641 // Test Data Class SP/DP/QP1642 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1643 let hasSideEffects = 1 in {1644 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,1645 (outs crrc:$BF), (ins u7imm:$DCMX, vssrc:$XB),1646 "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;1647 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,1648 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),1649 "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;1650 def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708,1651 (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$VB),1652 "xststdcqp $BF, $VB, $DCMX", IIC_VecFP, []>;1653 }1654 1655 // Vector Test Data Class SP/DP1656 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,1657 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),1658 "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,1659 [(set v4i32: $XT,1660 (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>;1661 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,1662 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),1663 "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,1664 [(set v2i64: $XT,1665 (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>;1666 1667 // Maximum/Minimum Type-C/Type-J DP1668 let mayRaiseFPException = 1 in {1669 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc,1670 IIC_VecFP,1671 [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>;1672 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc,1673 IIC_VecFP,1674 [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>;1675 1676 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1677 let hasSideEffects = 1 in {1678 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,1679 IIC_VecFP, []>;1680 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,1681 IIC_VecFP, []>;1682 }1683 }1684 1685 // Vector Byte-Reverse H/W/D/Q Word1686 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1687 let hasSideEffects = 1 in1688 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>;1689 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc,1690 [(set v4i32:$XT, (bswap v4i32:$XB))]>;1691 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,1692 [(set v2i64:$XT, (bswap v2i64:$XB))]>;1693 // FIXME: Setting the hasSideEffects flag here to match current behaviour.1694 let hasSideEffects = 1 in1695 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;1696 1697 // Vector Permute1698 def XXPERM : XX3Form<60, 26, (outs vsrc:$XT),1699 (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),1700 "xxperm $XT, $XA, $XB", IIC_VecPerm, []>,1701 RegConstraint<"$XTi = $XT">;1702 def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT),1703 (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),1704 "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>,1705 RegConstraint<"$XTi = $XT">;1706 1707 // Vector Splat Immediate Byte1708 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),1709 "xxspltib $XT, $IMM8", IIC_VecPerm, []>;1710 1711 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in1712 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.1713 let mayLoad = 1, mayStore = 0 in {1714 // Load Vector1715 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins (memrix16 $DQ, $RA):$addr),1716 "lxv $XT, $addr", IIC_LdStLFD, []>;1717 // Load DWord1718 def LXSD : DSForm_1<57, 2, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr),1719 "lxsd $RST, $addr", IIC_LdStLFD, []>;1720 // Load SP from src, convert it to DP, and place in dword[0]1721 def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr),1722 "lxssp $RST, $addr", IIC_LdStLFD, []>;1723 1724 // Load as Integer Byte/Halfword & Zero Indexed1725 def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,1726 [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 1))]>;1727 def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc,1728 [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 2))]>;1729 1730 // Load Vector Halfword*8/Byte*16 Indexed1731 def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;1732 def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;1733 1734 // Load Vector Indexed1735 def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc,1736 [(set v2f64:$XT, (load XForm:$addr))]>;1737 // Load Vector (Left-justified) with Length1738 def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),1739 "lxvl $XT, $addr, $RB", IIC_LdStLoad,1740 [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$addr, i64:$RB))]>;1741 def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),1742 "lxvll $XT, $addr, $RB", IIC_LdStLoad,1743 [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$addr, i64:$RB))]>;1744 1745 // Load Vector Word & Splat Indexed1746 def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;1747 } // mayLoad1748 1749 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in1750 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.1751 let mayStore = 1, mayLoad = 0 in {1752 // Store Vector1753 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, (memrix16 $DQ, $RA):$addr),1754 "stxv $XT, $addr", IIC_LdStSTFD, []>;1755 // Store DWord1756 def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr),1757 "stxsd $RST, $addr", IIC_LdStSTFD, []>;1758 // Convert DP of dword[0] to SP, and Store to dst1759 def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr),1760 "stxssp $RST, $addr", IIC_LdStSTFD, []>;1761 1762 // Store as Integer Byte/Halfword Indexed1763 def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc,1764 [(PPCstxsix f64:$XT, ForceXForm:$addr, 1)]>;1765 def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc,1766 [(PPCstxsix f64:$XT, ForceXForm:$addr, 2)]>;1767 let isCodeGenOnly = 1 in {1768 def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>;1769 def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>;1770 }1771 1772 // Store Vector Halfword*8/Byte*16 Indexed1773 def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>;1774 def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;1775 1776 // Store Vector Indexed1777 def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc,1778 [(store v2f64:$XT, XForm:$addr)]>;1779 1780 // Store Vector (Left-justified) with Length1781 def STXVL : XX1Form_memOp<31, 397, (outs),1782 (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),1783 "stxvl $XT, $addr, $RB", IIC_LdStLoad,1784 [(int_ppc_vsx_stxvl v4i32:$XT, addr:$addr,1785 i64:$RB)]>;1786 def STXVLL : XX1Form_memOp<31, 429, (outs),1787 (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),1788 "stxvll $XT, $addr, $RB", IIC_LdStLoad,1789 [(int_ppc_vsx_stxvll v4i32:$XT, addr:$addr,1790 i64:$RB)]>;1791 } // mayStore1792 1793 def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src),1794 "#DFLOADf32",1795 [(set f32:$XT, (load DSForm:$src))]>;1796 def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src),1797 "#DFLOADf64",1798 [(set f64:$XT, (load DSForm:$src))]>;1799 def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst),1800 "#DFSTOREf32",1801 [(store f32:$XT, DSForm:$dst)]>;1802 def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst),1803 "#DFSTOREf64",1804 [(store f64:$XT, DSForm:$dst)]>;1805 1806 let mayStore = 1 in {1807 def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),1808 (ins spilltovsrrc:$XT, memrr:$dst),1809 "#SPILLTOVSR_STX", []>;1810 def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),1811 "#SPILLTOVSR_ST", []>;1812 }1813 let mayLoad = 1 in {1814 def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT),1815 (ins memrr:$src),1816 "#SPILLTOVSR_LDX", []>;1817 def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src),1818 "#SPILLTOVSR_LD", []>;1819 1820 }1821 } // HasP9Vector1822} // hasSideEffects = 01823 1824let PPC970_Single = 1, AddedComplexity = 400 in {1825 1826 def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),1827 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),1828 "#SELECT_CC_VSRC",1829 []>;1830 def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),1831 (ins crbitrc:$cond, vsrc:$T, vsrc:$F),1832 "#SELECT_VSRC",1833 [(set v2f64:$dst,1834 (select i1:$cond, v2f64:$T, v2f64:$F))]>;1835 def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),1836 (ins crrc:$cond, f8rc:$T, f8rc:$F,1837 i32imm:$BROPC), "#SELECT_CC_VSFRC",1838 []>;1839 def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),1840 (ins crbitrc:$cond, f8rc:$T, f8rc:$F),1841 "#SELECT_VSFRC",1842 [(set f64:$dst,1843 (select i1:$cond, f64:$T, f64:$F))]>;1844 def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),1845 (ins crrc:$cond, f4rc:$T, f4rc:$F,1846 i32imm:$BROPC), "#SELECT_CC_VSSRC",1847 []>;1848 def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),1849 (ins crbitrc:$cond, f4rc:$T, f4rc:$F),1850 "#SELECT_VSSRC",1851 [(set f32:$dst,1852 (select i1:$cond, f32:$T, f32:$F))]>;1853}1854}1855 1856//----------------------------- DAG Definitions ------------------------------//1857 1858// Output dag used to bitcast f32 to i32 and f64 to i641859def Bitcast {1860 dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));1861 dag DblToLong = (i64 (MFVSRD $A));1862}1863 1864def FpMinMax {1865 dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC),1866 (COPY_TO_REGCLASS $B, VSFRC)),1867 VSSRC);1868 dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC),1869 (COPY_TO_REGCLASS $B, VSFRC)),1870 VSSRC);1871}1872 1873def ScalarLoads {1874 dag Li8 = (i32 (extloadi8 ForceXForm:$src));1875 dag ZELi8 = (i32 (zextloadi8 ForceXForm:$src));1876 dag ZELi8i64 = (i64 (zextloadi8 ForceXForm:$src));1877 dag SELi8 = (i32 (sext_inreg (extloadi8 ForceXForm:$src), i8));1878 dag SELi8i64 = (i64 (sext_inreg (extloadi8 ForceXForm:$src), i8));1879 1880 dag Li16 = (i32 (extloadi16 ForceXForm:$src));1881 dag ZELi16 = (i32 (zextloadi16 ForceXForm:$src));1882 dag ZELi16i64 = (i64 (zextloadi16 ForceXForm:$src));1883 dag SELi16 = (i32 (sextloadi16 ForceXForm:$src));1884 dag SELi16i64 = (i64 (sextloadi16 ForceXForm:$src));1885 1886 dag Li32 = (i32 (load ForceXForm:$src));1887}1888 1889def DWToSPExtractConv {1890 dag El0US1 = (f32 (PPCfcfidus1891 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));1892 dag El1US1 = (f32 (PPCfcfidus1893 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));1894 dag El0US2 = (f32 (PPCfcfidus1895 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));1896 dag El1US2 = (f32 (PPCfcfidus1897 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));1898 dag El0SS1 = (f32 (PPCfcfids1899 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));1900 dag El1SS1 = (f32 (PPCfcfids1901 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));1902 dag El0SS2 = (f32 (PPCfcfids1903 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));1904 dag El1SS2 = (f32 (PPCfcfids1905 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));1906 dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2));1907 dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2));1908}1909 1910def WToDPExtractConv {1911 dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0))));1912 dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1))));1913 dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2))));1914 dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3))));1915 dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0))));1916 dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1))));1917 dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2))));1918 dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3))));1919 dag BV02S = (v2f64 (build_vector El0S, El2S));1920 dag BV13S = (v2f64 (build_vector El1S, El3S));1921 dag BV02U = (v2f64 (build_vector El0U, El2U));1922 dag BV13U = (v2f64 (build_vector El1U, El3U));1923}1924 1925/* Direct moves of various widths from GPR's into VSR's. Each move lines1926 the value up into element 0 (both BE and LE). Namely, entities smaller than1927 a doubleword are shifted left and moved for BE. For LE, they're moved, then1928 swapped to go into the least significant element of the VSR.1929*/1930def MovesToVSR {1931 dag BE_BYTE_0 =1932 (MTVSRD1933 (RLDICR1934 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7));1935 dag BE_HALF_0 =1936 (MTVSRD1937 (RLDICR1938 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15));1939 dag BE_WORD_0 =1940 (MTVSRD1941 (RLDICR1942 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31));1943 dag BE_DWORD_0 = (MTVSRD $A);1944 1945 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32));1946 dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),1947 LE_MTVSRW, sub_64));1948 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2);1949 dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),1950 BE_DWORD_0, sub_64));1951 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2);1952}1953 1954/* Patterns for extracting elements out of vectors. Integer elements are1955 extracted using direct move operations. Patterns for extracting elements1956 whose indices are not available at compile time are also provided with1957 various _VARIABLE_ patterns.1958 The numbering for the DAG's is for LE, but when used on BE, the correct1959 LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13).1960*/1961def VectorExtractions {1962 // Doubleword extraction1963 dag LE_DWORD_0 =1964 (MFVSRD1965 (EXTRACT_SUBREG1966 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC),1967 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64));1968 dag LE_DWORD_1 = (MFVSRD1969 (EXTRACT_SUBREG1970 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));1971 1972 // Word extraction1973 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64));1974 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));1975 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG1976 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));1977 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));1978 1979 // Halfword extraction1980 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32));1981 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32));1982 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32));1983 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32));1984 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32));1985 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32));1986 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32));1987 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32));1988 1989 // Byte extraction1990 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32));1991 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32));1992 dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32));1993 dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32));1994 dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32));1995 dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32));1996 dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32));1997 dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32));1998 dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32));1999 dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32));2000 dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32));2001 dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32));2002 dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32));2003 dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32));2004 dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32));2005 dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32));2006 2007 /* Variable element number (BE and LE patterns must be specified separately)2008 This is a rather involved process.2009 2010 Conceptually, this is how the move is accomplished:2011 1. Identify which doubleword contains the element2012 2. Shift in the VMX register so that the correct doubleword is correctly2013 lined up for the MFVSRD2014 3. Perform the move so that the element (along with some extra stuff)2015 is in the GPR2016 4. Right shift within the GPR so that the element is right-justified2017 2018 Of course, the index is an element number which has a different meaning2019 on LE/BE so the patterns have to be specified separately.2020 2021 Note: The final result will be the element right-justified with high2022 order bits being arbitrarily defined (namely, whatever was in the2023 vector register to the left of the value originally).2024 */2025 2026 /* LE variable byte2027 Number 1. above:2028 - For elements 0-7, we shift left by 8 bytes since they're on the right2029 - For elements 8-15, we need not shift (shift left by zero bytes)2030 This is accomplished by inverting the bits of the index and AND-ing2031 with 0x8 (i.e. clearing all bits of the index and inverting bit 60).2032 */2033 dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx)));2034 2035 // Number 2. above:2036 // - Now that we set up the shift amount, we shift in the VMX register2037 dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC));2038 2039 // Number 3. above:2040 // - The doubleword containing our element is moved to a GPR2041 dag LE_MV_VBYTE = (MFVSRD2042 (EXTRACT_SUBREG2043 (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)),2044 sub_64));2045 2046 /* Number 4. above:2047 - Truncate the element number to the range 0-7 (8-15 are symmetrical2048 and out of range values are truncated accordingly)2049 - Multiply by 8 as we need to shift right by the number of bits, not bytes2050 - Shift right in the GPR by the calculated value2051 */2052 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60),2053 sub_32);2054 dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT),2055 sub_32);2056 2057 /* LE variable halfword2058 Number 1. above:2059 - For elements 0-3, we shift left by 8 since they're on the right2060 - For elements 4-7, we need not shift (shift left by zero bytes)2061 Similarly to the byte pattern, we invert the bits of the index, but we2062 AND with 0x4 (i.e. clear all bits of the index and invert bit 61).2063 Of course, the shift is still by 8 bytes, so we must multiply by 2.2064 */2065 dag LE_VHALF_PERM_VEC =2066 (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62)));2067 2068 // Number 2. above:2069 // - Now that we set up the shift amount, we shift in the VMX register2070 dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC));2071 2072 // Number 3. above:2073 // - The doubleword containing our element is moved to a GPR2074 dag LE_MV_VHALF = (MFVSRD2075 (EXTRACT_SUBREG2076 (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)),2077 sub_64));2078 2079 /* Number 4. above:2080 - Truncate the element number to the range 0-3 (4-7 are symmetrical2081 and out of range values are truncated accordingly)2082 - Multiply by 16 as we need to shift right by the number of bits2083 - Shift right in the GPR by the calculated value2084 */2085 dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59),2086 sub_32);2087 dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT),2088 sub_32);2089 2090 /* LE variable word2091 Number 1. above:2092 - For elements 0-1, we shift left by 8 since they're on the right2093 - For elements 2-3, we need not shift2094 */2095 dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,2096 (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61)));2097 2098 // Number 2. above:2099 // - Now that we set up the shift amount, we shift in the VMX register2100 dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC));2101 2102 // Number 3. above:2103 // - The doubleword containing our element is moved to a GPR2104 dag LE_MV_VWORD = (MFVSRD2105 (EXTRACT_SUBREG2106 (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)),2107 sub_64));2108 2109 /* Number 4. above:2110 - Truncate the element number to the range 0-1 (2-3 are symmetrical2111 and out of range values are truncated accordingly)2112 - Multiply by 32 as we need to shift right by the number of bits2113 - Shift right in the GPR by the calculated value2114 */2115 dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58),2116 sub_32);2117 dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT),2118 sub_32);2119 2120 /* LE variable doubleword2121 Number 1. above:2122 - For element 0, we shift left by 8 since it's on the right2123 - For element 1, we need not shift2124 */2125 dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,2126 (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60)));2127 2128 // Number 2. above:2129 // - Now that we set up the shift amount, we shift in the VMX register2130 dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC));2131 2132 // Number 3. above:2133 // - The doubleword containing our element is moved to a GPR2134 // - Number 4. is not needed for the doubleword as the value is 64-bits2135 dag LE_VARIABLE_DWORD =2136 (MFVSRD (EXTRACT_SUBREG2137 (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)),2138 sub_64));2139 2140 /* LE variable float2141 - Shift the vector to line up the desired element to BE Word 02142 - Convert 32-bit float to a 64-bit single precision float2143 */2144 dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8,2145 (RLDICR (XOR8 (LI8 3), $Idx), 2, 61)));2146 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC);2147 dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE);2148 2149 /* LE variable double2150 Same as the LE doubleword except there is no move.2151 */2152 dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2153 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2154 LE_VDWORD_PERM_VEC));2155 dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC);2156 2157 /* BE variable byte2158 The algorithm here is the same as the LE variable byte except:2159 - The shift in the VMX register is by 0/8 for opposite element numbers so2160 we simply AND the element number with 0x82161 - The order of elements after the move to GPR is reversed, so we invert2162 the bits of the index prior to truncating to the range 0-72163 */2164 dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8)));2165 dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));2166 dag BE_MV_VBYTE = (MFVSRD2167 (EXTRACT_SUBREG2168 (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)),2169 sub_64));2170 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),2171 sub_32);2172 dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT),2173 sub_32);2174 2175 /* BE variable halfword2176 The algorithm here is the same as the LE variable halfword except:2177 - The shift in the VMX register is by 0/8 for opposite element numbers so2178 we simply AND the element number with 0x4 and multiply by 22179 - The order of elements after the move to GPR is reversed, so we invert2180 the bits of the index prior to truncating to the range 0-32181 */2182 dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,2183 (RLDICR (ANDI8_rec $Idx, 4), 1, 62)));2184 dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));2185 dag BE_MV_VHALF = (MFVSRD2186 (EXTRACT_SUBREG2187 (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)),2188 sub_64));2189 dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),2190 sub_32);2191 dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT),2192 sub_32);2193 2194 /* BE variable word2195 The algorithm is the same as the LE variable word except:2196 - The shift in the VMX register happens for opposite element numbers2197 - The order of elements after the move to GPR is reversed, so we invert2198 the bits of the index prior to truncating to the range 0-12199 */2200 dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,2201 (RLDICR (ANDI8_rec $Idx, 2), 2, 61)));2202 dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));2203 dag BE_MV_VWORD = (MFVSRD2204 (EXTRACT_SUBREG2205 (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)),2206 sub_64));2207 dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58),2208 sub_32);2209 dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT),2210 sub_32);2211 2212 /* BE variable doubleword2213 Same as the LE doubleword except we shift in the VMX register for opposite2214 element indices.2215 */2216 dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,2217 (RLDICR (ANDI8_rec $Idx, 1), 3, 60)));2218 dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));2219 dag BE_VARIABLE_DWORD =2220 (MFVSRD (EXTRACT_SUBREG2221 (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)),2222 sub_64));2223 2224 /* BE variable float2225 - Shift the vector to line up the desired element to BE Word 02226 - Convert 32-bit float to a 64-bit single precision float2227 */2228 dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61)));2229 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC);2230 dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE);2231 2232 // BE variable float 32-bit version2233 dag BE_32B_VFLOAT_PERM_VEC = (v16i8 (LVSL (i32 ZERO), (RLWINM $Idx, 2, 0, 29)));2234 dag BE_32B_VFLOAT_PERMUTE = (VPERM $S, $S, BE_32B_VFLOAT_PERM_VEC);2235 dag BE_32B_VARIABLE_FLOAT = (XSCVSPDPN BE_32B_VFLOAT_PERMUTE);2236 2237 /* BE variable double2238 Same as the BE doubleword except there is no move.2239 */2240 dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2241 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2242 BE_VDWORD_PERM_VEC));2243 dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC);2244 2245 // BE variable double 32-bit version2246 dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO),2247 (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28)));2248 dag BE_32B_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2249 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),2250 BE_32B_VDWORD_PERM_VEC));2251 dag BE_32B_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_32B_VDOUBLE_PERMUTE, VSRC);2252}2253 2254def AlignValues {2255 dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B));2256 dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64);2257}2258 2259// Integer extend helper dags 32 -> 642260def AnyExts {2261 dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);2262 dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);2263 dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);2264 dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32);2265}2266 2267def DblToFlt {2268 dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0))));2269 dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1))));2270 dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0))));2271 dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1))));2272}2273 2274def ExtDbl {2275 dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));2276 dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));2277 dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));2278 dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));2279 dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));2280 dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1))))));2281 dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0))))));2282 dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1))))));2283}2284 2285def ByteToWord {2286 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));2287 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));2288 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8));2289 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8));2290 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8));2291 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8));2292 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8));2293 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8));2294}2295 2296def ByteToDWord {2297 dag LE_A0 = (i64 (sext_inreg2298 (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8));2299 dag LE_A1 = (i64 (sext_inreg2300 (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8));2301 dag BE_A0 = (i64 (sext_inreg2302 (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8));2303 dag BE_A1 = (i64 (sext_inreg2304 (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8));2305}2306 2307def HWordToWord {2308 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16));2309 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16));2310 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16));2311 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16));2312 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16));2313 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16));2314 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16));2315 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16));2316}2317 2318def HWordToDWord {2319 dag LE_A0 = (i64 (sext_inreg2320 (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16));2321 dag LE_A1 = (i64 (sext_inreg2322 (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16));2323 dag BE_A0 = (i64 (sext_inreg2324 (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16));2325 dag BE_A1 = (i64 (sext_inreg2326 (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16));2327}2328 2329def WordToDWord {2330 dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0))));2331 dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2))));2332 dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1))));2333 dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3))));2334}2335 2336def FltToIntLoad {2337 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 ForceXForm:$A)))));2338}2339def FltToUIntLoad {2340 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 ForceXForm:$A)))));2341}2342def FltToLongLoad {2343 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ForceXForm:$A)))));2344}2345def FltToLongLoadP9 {2346 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 DSForm:$A)))));2347}2348def FltToULongLoad {2349 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ForceXForm:$A)))));2350}2351def FltToULongLoadP9 {2352 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 DSForm:$A)))));2353}2354def FltToLong {2355 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A)))));2356}2357def FltToULong {2358 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A)))));2359}2360def DblToInt {2361 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));2362 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B))));2363 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C))));2364 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D))));2365}2366def DblToUInt {2367 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));2368 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B))));2369 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C))));2370 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D))));2371}2372def DblToLong {2373 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));2374}2375def DblToULong {2376 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A))));2377}2378def DblToIntLoad {2379 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ForceXForm:$A)))));2380}2381def DblToIntLoadP9 {2382 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load DSForm:$A)))));2383}2384def DblToUIntLoad {2385 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ForceXForm:$A)))));2386}2387def DblToUIntLoadP9 {2388 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load DSForm:$A)))));2389}2390def DblToLongLoad {2391 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load ForceXForm:$A)))));2392}2393def DblToULongLoad {2394 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load ForceXForm:$A)))));2395}2396 2397// FP load dags (for f32 -> v4f32)2398def LoadFP {2399 dag A = (f32 (load ForceXForm:$A));2400 dag B = (f32 (load ForceXForm:$B));2401 dag C = (f32 (load ForceXForm:$C));2402 dag D = (f32 (load ForceXForm:$D));2403}2404 2405// FP merge dags (for f32 -> v4f32)2406def MrgFP {2407 dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64);2408 dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64);2409 dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64);2410 dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64);2411 dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),2412 (SUBREG_TO_REG (i64 1), $C, sub_64), 0));2413 dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64),2414 (SUBREG_TO_REG (i64 1), $D, sub_64), 0));2415 dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0));2416 dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3));2417 dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0));2418 dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3));2419}2420 2421// Word-element merge dags - conversions from f64 to i32 merged into vectors.2422def MrgWords {2423 // For big endian, we merge low and hi doublewords (A, B).2424 dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0));2425 dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3));2426 dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1));2427 dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0));2428 dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1));2429 dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0));2430 2431 // For little endian, we merge low and hi doublewords (B, A).2432 dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0));2433 dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3));2434 dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1));2435 dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0));2436 dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1));2437 dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0));2438 2439 // For big endian, we merge hi doublewords of (A, C) and (B, D), convert2440 // then merge.2441 dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64),2442 (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0));2443 dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64),2444 (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0));2445 dag CVACS = (v4i32 (XVCVDPSXWS AC));2446 dag CVBDS = (v4i32 (XVCVDPSXWS BD));2447 dag CVACU = (v4i32 (XVCVDPUXWS AC));2448 dag CVBDU = (v4i32 (XVCVDPUXWS BD));2449 2450 // For little endian, we merge hi doublewords of (D, B) and (C, A), convert2451 // then merge.2452 dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64),2453 (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0));2454 dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64),2455 (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0));2456 dag CVDBS = (v4i32 (XVCVDPSXWS DB));2457 dag CVCAS = (v4i32 (XVCVDPSXWS CA));2458 dag CVDBU = (v4i32 (XVCVDPUXWS DB));2459 dag CVCAU = (v4i32 (XVCVDPUXWS CA));2460}2461 2462def DblwdCmp {2463 dag SGTW = (v2i64 (v2i64 (VCMPGTSW v2i64:$vA, v2i64:$vB)));2464 dag UGTW = (v2i64 (v2i64 (VCMPGTUW v2i64:$vA, v2i64:$vB)));2465 dag EQW = (v2i64 (v2i64 (VCMPEQUW v2i64:$vA, v2i64:$vB)));2466 dag UGTWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI UGTW, UGTW, 1)), EQW));2467 dag EQWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI EQW, EQW, 1)), EQW));2468 dag SGTWOR = (v2i64 (XXLOR SGTW, UGTWSHAND));2469 dag UGTWOR = (v2i64 (XXLOR UGTW, UGTWSHAND));2470 dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)),2471 (v2i64 (XXSPLTW SGTWOR, 2)), 0));2472 dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)),2473 (v2i64 (XXSPLTW UGTWOR, 2)), 0));2474 dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)),2475 (v2i64 (XXSPLTW EQWSHAND, 2)), 0));2476}2477 2478//---------------------------- Anonymous Patterns ----------------------------//2479// Predicate combinations are kept in roughly chronological order in terms of2480// instruction availability in the architecture. For example, VSX came in with2481// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and2482// ISA 3.0 (Power9). However, the granularity of features on later subtargets2483// is finer for various reasons. For example, we have Power8Vector,2484// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is2485// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there2486// are orthogonal predicates such as endianness for which the order was2487// arbitrarily chosen to be Big, Little.2488//2489// Predicate combinations available:2490// [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr.2491// [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr.2492// [HasVSX]2493// [HasVSX, IsBigEndian]2494// [HasVSX, IsLittleEndian]2495// [HasVSX, NoP9Vector]2496// [HasVSX, NoP9Vector, IsLittleEndian]2497// [HasVSX, NoP9Vector, IsBigEndian]2498// [HasVSX, HasOnlySwappingMemOps]2499// [HasVSX, HasOnlySwappingMemOps, IsBigEndian]2500// [HasVSX, NoP8Vector]2501// [HasVSX, HasP8Vector]2502// [HasVSX, HasP8Vector, IsBigEndian]2503// [HasVSX, HasP8Vector, IsBigEndian, IsPPC64]2504// [HasVSX, HasP8Vector, IsLittleEndian]2505// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64]2506// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian]2507// [HasVSX, HasP8Altivec]2508// [HasVSX, HasDirectMove]2509// [HasVSX, HasDirectMove, IsBigEndian]2510// [HasVSX, HasDirectMove, IsLittleEndian]2511// [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64]2512// [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64]2513// [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian]2514// [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian]2515// [HasVSX, HasP9Vector]2516// [HasVSX, HasP9Vector, NoP10Vector]2517// [HasVSX, HasP9Vector, IsBigEndian]2518// [HasVSX, HasP9Vector, IsBigEndian, IsPPC64]2519// [HasVSX, HasP9Vector, IsLittleEndian]2520// [HasVSX, HasP9Altivec]2521// [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64]2522// [HasVSX, HasP9Altivec, IsLittleEndian]2523// [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64]2524// [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian]2525 2526// These Altivec patterns are here because we need a VSX instruction to match2527// the intrinsic (but only for little endian system).2528let Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in2529 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,2530 v16i8:$b, v16i8:$c)),2531 (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC),2532 (COPY_TO_REGCLASS $c, VSRC))))>;2533let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in2534 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,2535 v16i8:$b, v16i8:$c)),2536 (v16i8 (VPERMXOR $a, $b, $c))>;2537let Predicates = [HasVSX, HasP8Altivec] in2538 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a,2539 v16i8:$b, v16i8:$c)),2540 (v16i8 (VPERMXOR $a, $b, $c))>;2541 2542let AddedComplexity = 400 in {2543// Valid for any VSX subtarget, regardless of endianness.2544let Predicates = [HasVSX] in {2545def : Pat<(v4i32 (vnot v4i32:$A)),2546 (v4i32 (XXLNOR $A, $A))>;2547def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A),2548 (and v4i32:$B, v4i32:$C))),2549 (v4i32 (XXSEL $A, $B, $C))>;2550 2551def : Pat<(f64 (fpimm0neg)),2552 (f64 (XSNEGDP (XXLXORdpz)))>;2553 2554def : Pat<(f64 (nzFPImmExactInti5:$A)),2555 (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS2556 (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSFRC)>;2557 2558// Additional fnmsub pattern for PPC specific ISD opcode2559def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),2560 (XSNMSUBADP $C, $A, $B)>;2561def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),2562 (XSMSUBADP $C, $A, $B)>;2563def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),2564 (XSNMADDADP $C, $A, $B)>;2565 2566def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C),2567 (XVNMSUBADP $C, $A, $B)>;2568def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)),2569 (XVMSUBADP $C, $A, $B)>;2570def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)),2571 (XVNMADDADP $C, $A, $B)>;2572 2573def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),2574 (XVNMSUBASP $C, $A, $B)>;2575def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)),2576 (XVMSUBASP $C, $A, $B)>;2577def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)),2578 (XVNMADDASP $C, $A, $B)>;2579 2580def : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>;2581def : Pat<(PPCfsqrt v2f64:$frA), (XVSQRTDP $frA)>;2582def : Pat<(PPCfsqrt v4f32:$frA), (XVSQRTSP $frA)>;2583 2584def : Pat<(v2f64 (bitconvert v4f32:$A)),2585 (COPY_TO_REGCLASS $A, VSRC)>;2586def : Pat<(v2f64 (bitconvert v4i32:$A)),2587 (COPY_TO_REGCLASS $A, VSRC)>;2588def : Pat<(v2f64 (bitconvert v8i16:$A)),2589 (COPY_TO_REGCLASS $A, VSRC)>;2590def : Pat<(v2f64 (bitconvert v16i8:$A)),2591 (COPY_TO_REGCLASS $A, VSRC)>;2592 2593def : Pat<(v4f32 (bitconvert v2f64:$A)),2594 (COPY_TO_REGCLASS $A, VRRC)>;2595def : Pat<(v4i32 (bitconvert v2f64:$A)),2596 (COPY_TO_REGCLASS $A, VRRC)>;2597def : Pat<(v8i16 (bitconvert v2f64:$A)),2598 (COPY_TO_REGCLASS $A, VRRC)>;2599def : Pat<(v16i8 (bitconvert v2f64:$A)),2600 (COPY_TO_REGCLASS $A, VRRC)>;2601 2602def : Pat<(v2i64 (bitconvert v4f32:$A)),2603 (COPY_TO_REGCLASS $A, VSRC)>;2604def : Pat<(v2i64 (bitconvert v4i32:$A)),2605 (COPY_TO_REGCLASS $A, VSRC)>;2606def : Pat<(v2i64 (bitconvert v8i16:$A)),2607 (COPY_TO_REGCLASS $A, VSRC)>;2608def : Pat<(v2i64 (bitconvert v16i8:$A)),2609 (COPY_TO_REGCLASS $A, VSRC)>;2610 2611def : Pat<(v4f32 (bitconvert v2i64:$A)),2612 (COPY_TO_REGCLASS $A, VRRC)>;2613def : Pat<(v4i32 (bitconvert v2i64:$A)),2614 (COPY_TO_REGCLASS $A, VRRC)>;2615def : Pat<(v8i16 (bitconvert v2i64:$A)),2616 (COPY_TO_REGCLASS $A, VRRC)>;2617def : Pat<(v16i8 (bitconvert v2i64:$A)),2618 (COPY_TO_REGCLASS $A, VRRC)>;2619 2620def : Pat<(v2f64 (bitconvert v2i64:$A)),2621 (COPY_TO_REGCLASS $A, VRRC)>;2622def : Pat<(v2i64 (bitconvert v2f64:$A)),2623 (COPY_TO_REGCLASS $A, VRRC)>;2624 2625def : Pat<(v2f64 (bitconvert v1i128:$A)),2626 (COPY_TO_REGCLASS $A, VRRC)>;2627def : Pat<(v1i128 (bitconvert v2f64:$A)),2628 (COPY_TO_REGCLASS $A, VRRC)>;2629 2630def : Pat<(v2i64 (bitconvert f128:$A)),2631 (COPY_TO_REGCLASS $A, VRRC)>;2632def : Pat<(v4i32 (bitconvert f128:$A)),2633 (COPY_TO_REGCLASS $A, VRRC)>;2634def : Pat<(v8i16 (bitconvert f128:$A)),2635 (COPY_TO_REGCLASS $A, VRRC)>;2636def : Pat<(v16i8 (bitconvert f128:$A)),2637 (COPY_TO_REGCLASS $A, VRRC)>;2638 2639def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)),2640 (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>;2641def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)),2642 (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>;2643 2644def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)),2645 (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>;2646def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)),2647 (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>;2648 2649def : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>;2650def : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>;2651 2652// Permutes.2653def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;2654def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;2655def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;2656def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;2657def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>;2658 2659// PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and2660// XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable.2661def : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)),2662 (XXPERMDI $src, $src, 2)>;2663 2664// Selects.2665def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),2666 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;2667def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),2668 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;2669def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),2670 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;2671def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)),2672 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;2673def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),2674 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;2675def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),2676 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;2677def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),2678 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;2679def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),2680 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;2681def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),2682 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;2683def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),2684 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;2685 2686def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),2687 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;2688def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),2689 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;2690def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),2691 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;2692def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),2693 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;2694def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),2695 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;2696def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),2697 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;2698def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),2699 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;2700def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),2701 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;2702def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),2703 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;2704def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),2705 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;2706 2707// Divides.2708def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),2709 (XVDIVSP $A, $B)>;2710def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),2711 (XVDIVDP $A, $B)>;2712 2713// Vector test for software divide and sqrt.2714def : Pat<(i32 (int_ppc_vsx_xvtdivdp v2f64:$A, v2f64:$B)),2715 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;2716def : Pat<(i32 (int_ppc_vsx_xvtdivsp v4f32:$A, v4f32:$B)),2717 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;2718def : Pat<(i32 (int_ppc_vsx_xvtsqrtdp v2f64:$A)),2719 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;2720def : Pat<(i32 (int_ppc_vsx_xvtsqrtsp v4f32:$A)),2721 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;2722 2723// Reciprocal estimate2724def : Pat<(int_ppc_vsx_xvresp v4f32:$A),2725 (XVRESP $A)>;2726def : Pat<(int_ppc_vsx_xvredp v2f64:$A),2727 (XVREDP $A)>;2728 2729// Recip. square root estimate2730def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),2731 (XVRSQRTESP $A)>;2732def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),2733 (XVRSQRTEDP $A)>;2734 2735// Vector selection2736def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),2737 (COPY_TO_REGCLASS2738 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),2739 (COPY_TO_REGCLASS $vB, VSRC),2740 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2741def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),2742 (COPY_TO_REGCLASS2743 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),2744 (COPY_TO_REGCLASS $vB, VSRC),2745 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2746def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),2747 (XXSEL $vC, $vB, $vA)>;2748def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),2749 (XXSEL $vC, $vB, $vA)>;2750def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),2751 (XXSEL $vC, $vB, $vA)>;2752def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),2753 (XXSEL $vC, $vB, $vA)>;2754def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)),2755 (COPY_TO_REGCLASS2756 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),2757 (COPY_TO_REGCLASS $vB, VSRC),2758 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2759 2760def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)),2761 (v4f32 (XVMAXSP $src1, $src2))>;2762def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)),2763 (v4f32 (XVMINSP $src1, $src2))>;2764def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)),2765 (v2f64 (XVMAXDP $src1, $src2))>;2766def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)),2767 (v2f64 (XVMINDP $src1, $src2))>;2768 2769// f32 abs2770def : Pat<(f32 (fabs f32:$S)),2771 (f32 (COPY_TO_REGCLASS (XSABSDP2772 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2773 2774// f32 nabs2775def : Pat<(f32 (fneg (fabs f32:$S))),2776 (f32 (COPY_TO_REGCLASS (XSNABSDP2777 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2778 2779// f32 Min.2780def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)),2781 (f32 FpMinMax.F32Min)>;2782def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)),2783 (f32 FpMinMax.F32Min)>;2784def : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))),2785 (f32 FpMinMax.F32Min)>;2786def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),2787 (f32 FpMinMax.F32Min)>;2788// F32 Max.2789def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)),2790 (f32 FpMinMax.F32Max)>;2791def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)),2792 (f32 FpMinMax.F32Max)>;2793def : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))),2794 (f32 FpMinMax.F32Max)>;2795def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),2796 (f32 FpMinMax.F32Max)>;2797 2798// f64 Min.2799def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)),2800 (f64 (XSMINDP $A, $B))>;2801def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)),2802 (f64 (XSMINDP $A, $B))>;2803def : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))),2804 (f64 (XSMINDP $A, $B))>;2805def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),2806 (f64 (XSMINDP $A, $B))>;2807// f64 Max.2808def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)),2809 (f64 (XSMAXDP $A, $B))>;2810def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)),2811 (f64 (XSMAXDP $A, $B))>;2812def : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))),2813 (f64 (XSMAXDP $A, $B))>;2814def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),2815 (f64 (XSMAXDP $A, $B))>;2816 2817def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, ForceXForm:$dst),2818 (STXVD2X $rS, ForceXForm:$dst)>;2819def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, ForceXForm:$dst),2820 (STXVW4X $rS, ForceXForm:$dst)>;2821def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;2822def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;2823 2824// Rounding for single precision.2825def : Pat<(f32 (any_fround f32:$S)),2826 (f32 (COPY_TO_REGCLASS (XSRDPI2827 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2828def : Pat<(f32 (any_ffloor f32:$S)),2829 (f32 (COPY_TO_REGCLASS (XSRDPIM2830 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2831def : Pat<(f32 (any_fceil f32:$S)),2832 (f32 (COPY_TO_REGCLASS (XSRDPIP2833 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2834def : Pat<(f32 (any_ftrunc f32:$S)),2835 (f32 (COPY_TO_REGCLASS (XSRDPIZ2836 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2837def : Pat<(f32 (any_frint f32:$S)),2838 (f32 (COPY_TO_REGCLASS (XSRDPIC2839 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2840def : Pat<(v4f32 (any_frint v4f32:$S)), (v4f32 (XVRSPIC $S))>;2841 2842// Rounding for double precision.2843def : Pat<(f64 (any_frint f64:$S)), (f64 (XSRDPIC $S))>;2844def : Pat<(v2f64 (any_frint v2f64:$S)), (v2f64 (XVRDPIC $S))>;2845 2846// Rounding without exceptions (nearbyint). Due to strange tblgen behaviour,2847// these need to be defined after the any_frint versions so ISEL will correctly2848// add the chain to the strict versions.2849// TODO: Match strict fp rounding intrinsics with instructions like xsrdpiz when2850// rounding mode is propagated to CodeGen part.2851def : Pat<(f32 (strict_fnearbyint f32:$S)),2852 (f32 (COPY_TO_REGCLASS (XSRDPIC2853 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;2854def : Pat<(f64 (strict_fnearbyint f64:$S)),2855 (f64 (XSRDPIC $S))>;2856def : Pat<(v2f64 (strict_fnearbyint v2f64:$S)),2857 (v2f64 (XVRDPIC $S))>;2858def : Pat<(v4f32 (strict_fnearbyint v4f32:$S)),2859 (v4f32 (XVRSPIC $S))>;2860 2861// Materialize a zero-vector of long long2862def : Pat<(v2i64 immAllZerosV),2863 (v2i64 (XXLXORz))>;2864 2865// Build vectors of floating point converted to i32.2866def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A,2867 DblToInt.A, DblToInt.A)),2868 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>;2869def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A,2870 DblToUInt.A, DblToUInt.A)),2871 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>;2872def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)),2873 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64),2874 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>;2875def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)),2876 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64),2877 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>;2878def : Pat<(v4i32 (PPCSToV DblToInt.A)),2879 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;2880def : Pat<(v4i32 (PPCSToV DblToUInt.A)),2881 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>;2882defm : ScalToVecWPermute<2883 v4i32, FltToIntLoad.A,2884 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),2885 (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;2886defm : ScalToVecWPermute<2887 v4i32, FltToUIntLoad.A,2888 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),2889 (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;2890def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)),2891 (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))),2892 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>;2893 2894def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),2895 (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;2896 2897// Splat loads.2898def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)),2899 (v2f64 (LXVDSX ForceXForm:$A))>;2900def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),2901 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;2902def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)),2903 (v2i64 (LXVDSX ForceXForm:$A))>;2904def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),2905 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;2906def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),2907 (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;2908def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),2909 (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;2910 2911// Build vectors of floating point converted to i64.2912def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),2913 (v2i64 (XXPERMDIs2914 (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;2915def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),2916 (v2i64 (XXPERMDIs2917 (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;2918defm : ScalToVecWPermute<2919 v2i64, DblToLongLoad.A,2920 (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>;2921defm : ScalToVecWPermute<2922 v2i64, DblToULongLoad.A,2923 (XVCVDPUXDS (LXVDSX ForceXForm:$A)), (XVCVDPUXDS (LXVDSX ForceXForm:$A))>;2924 2925// Doubleword vector predicate comparisons without Power8.2926let AddedComplexity = 0 in {2927def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)),2928 (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>;2929def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)),2930 (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>;2931def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),2932 (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;2933} // AddedComplexity = 02934 2935// XL Compat builtins.2936def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>;2937def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;2938def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;2939def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;2940def : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>;2941def : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>;2942 2943// XXMRG[LH]W is a direct replacement for VMRG[LH]W respectively.2944// Prefer the VSX form for greater register range.2945def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),2946 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC),2947 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2948def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),2949 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC),2950 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2951def:Pat<(vmrglw_shuffle v16i8:$vA, v16i8:$vB),2952 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC),2953 (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>;2954def:Pat<(vmrghw_shuffle v16i8:$vA, v16i8:$vB),2955 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC),2956 (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>;2957def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),2958 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vB, VSRC),2959 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2960def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),2961 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vB, VSRC),2962 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;2963def : Pat<(PPCstore_scal_int_from_vsr f64:$src, XForm:$dst, 8),2964 (STXSDX $src, XForm:$dst)>;2965def : Pat<(PPCstore_scal_int_from_vsr f128:$src, XForm:$dst, 8),2966 (STXSDX (COPY_TO_REGCLASS $src, VSFRC), XForm:$dst)>;2967} // HasVSX2968 2969// Any big endian VSX subtarget.2970let Predicates = [HasVSX, IsBigEndian] in {2971def : Pat<(v2f64 (scalar_to_vector f64:$A)),2972 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;2973 2974def : Pat<(f64 (extractelt v2f64:$S, 0)),2975 (f64 (EXTRACT_SUBREG $S, sub_64))>;2976def : Pat<(f64 (extractelt v2f64:$S, 1)),2977 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;2978def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),2979 (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;2980def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),2981 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;2982def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),2983 (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;2984def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),2985 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;2986 2987def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),2988 (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>;2989 2990def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),2991 (v2f64 (XXPERMDI2992 (SUBREG_TO_REG (i64 1), $A, sub_64),2993 (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;2994// Using VMRGEW to assemble the final vector would be a lower latency2995// solution. However, we choose to go with the slightly higher latency2996// XXPERMDI for 2 reasons:2997// 1. This is likely to occur in unrolled loops where regpressure is high,2998// so we want to use the latter as it has access to all 64 VSX registers.2999// 2. Using Altivec instructions in this sequence would likely cause the3000// allocation of Altivec registers even for the loads which in turn would3001// force the use of LXSIWZX for the loads, adding a cycle of latency to3002// each of the loads which would otherwise be able to use LFIWZX.3003def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),3004 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B),3005 (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>;3006def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)),3007 (VMRGEW MrgFP.AC, MrgFP.BD)>;3008def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,3009 DblToFlt.B0, DblToFlt.B1)),3010 (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>;3011 3012// Convert 4 doubles to a vector of ints.3013def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,3014 DblToInt.C, DblToInt.D)),3015 (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>;3016def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,3017 DblToUInt.C, DblToUInt.D)),3018 (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>;3019def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,3020 ExtDbl.B0S, ExtDbl.B1S)),3021 (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>;3022def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,3023 ExtDbl.B0U, ExtDbl.B1U)),3024 (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>;3025def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3026 (f64 (fpextend (extractelt v4f32:$A, 1))))),3027 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;3028def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3029 (f64 (fpextend (extractelt v4f32:$A, 0))))),3030 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),3031 (XVCVSPDP (XXMRGHW $A, $A)), 2))>;3032def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3033 (f64 (fpextend (extractelt v4f32:$A, 2))))),3034 (v2f64 (XVCVSPDP $A))>;3035def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3036 (f64 (fpextend (extractelt v4f32:$A, 3))))),3037 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>;3038def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),3039 (f64 (fpextend (extractelt v4f32:$A, 3))))),3040 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;3041def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),3042 (f64 (fpextend (extractelt v4f32:$A, 2))))),3043 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),3044 (XVCVSPDP (XXMRGLW $A, $A)), 2))>;3045def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3046 (f64 (fpextend (extractelt v4f32:$B, 0))))),3047 (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>;3048def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),3049 (f64 (fpextend (extractelt v4f32:$B, 3))))),3050 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3),3051 (XXPERMDI $A, $B, 3), 1)))>;3052def : Pat<(v2i64 (fp_to_sint3053 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3054 (f64 (fpextend (extractelt v4f32:$A, 2)))))),3055 (v2i64 (XVCVSPSXDS $A))>;3056def : Pat<(v2i64 (fp_to_uint3057 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3058 (f64 (fpextend (extractelt v4f32:$A, 2)))))),3059 (v2i64 (XVCVSPUXDS $A))>;3060def : Pat<(v2i64 (fp_to_sint3061 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3062 (f64 (fpextend (extractelt v4f32:$A, 3)))))),3063 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>;3064def : Pat<(v2i64 (fp_to_uint3065 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3066 (f64 (fpextend (extractelt v4f32:$A, 3)))))),3067 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>;3068def : Pat<WToDPExtractConv.BV02S,3069 (v2f64 (XVCVSXWDP $A))>;3070def : Pat<WToDPExtractConv.BV13S,3071 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;3072def : Pat<WToDPExtractConv.BV02U,3073 (v2f64 (XVCVUXWDP $A))>;3074def : Pat<WToDPExtractConv.BV13U,3075 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;3076def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),3077 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;3078def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),3079 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;3080} // HasVSX, IsBigEndian3081 3082// Any little endian VSX subtarget.3083let Predicates = [HasVSX, IsLittleEndian] in {3084defm : ScalToVecWPermute<v2f64, (f64 f64:$A),3085 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),3086 (SUBREG_TO_REG (i64 1), $A, sub_64), 0),3087 (SUBREG_TO_REG (i64 1), $A, sub_64)>;3088 3089def : Pat<(f64 (extractelt v2f64:$S, 0)),3090 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;3091def : Pat<(f64 (extractelt v2f64:$S, 1)),3092 (f64 (EXTRACT_SUBREG $S, sub_64))>;3093 3094def : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;3095def : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;3096def : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;3097def : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;3098def : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;3099def : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;3100def : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;3101def : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;3102def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),3103 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;3104def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),3105 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;3106def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),3107 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;3108def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),3109 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;3110 3111def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),3112 (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>;3113 3114// Little endian, available on all targets with VSX3115def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),3116 (v2f64 (XXPERMDI3117 (SUBREG_TO_REG (i64 1), $B, sub_64),3118 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;3119// Using VMRGEW to assemble the final vector would be a lower latency3120// solution. However, we choose to go with the slightly higher latency3121// XXPERMDI for 2 reasons:3122// 1. This is likely to occur in unrolled loops where regpressure is high,3123// so we want to use the latter as it has access to all 64 VSX registers.3124// 2. Using Altivec instructions in this sequence would likely cause the3125// allocation of Altivec registers even for the loads which in turn would3126// force the use of LXSIWZX for the loads, adding a cycle of latency to3127// each of the loads which would otherwise be able to use LFIWZX.3128def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),3129 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C),3130 (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>;3131def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)),3132 (VMRGEW MrgFP.AC, MrgFP.BD)>;3133def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,3134 DblToFlt.B0, DblToFlt.B1)),3135 (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>;3136 3137// Convert 4 doubles to a vector of ints.3138def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,3139 DblToInt.C, DblToInt.D)),3140 (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>;3141def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,3142 DblToUInt.C, DblToUInt.D)),3143 (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>;3144def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,3145 ExtDbl.B0S, ExtDbl.B1S)),3146 (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>;3147def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,3148 ExtDbl.B0U, ExtDbl.B1U)),3149 (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>;3150def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3151 (f64 (fpextend (extractelt v4f32:$A, 1))))),3152 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;3153def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3154 (f64 (fpextend (extractelt v4f32:$A, 0))))),3155 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),3156 (XVCVSPDP (XXMRGLW $A, $A)), 2))>;3157def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3158 (f64 (fpextend (extractelt v4f32:$A, 2))))),3159 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>;3160def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3161 (f64 (fpextend (extractelt v4f32:$A, 3))))),3162 (v2f64 (XVCVSPDP $A))>;3163def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),3164 (f64 (fpextend (extractelt v4f32:$A, 3))))),3165 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;3166def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),3167 (f64 (fpextend (extractelt v4f32:$A, 2))))),3168 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),3169 (XVCVSPDP (XXMRGHW $A, $A)), 2))>;3170def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3171 (f64 (fpextend (extractelt v4f32:$B, 0))))),3172 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3),3173 (XXPERMDI $B, $A, 3), 1)))>;3174def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),3175 (f64 (fpextend (extractelt v4f32:$B, 3))))),3176 (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>;3177def : Pat<(v2i64 (fp_to_sint3178 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3179 (f64 (fpextend (extractelt v4f32:$A, 3)))))),3180 (v2i64 (XVCVSPSXDS $A))>;3181def : Pat<(v2i64 (fp_to_uint3182 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),3183 (f64 (fpextend (extractelt v4f32:$A, 3)))))),3184 (v2i64 (XVCVSPUXDS $A))>;3185def : Pat<(v2i64 (fp_to_sint3186 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3187 (f64 (fpextend (extractelt v4f32:$A, 2)))))),3188 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>;3189def : Pat<(v2i64 (fp_to_uint3190 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),3191 (f64 (fpextend (extractelt v4f32:$A, 2)))))),3192 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>;3193def : Pat<WToDPExtractConv.BV02S,3194 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;3195def : Pat<WToDPExtractConv.BV13S,3196 (v2f64 (XVCVSXWDP $A))>;3197def : Pat<WToDPExtractConv.BV02U,3198 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;3199def : Pat<WToDPExtractConv.BV13U,3200 (v2f64 (XVCVUXWDP $A))>;3201def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),3202 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;3203def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),3204 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;3205} // HasVSX, IsLittleEndian3206 3207// Any pre-Power9 VSX subtarget.3208let Predicates = [HasVSX, NoP9Vector] in {3209def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 8),3210 (STXSDX $src, ForceXForm:$dst)>;3211def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8),3212 (STXSDX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;3213 3214// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads).3215defm : ScalToVecWPermute<3216 v4i32, DblToIntLoad.A,3217 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),3218 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;3219defm : ScalToVecWPermute<3220 v4i32, DblToUIntLoad.A,3221 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),3222 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;3223defm : ScalToVecWPermute<3224 v2i64, FltToLongLoad.A,3225 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),3226 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),3227 VSFRC)), sub_64)>;3228defm : ScalToVecWPermute<3229 v2i64, FltToULongLoad.A,3230 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),3231 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),3232 VSFRC)), sub_64)>;3233} // HasVSX, NoP9Vector3234 3235// Any little endian pre-Power9 VSX subtarget.3236let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in {3237// Load-and-splat using only X-Form VSX loads.3238defm : ScalToVecWPermute<3239 v2i64, (i64 (load ForceXForm:$src)),3240 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),3241 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;3242defm : ScalToVecWPermute<3243 v2f64, (f64 (load ForceXForm:$src)),3244 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),3245 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;3246 3247// Splat loads.3248def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),3249 (v8i16 (VSPLTH 7, (LVX ForceXForm:$A)))>;3250def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),3251 (v16i8 (VSPLTB 15, (LVX ForceXForm:$A)))>;3252} // HasVSX, NoP9Vector, IsLittleEndian3253 3254let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in {3255 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)),3256 (LXVD2X ForceXForm:$src)>;3257 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),3258 (STXVD2X $rS, ForceXForm:$dst)>;3259 3260 // Splat loads.3261 def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),3262 (v8i16 (VSPLTH 0, (LVX ForceXForm:$A)))>;3263 def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),3264 (v16i8 (VSPLTB 0, (LVX ForceXForm:$A)))>;3265} // HasVSX, NoP9Vector, IsBigEndian3266 3267// Any VSX subtarget that only has loads and stores that load in big endian3268// order regardless of endianness. This is really pre-Power9 subtargets.3269let Predicates = [HasVSX, HasOnlySwappingMemOps] in {3270 def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;3271 3272 // Stores.3273 def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;3274} // HasVSX, HasOnlySwappingMemOps3275 3276// Big endian VSX subtarget that only has loads and stores that always3277// load in big endian order. Really big endian pre-Power9 subtargets.3278let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in {3279 def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;3280 def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;3281 def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;3282 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;3283 def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;3284 def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;3285 def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>;3286 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst),3287 (STXVW4X $rS, ForceXForm:$dst)>;3288 def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))),3289 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;3290} // HasVSX, HasOnlySwappingMemOps, IsBigEndian3291 3292// Target before Power8 with VSX.3293let Predicates = [HasVSX, NoP8Vector] in {3294def : Pat<(f32 (fpimm0neg)),3295 (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), F4RC))>;3296 3297def : Pat<(f32 (nzFPImmExactInti5:$A)),3298 (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS3299 (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), F4RC)>;3300 3301} // HasVSX, NoP8Vector3302 3303// Any Power8 VSX subtarget.3304let Predicates = [HasVSX, HasP8Vector] in {3305def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),3306 (XXLEQV $A, $B)>;3307def : Pat<(f64 (extloadf32 XForm:$src)),3308 (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>;3309def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))),3310 (f32 (XFLOADf32 ForceXForm:$src))>;3311def : Pat<(f64 (any_fpextend f32:$src)),3312 (COPY_TO_REGCLASS $src, VSFRC)>;3313 3314def : Pat<(f32 (fpimm0neg)),3315 (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), VSSRC))>;3316 3317def : Pat<(f32 (nzFPImmExactInti5:$A)),3318 (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS3319 (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSSRC)>;3320 3321def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),3322 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;3323def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),3324 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;3325def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),3326 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;3327def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),3328 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;3329def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),3330 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;3331def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),3332 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;3333def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),3334 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;3335def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),3336 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;3337def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),3338 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;3339def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),3340 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;3341 3342// Additional fnmsub pattern for PPC specific ISD opcode3343def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C),3344 (XSNMSUBASP $C, $A, $B)>;3345def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)),3346 (XSMSUBASP $C, $A, $B)>;3347def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)),3348 (XSNMADDASP $C, $A, $B)>;3349 3350// f32 neg3351// Although XSNEGDP is available in P7, we want to select it starting from P8,3352// so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version,3353// XSNMSUBASP, is available since P8)3354def : Pat<(f32 (fneg f32:$S)),3355 (f32 (COPY_TO_REGCLASS (XSNEGDP3356 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;3357 3358// Instructions for converting float to i32 feeding a store.3359def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4),3360 (STIWX $src, ForceXForm:$dst)>;3361def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4),3362 (STIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;3363 3364def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4),3365 (STXSIWX $src, ForceXForm:$dst)>;3366def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4),3367 (STXSIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;3368 3369def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)),3370 (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC),3371 (COPY_TO_REGCLASS $src2, VRRC)))>;3372def : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)),3373 (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC),3374 (COPY_TO_REGCLASS $src2, VRRC)))>;3375def : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)),3376 (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC),3377 (COPY_TO_REGCLASS $src2, VRRC)))>;3378def : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)),3379 (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC),3380 (COPY_TO_REGCLASS $src2, VRRC)))>;3381 3382def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),3383 (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;3384def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),3385 (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;3386def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),3387 (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;3388def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),3389 (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;3390 3391// XL Compat builtins.3392def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (XSMSUBMSP $A, $B, $C)>;3393def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (XSNMADDMSP $A, $B, $C)>;3394def : Pat<(int_ppc_fres f32:$A), (XSRESP $A)>;3395def : Pat<(i32 (int_ppc_extract_exp f64:$A)),3396 (EXTRACT_SUBREG (XSXEXPDP (COPY_TO_REGCLASS $A, VSFRC)), sub_32)>;3397def : Pat<(int_ppc_extract_sig f64:$A),3398 (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>;3399def : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)),3400 (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>;3401 3402def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),3403 (STXSIWX f64:$XT, ForceXForm:$dst)>;3404def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;3405} // HasVSX, HasP8Vector3406 3407// Any big endian Power8 VSX subtarget.3408let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in {3409def : Pat<DWToSPExtractConv.El0SS1,3410 (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;3411def : Pat<DWToSPExtractConv.El1SS1,3412 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;3413def : Pat<DWToSPExtractConv.El0US1,3414 (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;3415def : Pat<DWToSPExtractConv.El1US1,3416 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;3417 3418// v4f32 scalar <-> vector conversions (BE)3419defm : ScalToVecWPermute<v4f32, (f32 f32:$A), (XSCVDPSPN $A), (XSCVDPSPN $A)>;3420def : Pat<(f32 (vector_extract v4f32:$S, 0)),3421 (f32 (XSCVSPDPN $S))>;3422def : Pat<(f32 (vector_extract v4f32:$S, 1)),3423 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;3424def : Pat<(f32 (vector_extract v4f32:$S, 2)),3425 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;3426def : Pat<(f32 (vector_extract v4f32:$S, 3)),3427 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;3428 3429def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),3430 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;3431def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),3432 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;3433def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),3434 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;3435def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),3436 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;3437def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),3438 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;3439def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),3440 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;3441def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),3442 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;3443def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),3444 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;3445 3446def : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)),3447 (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>;3448 3449def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)),3450 (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>;3451 3452defm : ScalToVecWPermute<3453 v4i32, (i32 (load ForceXForm:$src)),3454 (XXSLDWIs (LIWZX ForceXForm:$src), 1),3455 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;3456defm : ScalToVecWPermute<3457 v4f32, (f32 (load ForceXForm:$src)),3458 (XXSLDWIs (LIWZX ForceXForm:$src), 1),3459 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;3460} // HasVSX, HasP8Vector, IsBigEndian3461 3462// Big endian Power8 64Bit VSX subtarget.3463let Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in {3464def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),3465 (f32 VectorExtractions.BE_VARIABLE_FLOAT)>;3466 3467// LIWAX - This instruction is used for sign extending i32 -> i64.3468// LIWZX - This instruction will be emitted for i32, f32, and when3469// zero-extending i32 to i64 (zext i32 -> i64).3470def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))),3471 (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>;3472def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))),3473 (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>;3474 3475def : Pat<DWToSPExtractConv.BVU,3476 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3),3477 (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>;3478def : Pat<DWToSPExtractConv.BVS,3479 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3),3480 (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>;3481def : Pat<(store (i32 (extractelt v4i32:$A, 1)), ForceXForm:$src),3482 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3483def : Pat<(store (f32 (extractelt v4f32:$A, 1)), ForceXForm:$src),3484 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3485 3486// Elements in a register on a BE system are in order <0, 1, 2, 3>.3487// The store instructions store the second word from the left.3488// So to align element zero, we need to modulo-left-shift by 3 words.3489// Similar logic applies for elements 2 and 3.3490foreach Idx = [ [0,3], [2,1], [3,2] ] in {3491 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src),3492 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),3493 sub_64), ForceXForm:$src)>;3494 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src),3495 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),3496 sub_64), ForceXForm:$src)>;3497}3498} // HasVSX, HasP8Vector, IsBigEndian, IsPPC643499 3500// Little endian Power8 VSX subtarget.3501let Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in {3502def : Pat<DWToSPExtractConv.El0SS1,3503 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;3504def : Pat<DWToSPExtractConv.El1SS1,3505 (f32 (XSCVSXDSP (COPY_TO_REGCLASS3506 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;3507def : Pat<DWToSPExtractConv.El0US1,3508 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;3509def : Pat<DWToSPExtractConv.El1US1,3510 (f32 (XSCVUXDSP (COPY_TO_REGCLASS3511 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;3512 3513// v4f32 scalar <-> vector conversions (LE)3514 defm : ScalToVecWPermute<v4f32, (f32 f32:$A),3515 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1),3516 (XSCVDPSPN $A)>;3517def : Pat<(f32 (vector_extract v4f32:$S, 0)),3518 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;3519def : Pat<(f32 (vector_extract v4f32:$S, 1)),3520 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;3521def : Pat<(f32 (vector_extract v4f32:$S, 2)),3522 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;3523def : Pat<(f32 (vector_extract v4f32:$S, 3)),3524 (f32 (XSCVSPDPN $S))>;3525def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),3526 (f32 VectorExtractions.LE_VARIABLE_FLOAT)>;3527 3528def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),3529 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;3530def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),3531 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;3532def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),3533 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;3534def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),3535 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;3536def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),3537 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;3538def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),3539 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;3540def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),3541 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;3542def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),3543 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;3544 3545// LIWAX - This instruction is used for sign extending i32 -> i64.3546// LIWZX - This instruction will be emitted for i32, f32, and when3547// zero-extending i32 to i64 (zext i32 -> i64).3548defm : ScalToVecWPermute<3549 v2i64, (i64 (sextloadi32 ForceXForm:$src)),3550 (XXPERMDIs (LIWAX ForceXForm:$src), 2),3551 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>;3552 3553defm : ScalToVecWPermute<3554 v2i64, (i64 (zextloadi32 ForceXForm:$src)),3555 (XXPERMDIs (LIWZX ForceXForm:$src), 2),3556 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;3557 3558defm : ScalToVecWPermute<3559 v4i32, (i32 (load ForceXForm:$src)),3560 (XXPERMDIs (LIWZX ForceXForm:$src), 2),3561 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;3562 3563defm : ScalToVecWPermute<3564 v4f32, (f32 (load ForceXForm:$src)),3565 (XXPERMDIs (LIWZX ForceXForm:$src), 2),3566 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;3567 3568def : Pat<DWToSPExtractConv.BVU,3569 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3),3570 (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>;3571def : Pat<DWToSPExtractConv.BVS,3572 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3),3573 (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>;3574def : Pat<(store (i32 (extractelt v4i32:$A, 2)), ForceXForm:$src),3575 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3576def : Pat<(store (f32 (extractelt v4f32:$A, 2)), ForceXForm:$src),3577 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3578 3579// Elements in a register on a LE system are in order <3, 2, 1, 0>.3580// The store instructions store the second word from the left.3581// So to align element 3, we need to modulo-left-shift by 3 words.3582// Similar logic applies for elements 0 and 1.3583foreach Idx = [ [0,2], [1,1], [3,3] ] in {3584 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src),3585 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),3586 sub_64), ForceXForm:$src)>;3587 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src),3588 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),3589 sub_64), ForceXForm:$src)>;3590}3591} // HasVSX, HasP8Vector, IsLittleEndian3592 3593// Big endian pre-Power9 VSX subtarget.3594let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] in {3595def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),3596 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3597def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src),3598 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3599def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src),3600 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),3601 ForceXForm:$src)>;3602def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src),3603 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),3604 ForceXForm:$src)>;3605} // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC643606 3607// Little endian pre-Power9 VSX subtarget.3608let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in {3609def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),3610 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),3611 ForceXForm:$src)>;3612def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src),3613 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),3614 ForceXForm:$src)>;3615def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src),3616 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3617def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src),3618 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;3619} // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian3620 3621// Any VSX target with direct moves.3622let Predicates = [HasVSX, HasDirectMove] in {3623// bitconvert f32 -> i323624// (convert to 32-bit fp single, shift right 1 word, move to GPR)3625def : Pat<(i32 (bitconvert f32:$A)), Bitcast.FltToInt>;3626 3627// bitconvert i32 -> f323628// (move to FPR, shift left 1 word, convert to 64-bit fp single)3629def : Pat<(f32 (bitconvert i32:$A)),3630 (f32 (XSCVSPDPN3631 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>;3632 3633// bitconvert f64 -> i643634// (move to GPR, nothing else needed)3635def : Pat<(i64 (bitconvert f64:$A)), Bitcast.DblToLong>;3636 3637// bitconvert i64 -> f643638// (move to FPR, nothing else needed)3639def : Pat<(f64 (bitconvert i64:$S)),3640 (f64 (MTVSRD $S))>;3641 3642// Rounding to integer.3643def : Pat<(i64 (strict_lrint f64:$S)),3644 (i64 (MFVSRD (FCTID $S)))>;3645def : Pat<(i64 (strict_lrint f32:$S)),3646 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;3647def : Pat<(i64 (strict_llrint f64:$S)),3648 (i64 (MFVSRD (FCTID $S)))>;3649def : Pat<(i64 (strict_llrint f32:$S)),3650 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;3651def : Pat<(i64 (strict_lround f64:$S)),3652 (i64 (MFVSRD (FCTID (XSRDPI $S))))>;3653def : Pat<(i64 (strict_lround f32:$S)),3654 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;3655def : Pat<(i32 (strict_lround f64:$S)),3656 (i32 (MFVSRWZ (FCTIW (XSRDPI $S))))>;3657def : Pat<(i32 (strict_lround f32:$S)),3658 (i32 (MFVSRWZ (FCTIW (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;3659def : Pat<(i64 (strict_llround f64:$S)),3660 (i64 (MFVSRD (FCTID (XSRDPI $S))))>;3661def : Pat<(i64 (strict_llround f32:$S)),3662 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;3663 3664// Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead3665// of f643666def : Pat<(v8i16 (PPCmtvsrz i32:$A)),3667 (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;3668def : Pat<(v16i8 (PPCmtvsrz i32:$A)),3669 (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;3670 3671// Endianness-neutral constant splat on P8 and newer targets. The reason3672// for this pattern is that on targets with direct moves, we don't expand3673// BUILD_VECTOR nodes for v4i32.3674def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,3675 immSExt5NonZero:$A, immSExt5NonZero:$A)),3676 (v4i32 (VSPLTISW imm:$A))>;3677 3678// Splat loads.3679def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),3680 (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>;3681def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),3682 (v16i8 (VSPLTBs 7, (MTVSRWZ (LBZX ForceXForm:$A))))>;3683} // HasVSX, HasDirectMove3684 3685// Big endian VSX subtarget with direct moves.3686let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in {3687// v16i8 scalar <-> vector conversions (BE)3688defm : ScalToVecWPermute<3689 v16i8, (i32 i32:$A),3690 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64),3691 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;3692defm : ScalToVecWPermute<3693 v8i16, (i32 i32:$A),3694 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64),3695 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;3696defm : ScalToVecWPermute<3697 v4i32, (i32 i32:$A),3698 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64),3699 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;3700def : Pat<(v2i64 (scalar_to_vector i64:$A)),3701 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;3702 3703// v2i64 scalar <-> vector conversions (BE)3704def : Pat<(i64 (vector_extract v2i64:$S, 0)),3705 (i64 VectorExtractions.LE_DWORD_1)>;3706def : Pat<(i64 (vector_extract v2i64:$S, 1)),3707 (i64 VectorExtractions.LE_DWORD_0)>;3708def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),3709 (i64 VectorExtractions.BE_VARIABLE_DWORD)>;3710} // HasVSX, HasDirectMove, IsBigEndian3711 3712// Little endian VSX subtarget with direct moves.3713let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in {3714 // v16i8 scalar <-> vector conversions (LE)3715 defm : ScalToVecWPermute<v16i8, (i32 i32:$A),3716 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),3717 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;3718 defm : ScalToVecWPermute<v8i16, (i32 i32:$A),3719 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),3720 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;3721 defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0,3722 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;3723 defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0,3724 MovesToVSR.LE_DWORD_1>;3725 3726 // v2i64 scalar <-> vector conversions (LE)3727 def : Pat<(i64 (vector_extract v2i64:$S, 0)),3728 (i64 VectorExtractions.LE_DWORD_0)>;3729 def : Pat<(i64 (vector_extract v2i64:$S, 1)),3730 (i64 VectorExtractions.LE_DWORD_1)>;3731 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),3732 (i64 VectorExtractions.LE_VARIABLE_DWORD)>;3733} // HasVSX, HasDirectMove, IsLittleEndian3734 3735// Big endian pre-P9 VSX subtarget with direct moves.3736let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in {3737def : Pat<(i32 (vector_extract v16i8:$S, 0)),3738 (i32 VectorExtractions.LE_BYTE_15)>;3739def : Pat<(i32 (vector_extract v16i8:$S, 1)),3740 (i32 VectorExtractions.LE_BYTE_14)>;3741def : Pat<(i32 (vector_extract v16i8:$S, 2)),3742 (i32 VectorExtractions.LE_BYTE_13)>;3743def : Pat<(i32 (vector_extract v16i8:$S, 3)),3744 (i32 VectorExtractions.LE_BYTE_12)>;3745def : Pat<(i32 (vector_extract v16i8:$S, 4)),3746 (i32 VectorExtractions.LE_BYTE_11)>;3747def : Pat<(i32 (vector_extract v16i8:$S, 5)),3748 (i32 VectorExtractions.LE_BYTE_10)>;3749def : Pat<(i32 (vector_extract v16i8:$S, 6)),3750 (i32 VectorExtractions.LE_BYTE_9)>;3751def : Pat<(i32 (vector_extract v16i8:$S, 7)),3752 (i32 VectorExtractions.LE_BYTE_8)>;3753def : Pat<(i32 (vector_extract v16i8:$S, 8)),3754 (i32 VectorExtractions.LE_BYTE_7)>;3755def : Pat<(i32 (vector_extract v16i8:$S, 9)),3756 (i32 VectorExtractions.LE_BYTE_6)>;3757def : Pat<(i32 (vector_extract v16i8:$S, 10)),3758 (i32 VectorExtractions.LE_BYTE_5)>;3759def : Pat<(i32 (vector_extract v16i8:$S, 11)),3760 (i32 VectorExtractions.LE_BYTE_4)>;3761def : Pat<(i32 (vector_extract v16i8:$S, 12)),3762 (i32 VectorExtractions.LE_BYTE_3)>;3763def : Pat<(i32 (vector_extract v16i8:$S, 13)),3764 (i32 VectorExtractions.LE_BYTE_2)>;3765def : Pat<(i32 (vector_extract v16i8:$S, 14)),3766 (i32 VectorExtractions.LE_BYTE_1)>;3767def : Pat<(i32 (vector_extract v16i8:$S, 15)),3768 (i32 VectorExtractions.LE_BYTE_0)>;3769def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),3770 (i32 VectorExtractions.BE_VARIABLE_BYTE)>;3771 3772// v8i16 scalar <-> vector conversions (BE)3773def : Pat<(i32 (vector_extract v8i16:$S, 0)),3774 (i32 VectorExtractions.LE_HALF_7)>;3775def : Pat<(i32 (vector_extract v8i16:$S, 1)),3776 (i32 VectorExtractions.LE_HALF_6)>;3777def : Pat<(i32 (vector_extract v8i16:$S, 2)),3778 (i32 VectorExtractions.LE_HALF_5)>;3779def : Pat<(i32 (vector_extract v8i16:$S, 3)),3780 (i32 VectorExtractions.LE_HALF_4)>;3781def : Pat<(i32 (vector_extract v8i16:$S, 4)),3782 (i32 VectorExtractions.LE_HALF_3)>;3783def : Pat<(i32 (vector_extract v8i16:$S, 5)),3784 (i32 VectorExtractions.LE_HALF_2)>;3785def : Pat<(i32 (vector_extract v8i16:$S, 6)),3786 (i32 VectorExtractions.LE_HALF_1)>;3787def : Pat<(i32 (vector_extract v8i16:$S, 7)),3788 (i32 VectorExtractions.LE_HALF_0)>;3789def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),3790 (i32 VectorExtractions.BE_VARIABLE_HALF)>;3791 3792// v4i32 scalar <-> vector conversions (BE)3793def : Pat<(i32 (vector_extract v4i32:$S, 0)),3794 (i32 VectorExtractions.LE_WORD_3)>;3795def : Pat<(i32 (vector_extract v4i32:$S, 1)),3796 (i32 VectorExtractions.LE_WORD_2)>;3797def : Pat<(i32 (vector_extract v4i32:$S, 2)),3798 (i32 VectorExtractions.LE_WORD_1)>;3799def : Pat<(i32 (vector_extract v4i32:$S, 3)),3800 (i32 VectorExtractions.LE_WORD_0)>;3801def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),3802 (i32 VectorExtractions.BE_VARIABLE_WORD)>;3803} // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian3804 3805// Little endian pre-P9 VSX subtarget with direct moves.3806let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in {3807def : Pat<(i32 (vector_extract v16i8:$S, 0)),3808 (i32 VectorExtractions.LE_BYTE_0)>;3809def : Pat<(i32 (vector_extract v16i8:$S, 1)),3810 (i32 VectorExtractions.LE_BYTE_1)>;3811def : Pat<(i32 (vector_extract v16i8:$S, 2)),3812 (i32 VectorExtractions.LE_BYTE_2)>;3813def : Pat<(i32 (vector_extract v16i8:$S, 3)),3814 (i32 VectorExtractions.LE_BYTE_3)>;3815def : Pat<(i32 (vector_extract v16i8:$S, 4)),3816 (i32 VectorExtractions.LE_BYTE_4)>;3817def : Pat<(i32 (vector_extract v16i8:$S, 5)),3818 (i32 VectorExtractions.LE_BYTE_5)>;3819def : Pat<(i32 (vector_extract v16i8:$S, 6)),3820 (i32 VectorExtractions.LE_BYTE_6)>;3821def : Pat<(i32 (vector_extract v16i8:$S, 7)),3822 (i32 VectorExtractions.LE_BYTE_7)>;3823def : Pat<(i32 (vector_extract v16i8:$S, 8)),3824 (i32 VectorExtractions.LE_BYTE_8)>;3825def : Pat<(i32 (vector_extract v16i8:$S, 9)),3826 (i32 VectorExtractions.LE_BYTE_9)>;3827def : Pat<(i32 (vector_extract v16i8:$S, 10)),3828 (i32 VectorExtractions.LE_BYTE_10)>;3829def : Pat<(i32 (vector_extract v16i8:$S, 11)),3830 (i32 VectorExtractions.LE_BYTE_11)>;3831def : Pat<(i32 (vector_extract v16i8:$S, 12)),3832 (i32 VectorExtractions.LE_BYTE_12)>;3833def : Pat<(i32 (vector_extract v16i8:$S, 13)),3834 (i32 VectorExtractions.LE_BYTE_13)>;3835def : Pat<(i32 (vector_extract v16i8:$S, 14)),3836 (i32 VectorExtractions.LE_BYTE_14)>;3837def : Pat<(i32 (vector_extract v16i8:$S, 15)),3838 (i32 VectorExtractions.LE_BYTE_15)>;3839def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),3840 (i32 VectorExtractions.LE_VARIABLE_BYTE)>;3841 3842// v8i16 scalar <-> vector conversions (LE)3843def : Pat<(i32 (vector_extract v8i16:$S, 0)),3844 (i32 VectorExtractions.LE_HALF_0)>;3845def : Pat<(i32 (vector_extract v8i16:$S, 1)),3846 (i32 VectorExtractions.LE_HALF_1)>;3847def : Pat<(i32 (vector_extract v8i16:$S, 2)),3848 (i32 VectorExtractions.LE_HALF_2)>;3849def : Pat<(i32 (vector_extract v8i16:$S, 3)),3850 (i32 VectorExtractions.LE_HALF_3)>;3851def : Pat<(i32 (vector_extract v8i16:$S, 4)),3852 (i32 VectorExtractions.LE_HALF_4)>;3853def : Pat<(i32 (vector_extract v8i16:$S, 5)),3854 (i32 VectorExtractions.LE_HALF_5)>;3855def : Pat<(i32 (vector_extract v8i16:$S, 6)),3856 (i32 VectorExtractions.LE_HALF_6)>;3857def : Pat<(i32 (vector_extract v8i16:$S, 7)),3858 (i32 VectorExtractions.LE_HALF_7)>;3859def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),3860 (i32 VectorExtractions.LE_VARIABLE_HALF)>;3861 3862// v4i32 scalar <-> vector conversions (LE)3863def : Pat<(i32 (vector_extract v4i32:$S, 0)),3864 (i32 VectorExtractions.LE_WORD_0)>;3865def : Pat<(i32 (vector_extract v4i32:$S, 1)),3866 (i32 VectorExtractions.LE_WORD_1)>;3867def : Pat<(i32 (vector_extract v4i32:$S, 2)),3868 (i32 VectorExtractions.LE_WORD_2)>;3869def : Pat<(i32 (vector_extract v4i32:$S, 3)),3870 (i32 VectorExtractions.LE_WORD_3)>;3871def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),3872 (i32 VectorExtractions.LE_VARIABLE_WORD)>;3873} // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian3874 3875// Big endian pre-Power9 64Bit VSX subtarget that has direct moves.3876let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in {3877// Big endian integer vectors using direct moves.3878def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),3879 (v2i64 (XXPERMDI3880 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64),3881 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>;3882def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),3883 (XXPERMDI3884 (SUBREG_TO_REG (i64 1),3885 (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64),3886 (SUBREG_TO_REG (i64 1),3887 (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>;3888def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),3889 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>;3890} // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC643891 3892// Little endian pre-Power9 VSX subtarget that has direct moves.3893let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in {3894// Little endian integer vectors using direct moves.3895def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),3896 (v2i64 (XXPERMDI3897 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64),3898 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>;3899def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),3900 (XXPERMDI3901 (SUBREG_TO_REG (i64 1),3902 (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64),3903 (SUBREG_TO_REG (i64 1),3904 (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>;3905def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),3906 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>;3907}3908 3909// Any Power9 VSX subtarget.3910let Predicates = [HasVSX, HasP9Vector] in {3911// Additional fnmsub pattern for PPC specific ISD opcode3912def : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C),3913 (XSNMSUBQP $C, $A, $B)>;3914def : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)),3915 (XSMSUBQP $C, $A, $B)>;3916def : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)),3917 (XSNMADDQP $C, $A, $B)>;3918 3919def : Pat<(f128 (any_sint_to_fp i64:$src)),3920 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;3921def : Pat<(f128 (any_sint_to_fp (i64 (PPCmfvsr f64:$src)))),3922 (f128 (XSCVSDQP $src))>;3923def : Pat<(f128 (any_sint_to_fp (i32 (PPCmfvsr f64:$src)))),3924 (f128 (XSCVSDQP (VEXTSW2Ds $src)))>;3925def : Pat<(f128 (any_uint_to_fp i64:$src)),3926 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;3927def : Pat<(f128 (any_uint_to_fp (i64 (PPCmfvsr f64:$src)))),3928 (f128 (XSCVUDQP $src))>;3929 3930// Convert (Un)Signed Word -> QP.3931def : Pat<(f128 (any_sint_to_fp i32:$src)),3932 (f128 (XSCVSDQP (MTVSRWA $src)))>;3933def : Pat<(f128 (any_sint_to_fp (i32 (load ForceXForm:$src)))),3934 (f128 (XSCVSDQP (LIWAX ForceXForm:$src)))>;3935def : Pat<(f128 (any_uint_to_fp i32:$src)),3936 (f128 (XSCVUDQP (MTVSRWZ $src)))>;3937def : Pat<(f128 (any_uint_to_fp (i32 (load ForceXForm:$src)))),3938 (f128 (XSCVUDQP (LIWZX ForceXForm:$src)))>;3939 3940// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a3941// separate pattern so that it can convert the input register class from3942// VRRC(v8i16) to VSRC.3943def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)),3944 (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>;3945 3946// Use current rounding mode3947def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>;3948// Round to nearest, ties away from zero3949def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>;3950// Round towards Zero3951def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>;3952// Round towards +Inf3953def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>;3954// Round towards -Inf3955def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>;3956// Use current rounding mode, [with Inexact]3957def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>;3958 3959def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)),3960 (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>;3961 3962def : Pat<(i64 (int_ppc_scalar_extract_expq f128:$vA)),3963 (i64 (MFVSRD (EXTRACT_SUBREG3964 (v2i64 (XSXEXPQP $vA)), sub_64)))>;3965 3966// Extra patterns expanding to vector Extract Word/Insert Word3967def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),3968 (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;3969def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),3970 (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;3971 3972// Vector Reverse3973def : Pat<(v8i16 (bswap v8i16 :$A)),3974 (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;3975def : Pat<(v1i128 (bswap v1i128 :$A)),3976 (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;3977 3978// D-Form Load/Store3979foreach Ty = [v4i32, v4f32, v2i64, v2f64] in {3980 def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>;3981 def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>;3982 def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>;3983 def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>;3984}3985 3986def : Pat<(f128 (load DQForm:$src)),3987 (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>;3988def : Pat<(f128 (load XForm:$src)),3989 (COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>;3990def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>;3991def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>;3992def : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>;3993def : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>;3994 3995def : Pat<(store f128:$rS, DQForm:$dst),3996 (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>;3997def : Pat<(store f128:$rS, XForm:$dst),3998 (STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>;3999def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst),4000 (STXV $rS, memrix16:$dst)>;4001def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst),4002 (STXV $rS, memrix16:$dst)>;4003def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst),4004 (STXVX $rS, XForm:$dst)>;4005def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst),4006 (STXVX $rS, XForm:$dst)>;4007 4008// Build vectors from i8 loads4009defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,4010 (VSPLTHs 3, (LXSIBZX ForceXForm:$src)),4011 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;4012defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,4013 (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),4014 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;4015defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,4016 (XXPERMDIs (LXSIBZX ForceXForm:$src), 0),4017 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;4018defm : ScalToVecWPermute<4019 v4i32, ScalarLoads.SELi8,4020 (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1),4021 (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>;4022defm : ScalToVecWPermute<4023 v2i64, ScalarLoads.SELi8i64,4024 (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0),4025 (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>;4026 4027// Build vectors from i16 loads4028defm : ScalToVecWPermute<4029 v4i32, ScalarLoads.ZELi16,4030 (XXSPLTWs (LXSIHZX ForceXForm:$src), 1),4031 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;4032defm : ScalToVecWPermute<4033 v2i64, ScalarLoads.ZELi16i64,4034 (XXPERMDIs (LXSIHZX ForceXForm:$src), 0),4035 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;4036defm : ScalToVecWPermute<4037 v4i32, ScalarLoads.SELi16,4038 (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1),4039 (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>;4040defm : ScalToVecWPermute<4041 v2i64, ScalarLoads.SELi16i64,4042 (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0),4043 (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;4044 4045// Load/convert and convert/store patterns for f16.4046def : Pat<(f128 (extloadf16 ForceXForm:$src)),4047 (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src))))>;4048def : Pat<(f64 (extloadf16 ForceXForm:$src)),4049 (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;4050def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),4051 (STXSIHX (XSCVDPHP $src), ForceXForm:$dst)>;4052def : Pat<(f32 (extloadf16 ForceXForm:$src)),4053 (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), VSSRC))>;4054def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),4055 (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), ForceXForm:$dst)>;4056def : Pat<(f128 (f16_to_fp i32:$A)),4057 (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A))))>;4058def : Pat<(f64 (f16_to_fp i32:$A)),4059 (f64 (XSCVHPDP (MTVSRWZ $A)))>;4060def : Pat<(f32 (f16_to_fp i32:$A)),4061 (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>;4062def : Pat<(i32 (fp_to_f16 f32:$A)),4063 (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>;4064def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>;4065 4066// Vector sign extensions4067def : Pat<(f64 (PPCVexts f64:$A, 1)),4068 (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>;4069def : Pat<(f64 (PPCVexts f64:$A, 2)),4070 (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>;4071 4072def : Pat<(f64 (extloadf32 DSForm:$src)),4073 (COPY_TO_REGCLASS (DFLOADf32 DSForm:$src), VSFRC)>;4074def : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))),4075 (f32 (DFLOADf32 DSForm:$src))>;4076 4077def : Pat<(v4f32 (PPCldvsxlh XForm:$src)),4078 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;4079def : Pat<(v4f32 (PPCldvsxlh DSForm:$src)),4080 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;4081 4082// Convert (Un)Signed DWord in memory -> QP4083def : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))),4084 (f128 (XSCVSDQP (LXSDX XForm:$src)))>;4085def : Pat<(f128 (sint_to_fp (i64 (load DSForm:$src)))),4086 (f128 (XSCVSDQP (LXSD DSForm:$src)))>;4087def : Pat<(f128 (uint_to_fp (i64 (load XForm:$src)))),4088 (f128 (XSCVUDQP (LXSDX XForm:$src)))>;4089def : Pat<(f128 (uint_to_fp (i64 (load DSForm:$src)))),4090 (f128 (XSCVUDQP (LXSD DSForm:$src)))>;4091 4092// Convert Unsigned HWord in memory -> QP4093def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)),4094 (f128 (XSCVUDQP (LXSIHZX XForm:$src)))>;4095 4096// Convert Unsigned Byte in memory -> QP4097def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),4098 (f128 (XSCVUDQP (LXSIBZX ForceXForm:$src)))>;4099 4100// Truncate & Convert QP -> (Un)Signed (D)Word.4101def : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;4102def : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;4103def : Pat<(i32 (any_fp_to_sint f128:$src)),4104 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;4105def : Pat<(i32 (any_fp_to_uint f128:$src)),4106 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;4107 4108// Instructions for store(fptosi).4109def : Pat<(PPCstore_scal_int_from_vsr f64:$src, DSForm:$dst, 8),4110 (STXSD $src, DSForm:$dst)>;4111def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 2),4112 (STXSIHX $src, ForceXForm:$dst)>;4113def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 1),4114 (STXSIBX $src, ForceXForm:$dst)>;4115 4116def : Pat<(PPCstore_scal_int_from_vsr f128:$src, DSForm:$dst, 8),4117 (STXSD (COPY_TO_REGCLASS $src, VFRC), DSForm:$dst)>;4118def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 2),4119 (STXSIHX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;4120def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 1),4121 (STXSIBX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;4122 4123// Round & Convert QP -> DP/SP4124def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>;4125def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;4126 4127// Convert SP -> QP4128def : Pat<(f128 (any_fpextend f32:$src)),4129 (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>;4130 4131def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)),4132 (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC),4133 (COPY_TO_REGCLASS $XB, VSSRC)),4134 VSSRC))>;4135def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)),4136 (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC),4137 (COPY_TO_REGCLASS $XB, VSSRC)),4138 VSSRC))>;4139 4140// Endianness-neutral patterns for const splats with ISA 3.0 instructions.4141defm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A),4142 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;4143def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),4144 (v4i32 (MTVSRWS $A))>;4145def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4146 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4147 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4148 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4149 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4150 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4151 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,4152 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)),4153 (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;4154defm : ScalToVecWPermute<4155 v4i32, FltToIntLoad.A,4156 (XVCVSPSXWS (LXVWSX ForceXForm:$A)),4157 (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>;4158defm : ScalToVecWPermute<4159 v4i32, FltToUIntLoad.A,4160 (XVCVSPUXWS (LXVWSX ForceXForm:$A)),4161 (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>;4162defm : ScalToVecWPermute<4163 v4i32, DblToIntLoadP9.A,4164 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1),4165 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>;4166defm : ScalToVecWPermute<4167 v4i32, DblToUIntLoadP9.A,4168 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1),4169 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>;4170defm : ScalToVecWPermute<4171 v2i64, FltToLongLoadP9.A,4172 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),4173 (SUBREG_TO_REG4174 (i64 1),4175 (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;4176defm : ScalToVecWPermute<4177 v2i64, FltToULongLoadP9.A,4178 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),4179 (SUBREG_TO_REG4180 (i64 1),4181 (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;4182def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),4183 (v4f32 (LXVWSX ForceXForm:$A))>;4184def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),4185 (v4i32 (LXVWSX ForceXForm:$A))>;4186def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),4187 (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>;4188def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),4189 (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>;4190def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)),4191 (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;4192} // HasVSX, HasP9Vector4193 4194// Any Power9 VSX subtarget with equivalent length but better Power10 VSX4195// patterns.4196// Two identical blocks are required due to the slightly different predicates:4197// One without P10 instructions, the other is BigEndian only with P10 instructions.4198let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {4199// Little endian Power10 subtargets produce a shorter pattern but require a4200// COPY_TO_REGCLASS. The COPY_TO_REGCLASS makes it appear to need two instructions 4201// to perform the operation, when only one instruction is produced in practice.4202// The NoP10Vector predicate excludes these patterns from Power10 VSX subtargets.4203defm : ScalToVecWPermute<4204 v16i8, ScalarLoads.Li8,4205 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)),4206 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;4207// Build vectors from i16 loads4208defm : ScalToVecWPermute<4209 v8i16, ScalarLoads.Li16,4210 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)),4211 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;4212} // HasVSX, HasP9Vector, NoP10Vector4213 4214// Any big endian Power9 VSX subtarget4215let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in {4216// Power10 VSX subtargets produce a shorter pattern for little endian targets4217// but this is still the best pattern for Power9 and Power10 VSX big endian4218// Build vectors from i8 loads4219defm : ScalToVecWPermute<4220 v16i8, ScalarLoads.Li8,4221 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)),4222 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;4223// Build vectors from i16 loads4224defm : ScalToVecWPermute<4225 v8i16, ScalarLoads.Li16,4226 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)),4227 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;4228 4229def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),4230 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;4231def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),4232 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;4233def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),4234 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;4235def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),4236 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;4237def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),4238 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;4239def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),4240 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;4241def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),4242 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;4243def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),4244 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;4245def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),4246 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;4247def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),4248 (v4i32 (XXINSERTW v4i32:$A,4249 (SUBREG_TO_REG (i64 1),4250 (XSCVDPSXWS f64:$B), sub_64),4251 0))>;4252def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),4253 (v4i32 (XXINSERTW v4i32:$A,4254 (SUBREG_TO_REG (i64 1),4255 (XSCVDPUXWS f64:$B), sub_64),4256 0))>;4257def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),4258 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;4259def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),4260 (v4i32 (XXINSERTW v4i32:$A,4261 (SUBREG_TO_REG (i64 1),4262 (XSCVDPSXWS f64:$B), sub_64),4263 4))>;4264def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),4265 (v4i32 (XXINSERTW v4i32:$A,4266 (SUBREG_TO_REG (i64 1),4267 (XSCVDPUXWS f64:$B), sub_64),4268 4))>;4269def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),4270 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;4271def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),4272 (v4i32 (XXINSERTW v4i32:$A,4273 (SUBREG_TO_REG (i64 1),4274 (XSCVDPSXWS f64:$B), sub_64),4275 8))>;4276def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),4277 (v4i32 (XXINSERTW v4i32:$A,4278 (SUBREG_TO_REG (i64 1),4279 (XSCVDPUXWS f64:$B), sub_64),4280 8))>;4281def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),4282 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;4283def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),4284 (v4i32 (XXINSERTW v4i32:$A,4285 (SUBREG_TO_REG (i64 1),4286 (XSCVDPSXWS f64:$B), sub_64),4287 12))>;4288def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),4289 (v4i32 (XXINSERTW v4i32:$A,4290 (SUBREG_TO_REG (i64 1),4291 (XSCVDPUXWS f64:$B), sub_64),4292 12))>;4293def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),4294 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;4295def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),4296 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;4297def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),4298 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;4299def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),4300 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;4301 4302def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),4303 (v4f32 (XXINSERTW v4f32:$A,4304 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;4305def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),4306 (v4f32 (XXINSERTW v4f32:$A,4307 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;4308def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),4309 (v4f32 (XXINSERTW v4f32:$A,4310 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;4311def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),4312 (v4f32 (XXINSERTW v4f32:$A,4313 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;4314 4315// Scalar stores of i84316def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst),4317 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>;4318def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst),4319 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;4320def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst),4321 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>;4322def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst),4323 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;4324def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst),4325 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>;4326def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst),4327 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;4328def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst),4329 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>;4330def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst),4331 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;4332def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst),4333 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>;4334def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst),4335 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;4336def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst),4337 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>;4338def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst),4339 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;4340def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst),4341 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>;4342def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst),4343 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;4344def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst),4345 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>;4346def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst),4347 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;4348 4349// Scalar stores of i164350def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst),4351 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;4352def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst),4353 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;4354def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst),4355 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;4356def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst),4357 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;4358def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst),4359 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;4360def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst),4361 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;4362def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst),4363 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;4364def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst),4365 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;4366} // HasVSX, HasP9Vector, IsBigEndian4367 4368// Big endian 64Bit Power9 subtarget.4369let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in {4370def : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))),4371 (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>;4372def : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))),4373 (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>;4374 4375def : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))),4376 (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>;4377def : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))),4378 (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>;4379def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src),4380 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4381 sub_64), XForm:$src)>;4382def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src),4383 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4384 sub_64), XForm:$src)>;4385def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),4386 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;4387def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src),4388 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;4389def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src),4390 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4391 sub_64), DSForm:$src)>;4392def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src),4393 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4394 sub_64), DSForm:$src)>;4395def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src),4396 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;4397def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src),4398 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;4399 4400// (Un)Signed DWord vector extract -> QP4401def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),4402 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;4403def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),4404 (f128 (XSCVSDQP4405 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;4406def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),4407 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;4408def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),4409 (f128 (XSCVUDQP4410 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;4411 4412// (Un)Signed Word vector extract -> QP4413def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))),4414 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;4415foreach Idx = [0,2,3] in {4416 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),4417 (f128 (XSCVSDQP (EXTRACT_SUBREG4418 (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;4419}4420foreach Idx = 0-3 in {4421 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),4422 (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;4423}4424 4425// (Un)Signed HWord vector extract -> QP/DP/SP4426foreach Idx = 0-7 in {4427 def : Pat<(f128 (sint_to_fp4428 (i32 (sext_inreg4429 (vector_extract v8i16:$src, Idx), i16)))),4430 (f128 (XSCVSDQP (EXTRACT_SUBREG4431 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),4432 sub_64)))>;4433 // The SDAG adds the `and` since an `i16` is being extracted as an `i32`.4434 def : Pat<(f128 (uint_to_fp4435 (and (i32 (vector_extract v8i16:$src, Idx)), 65535))),4436 (f128 (XSCVUDQP (EXTRACT_SUBREG4437 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;4438 def : Pat<(f32 (PPCfcfidus4439 (f64 (PPCmtvsrz (and (i32 (vector_extract v8i16:$src, Idx)),4440 65535))))),4441 (f32 (XSCVUXDSP (EXTRACT_SUBREG4442 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;4443 def : Pat<(f32 (PPCfcfids4444 (f64 (PPCmtvsra4445 (i32 (sext_inreg (vector_extract v8i16:$src, Idx),4446 i16)))))),4447 (f32 (XSCVSXDSP (EXTRACT_SUBREG4448 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),4449 sub_64)))>;4450 def : Pat<(f64 (PPCfcfidu4451 (f64 (PPCmtvsrz4452 (and (i32 (vector_extract v8i16:$src, Idx)),4453 65535))))),4454 (f64 (XSCVUXDDP (EXTRACT_SUBREG4455 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;4456 def : Pat<(f64 (PPCfcfid4457 (f64 (PPCmtvsra4458 (i32 (sext_inreg (vector_extract v8i16:$src, Idx),4459 i16)))))),4460 (f64 (XSCVSXDDP (EXTRACT_SUBREG4461 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),4462 sub_64)))>;4463}4464 4465// (Un)Signed Byte vector extract -> QP4466foreach Idx = 0-15 in {4467 def : Pat<(f128 (sint_to_fp4468 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),4469 i8)))),4470 (f128 (XSCVSDQP (EXTRACT_SUBREG4471 (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>;4472 def : Pat<(f128 (uint_to_fp4473 (and (i32 (vector_extract v16i8:$src, Idx)), 255))),4474 (f128 (XSCVUDQP4475 (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;4476 4477 def : Pat<(f32 (PPCfcfidus4478 (f64 (PPCmtvsrz4479 (and (i32 (vector_extract v16i8:$src, Idx)),4480 255))))),4481 (f32 (XSCVUXDSP (EXTRACT_SUBREG4482 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;4483 def : Pat<(f32 (PPCfcfids4484 (f64 (PPCmtvsra4485 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),4486 i8)))))),4487 (f32 (XSCVSXDSP (EXTRACT_SUBREG4488 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),4489 sub_64)))>;4490 def : Pat<(f64 (PPCfcfidu4491 (f64 (PPCmtvsrz4492 (and (i32 (vector_extract v16i8:$src, Idx)),4493 255))))),4494 (f64 (XSCVUXDDP (EXTRACT_SUBREG4495 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;4496 def : Pat<(f64 (PPCfcfid4497 (f64 (PPCmtvsra4498 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),4499 i8)))))),4500 (f64 (XSCVSXDDP (EXTRACT_SUBREG4501 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),4502 sub_64)))>;4503}4504 4505// Unsiged int in vsx register -> QP4506def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),4507 (f128 (XSCVUDQP4508 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>;4509} // HasVSX, HasP9Vector, IsBigEndian, IsPPC644510 4511// Little endian Power9 subtarget.4512let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in {4513def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),4514 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;4515def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),4516 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;4517def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),4518 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;4519def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),4520 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;4521def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),4522 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;4523def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),4524 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;4525def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),4526 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;4527def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),4528 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;4529def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),4530 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;4531def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),4532 (v4i32 (XXINSERTW v4i32:$A,4533 (SUBREG_TO_REG (i64 1),4534 (XSCVDPSXWS f64:$B), sub_64),4535 12))>;4536def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),4537 (v4i32 (XXINSERTW v4i32:$A,4538 (SUBREG_TO_REG (i64 1),4539 (XSCVDPUXWS f64:$B), sub_64),4540 12))>;4541def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),4542 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;4543def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),4544 (v4i32 (XXINSERTW v4i32:$A,4545 (SUBREG_TO_REG (i64 1),4546 (XSCVDPSXWS f64:$B), sub_64),4547 8))>;4548def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),4549 (v4i32 (XXINSERTW v4i32:$A,4550 (SUBREG_TO_REG (i64 1),4551 (XSCVDPUXWS f64:$B), sub_64),4552 8))>;4553def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),4554 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;4555def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),4556 (v4i32 (XXINSERTW v4i32:$A,4557 (SUBREG_TO_REG (i64 1),4558 (XSCVDPSXWS f64:$B), sub_64),4559 4))>;4560def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),4561 (v4i32 (XXINSERTW v4i32:$A,4562 (SUBREG_TO_REG (i64 1),4563 (XSCVDPUXWS f64:$B), sub_64),4564 4))>;4565def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),4566 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;4567def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),4568 (v4i32 (XXINSERTW v4i32:$A,4569 (SUBREG_TO_REG (i64 1),4570 (XSCVDPSXWS f64:$B), sub_64),4571 0))>;4572def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),4573 (v4i32 (XXINSERTW v4i32:$A,4574 (SUBREG_TO_REG (i64 1),4575 (XSCVDPUXWS f64:$B), sub_64),4576 0))>;4577def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),4578 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;4579def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),4580 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;4581def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),4582 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;4583def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),4584 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;4585 4586def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),4587 (v4f32 (XXINSERTW v4f32:$A,4588 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;4589def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),4590 (v4f32 (XXINSERTW v4f32:$A,4591 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;4592def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),4593 (v4f32 (XXINSERTW v4f32:$A,4594 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;4595def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),4596 (v4f32 (XXINSERTW v4f32:$A,4597 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;4598 4599def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)),4600 (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>;4601def : Pat<(PPCst_vec_be v8i16:$rS, ForceXForm:$dst),4602 (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;4603 4604def : Pat<(v16i8 (PPCld_vec_be ForceXForm:$src)),4605 (COPY_TO_REGCLASS (LXVB16X ForceXForm:$src), VRRC)>;4606def : Pat<(PPCst_vec_be v16i8:$rS, ForceXForm:$dst),4607 (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;4608 4609// Scalar stores of i84610def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst),4611 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;4612def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst),4613 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>;4614def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst),4615 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;4616def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst),4617 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>;4618def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst),4619 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;4620def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst),4621 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>;4622def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst),4623 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;4624def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst),4625 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>;4626def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst),4627 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;4628def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst),4629 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>;4630def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst),4631 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;4632def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst),4633 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>;4634def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst),4635 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;4636def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst),4637 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>;4638def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst),4639 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;4640def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst),4641 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>;4642 4643// Scalar stores of i164644def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst),4645 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;4646def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst),4647 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;4648def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst),4649 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;4650def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst),4651 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;4652def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst),4653 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;4654def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst),4655 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;4656def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst),4657 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;4658def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst),4659 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;4660 4661defm : ScalToVecWPermute<4662 v2i64, (i64 (load DSForm:$src)),4663 (XXPERMDIs (DFLOADf64 DSForm:$src), 2),4664 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;4665defm : ScalToVecWPermute<4666 v2i64, (i64 (load XForm:$src)),4667 (XXPERMDIs (XFLOADf64 XForm:$src), 2),4668 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;4669defm : ScalToVecWPermute<4670 v2f64, (f64 (load DSForm:$src)),4671 (XXPERMDIs (DFLOADf64 DSForm:$src), 2),4672 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;4673defm : ScalToVecWPermute<4674 v2f64, (f64 (load XForm:$src)),4675 (XXPERMDIs (XFLOADf64 XForm:$src), 2),4676 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;4677 4678def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),4679 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4680 sub_64), XForm:$src)>;4681def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src),4682 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4683 sub_64), XForm:$src)>;4684def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src),4685 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;4686def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src),4687 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;4688def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src),4689 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),4690 sub_64), DSForm:$src)>;4691def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src),4692 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),4693 DSForm:$src)>;4694def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src),4695 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;4696def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src),4697 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;4698 4699// (Un)Signed DWord vector extract -> QP4700def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),4701 (f128 (XSCVSDQP4702 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;4703def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),4704 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;4705def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),4706 (f128 (XSCVUDQP4707 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;4708def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),4709 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;4710 4711// (Un)Signed Word vector extract -> QP4712foreach Idx = [[0,3],[1,2],[3,0]] in {4713 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),4714 (f128 (XSCVSDQP (EXTRACT_SUBREG4715 (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)),4716 sub_64)))>;4717}4718def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),4719 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;4720 4721foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {4722 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),4723 (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;4724}4725 4726// (Un)Signed HWord vector extract -> QP/DP/SP4727// The Nested foreach lists identifies the vector element and corresponding4728// register byte location.4729foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in {4730 def : Pat<(f128 (sint_to_fp4731 (i32 (sext_inreg4732 (vector_extract v8i16:$src, !head(Idx)), i16)))),4733 (f128 (XSCVSDQP4734 (EXTRACT_SUBREG (VEXTSH2D4735 (VEXTRACTUH !head(!tail(Idx)), $src)),4736 sub_64)))>;4737 def : Pat<(f128 (uint_to_fp4738 (and (i32 (vector_extract v8i16:$src, !head(Idx))),4739 65535))),4740 (f128 (XSCVUDQP (EXTRACT_SUBREG4741 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;4742 def : Pat<(f32 (PPCfcfidus4743 (f64 (PPCmtvsrz4744 (and (i32 (vector_extract v8i16:$src, !head(Idx))),4745 65535))))),4746 (f32 (XSCVUXDSP (EXTRACT_SUBREG4747 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;4748 def : Pat<(f32 (PPCfcfids4749 (f64 (PPCmtvsra4750 (i32 (sext_inreg (vector_extract v8i16:$src,4751 !head(Idx)), i16)))))),4752 (f32 (XSCVSXDSP4753 (EXTRACT_SUBREG4754 (VEXTSH2D (VEXTRACTUH !head(!tail(Idx)), $src)),4755 sub_64)))>;4756 def : Pat<(f64 (PPCfcfidu4757 (f64 (PPCmtvsrz4758 (and (i32 (vector_extract v8i16:$src, !head(Idx))),4759 65535))))),4760 (f64 (XSCVUXDDP (EXTRACT_SUBREG4761 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;4762 def : Pat<(f64 (PPCfcfid4763 (f64 (PPCmtvsra4764 (i32 (sext_inreg4765 (vector_extract v8i16:$src, !head(Idx)), i16)))))),4766 (f64 (XSCVSXDDP4767 (EXTRACT_SUBREG (VEXTSH2D4768 (VEXTRACTUH !head(!tail(Idx)), $src)),4769 sub_64)))>;4770}4771 4772// (Un)Signed Byte vector extract -> QP/DP/SP4773foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7],4774 [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in {4775 def : Pat<(f128 (sint_to_fp4776 (i32 (sext_inreg4777 (vector_extract v16i8:$src, !head(Idx)), i8)))),4778 (f128 (XSCVSDQP4779 (EXTRACT_SUBREG4780 (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)),4781 sub_64)))>;4782 def : Pat<(f128 (uint_to_fp4783 (and (i32 (vector_extract v16i8:$src, !head(Idx))),4784 255))),4785 (f128 (XSCVUDQP4786 (EXTRACT_SUBREG4787 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;4788 4789 def : Pat<(f32 (PPCfcfidus4790 (f64 (PPCmtvsrz4791 (and (i32 (vector_extract v16i8:$src, !head(Idx))),4792 255))))),4793 (f32 (XSCVUXDSP (EXTRACT_SUBREG4794 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;4795 def : Pat<(f32 (PPCfcfids4796 (f64 (PPCmtvsra4797 (i32 (sext_inreg4798 (vector_extract v16i8:$src, !head(Idx)), i8)))))),4799 (f32 (XSCVSXDSP4800 (EXTRACT_SUBREG (VEXTSH2D4801 (VEXTRACTUB !head(!tail(Idx)), $src)),4802 sub_64)))>;4803 def : Pat<(f64 (PPCfcfidu4804 (f64 (PPCmtvsrz4805 (and (i324806 (vector_extract v16i8:$src, !head(Idx))), 255))))),4807 (f64 (XSCVUXDDP (EXTRACT_SUBREG4808 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;4809 def : Pat<(f64 (PPCfcfidu4810 (f64 (PPCmtvsra4811 (i32 (sext_inreg4812 (vector_extract v16i8:$src, !head(Idx)), i8)))))),4813 (f64 (XSCVSXDDP4814 (EXTRACT_SUBREG (VEXTSH2D4815 (VEXTRACTUB !head(!tail(Idx)), $src)),4816 sub_64)))>;4817 4818 def : Pat<(f64 (PPCfcfid4819 (f64 (PPCmtvsra4820 (i32 (sext_inreg4821 (vector_extract v16i8:$src, !head(Idx)), i8)))))),4822 (f64 (XSCVSXDDP4823 (EXTRACT_SUBREG (VEXTSH2D4824 (VEXTRACTUH !head(!tail(Idx)), $src)),4825 sub_64)))>;4826}4827 4828// Unsiged int in vsx register -> QP4829def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),4830 (f128 (XSCVUDQP4831 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>;4832} // HasVSX, HasP9Vector, IsLittleEndian4833 4834// Any Power9 VSX subtarget that supports Power9 Altivec.4835let Predicates = [HasVSX, HasP9Altivec] in {4836// Unsigned absolute-difference.4837def : Pat<(v4i32 (abdu v4i32:$A, v4i32:$B)),4838 (v4i32 (VABSDUW $A, $B))>;4839 4840def : Pat<(v8i16 (abdu v8i16:$A, v8i16:$B)),4841 (v8i16 (VABSDUH $A, $B))>;4842 4843def : Pat<(v16i8 (abdu v16i8:$A, v16i8:$B)),4844 (v16i8 (VABSDUB $A, $B))>;4845 4846// Signed absolute-difference.4847// Power9 VABSD* instructions are designed to support unsigned integer4848// vectors (byte/halfword/word), if we want to make use of them for signed4849// integer vectors, we have to flip their sign bits first. To flip sign bit4850// for byte/halfword integer vector would become inefficient, but for word4851// integer vector, we can leverage XVNEGSP to make it efficiently.4852def : Pat<(v4i32 (abds v4i32:$A, v4i32:$B)),4853 (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>;4854} // HasVSX, HasP9Altivec4855 4856// Big endian Power9 64Bit VSX subtargets with P9 Altivec support.4857let Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in {4858def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),4859 (VEXTUBLX $Idx, $S)>;4860 4861def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),4862 (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>;4863def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),4864 (VEXTUHLX (LI8 0), $S)>;4865def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),4866 (VEXTUHLX (LI8 2), $S)>;4867def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),4868 (VEXTUHLX (LI8 4), $S)>;4869def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),4870 (VEXTUHLX (LI8 6), $S)>;4871def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),4872 (VEXTUHLX (LI8 8), $S)>;4873def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),4874 (VEXTUHLX (LI8 10), $S)>;4875def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),4876 (VEXTUHLX (LI8 12), $S)>;4877def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),4878 (VEXTUHLX (LI8 14), $S)>;4879 4880def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),4881 (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>;4882def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),4883 (VEXTUWLX (LI8 0), $S)>;4884 4885// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX4886def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),4887 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),4888 (i32 VectorExtractions.LE_WORD_2), sub_32)>;4889def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),4890 (VEXTUWLX (LI8 8), $S)>;4891def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),4892 (VEXTUWLX (LI8 12), $S)>;4893 4894def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),4895 (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>;4896def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),4897 (EXTSW (VEXTUWLX (LI8 0), $S))>;4898// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX4899def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),4900 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),4901 (i32 VectorExtractions.LE_WORD_2), sub_32))>;4902def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),4903 (EXTSW (VEXTUWLX (LI8 8), $S))>;4904def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),4905 (EXTSW (VEXTUWLX (LI8 12), $S))>;4906 4907def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),4908 (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>;4909def : Pat<(i32 (vector_extract v16i8:$S, 0)),4910 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>;4911def : Pat<(i32 (vector_extract v16i8:$S, 1)),4912 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>;4913def : Pat<(i32 (vector_extract v16i8:$S, 2)),4914 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>;4915def : Pat<(i32 (vector_extract v16i8:$S, 3)),4916 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>;4917def : Pat<(i32 (vector_extract v16i8:$S, 4)),4918 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>;4919def : Pat<(i32 (vector_extract v16i8:$S, 5)),4920 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>;4921def : Pat<(i32 (vector_extract v16i8:$S, 6)),4922 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>;4923def : Pat<(i32 (vector_extract v16i8:$S, 7)),4924 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>;4925def : Pat<(i32 (vector_extract v16i8:$S, 8)),4926 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>;4927def : Pat<(i32 (vector_extract v16i8:$S, 9)),4928 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>;4929def : Pat<(i32 (vector_extract v16i8:$S, 10)),4930 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>;4931def : Pat<(i32 (vector_extract v16i8:$S, 11)),4932 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>;4933def : Pat<(i32 (vector_extract v16i8:$S, 12)),4934 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>;4935def : Pat<(i32 (vector_extract v16i8:$S, 13)),4936 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>;4937def : Pat<(i32 (vector_extract v16i8:$S, 14)),4938 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>;4939def : Pat<(i32 (vector_extract v16i8:$S, 15)),4940 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>;4941 4942def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),4943 (i32 (EXTRACT_SUBREG (VEXTUHLX4944 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;4945def : Pat<(i32 (vector_extract v8i16:$S, 0)),4946 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>;4947def : Pat<(i32 (vector_extract v8i16:$S, 1)),4948 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>;4949def : Pat<(i32 (vector_extract v8i16:$S, 2)),4950 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>;4951def : Pat<(i32 (vector_extract v8i16:$S, 3)),4952 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>;4953def : Pat<(i32 (vector_extract v8i16:$S, 4)),4954 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>;4955def : Pat<(i32 (vector_extract v8i16:$S, 5)),4956 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>;4957def : Pat<(i32 (vector_extract v8i16:$S, 6)),4958 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>;4959def : Pat<(i32 (vector_extract v8i16:$S, 6)),4960 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>;4961 4962def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),4963 (i32 (EXTRACT_SUBREG (VEXTUWLX4964 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;4965def : Pat<(i32 (vector_extract v4i32:$S, 0)),4966 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>;4967// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX4968def : Pat<(i32 (vector_extract v4i32:$S, 1)),4969 (i32 VectorExtractions.LE_WORD_2)>;4970def : Pat<(i32 (vector_extract v4i32:$S, 2)),4971 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>;4972def : Pat<(i32 (vector_extract v4i32:$S, 3)),4973 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>;4974 4975// P9 Altivec instructions that can be used to build vectors.4976// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete4977// with complexities of existing build vector patterns in this file.4978def : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)),4979 (v2i64 (VEXTSW2D $A))>;4980def : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)),4981 (v2i64 (VEXTSH2D $A))>;4982def : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1,4983 HWordToWord.BE_A2, HWordToWord.BE_A3)),4984 (v4i32 (VEXTSH2W $A))>;4985def : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1,4986 ByteToWord.BE_A2, ByteToWord.BE_A3)),4987 (v4i32 (VEXTSB2W $A))>;4988def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)),4989 (v2i64 (VEXTSB2D $A))>;4990} // HasVSX, HasP9Altivec, IsBigEndian, IsPPC644991 4992// Little endian Power9 VSX subtargets with P9 Altivec support.4993let Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in {4994def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),4995 (VEXTUBRX $Idx, $S)>;4996 4997def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),4998 (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>;4999def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),5000 (VEXTUHRX (LI8 0), $S)>;5001def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),5002 (VEXTUHRX (LI8 2), $S)>;5003def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),5004 (VEXTUHRX (LI8 4), $S)>;5005def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),5006 (VEXTUHRX (LI8 6), $S)>;5007def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),5008 (VEXTUHRX (LI8 8), $S)>;5009def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),5010 (VEXTUHRX (LI8 10), $S)>;5011def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),5012 (VEXTUHRX (LI8 12), $S)>;5013def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),5014 (VEXTUHRX (LI8 14), $S)>;5015 5016def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),5017 (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>;5018def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),5019 (VEXTUWRX (LI8 0), $S)>;5020def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),5021 (VEXTUWRX (LI8 4), $S)>;5022// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX5023def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),5024 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),5025 (i32 VectorExtractions.LE_WORD_2), sub_32)>;5026def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),5027 (VEXTUWRX (LI8 12), $S)>;5028 5029def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),5030 (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>;5031def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),5032 (EXTSW (VEXTUWRX (LI8 0), $S))>;5033def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),5034 (EXTSW (VEXTUWRX (LI8 4), $S))>;5035// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX5036def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),5037 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),5038 (i32 VectorExtractions.LE_WORD_2), sub_32))>;5039def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),5040 (EXTSW (VEXTUWRX (LI8 12), $S))>;5041 5042def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),5043 (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>;5044def : Pat<(i32 (vector_extract v16i8:$S, 0)),5045 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>;5046def : Pat<(i32 (vector_extract v16i8:$S, 1)),5047 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>;5048def : Pat<(i32 (vector_extract v16i8:$S, 2)),5049 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>;5050def : Pat<(i32 (vector_extract v16i8:$S, 3)),5051 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>;5052def : Pat<(i32 (vector_extract v16i8:$S, 4)),5053 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>;5054def : Pat<(i32 (vector_extract v16i8:$S, 5)),5055 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>;5056def : Pat<(i32 (vector_extract v16i8:$S, 6)),5057 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>;5058def : Pat<(i32 (vector_extract v16i8:$S, 7)),5059 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>;5060def : Pat<(i32 (vector_extract v16i8:$S, 8)),5061 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>;5062def : Pat<(i32 (vector_extract v16i8:$S, 9)),5063 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>;5064def : Pat<(i32 (vector_extract v16i8:$S, 10)),5065 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>;5066def : Pat<(i32 (vector_extract v16i8:$S, 11)),5067 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>;5068def : Pat<(i32 (vector_extract v16i8:$S, 12)),5069 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>;5070def : Pat<(i32 (vector_extract v16i8:$S, 13)),5071 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>;5072def : Pat<(i32 (vector_extract v16i8:$S, 14)),5073 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>;5074def : Pat<(i32 (vector_extract v16i8:$S, 15)),5075 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>;5076 5077def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),5078 (i32 (EXTRACT_SUBREG (VEXTUHRX5079 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;5080def : Pat<(i32 (vector_extract v8i16:$S, 0)),5081 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>;5082def : Pat<(i32 (vector_extract v8i16:$S, 1)),5083 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>;5084def : Pat<(i32 (vector_extract v8i16:$S, 2)),5085 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>;5086def : Pat<(i32 (vector_extract v8i16:$S, 3)),5087 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>;5088def : Pat<(i32 (vector_extract v8i16:$S, 4)),5089 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>;5090def : Pat<(i32 (vector_extract v8i16:$S, 5)),5091 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>;5092def : Pat<(i32 (vector_extract v8i16:$S, 6)),5093 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>;5094def : Pat<(i32 (vector_extract v8i16:$S, 6)),5095 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>;5096 5097def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),5098 (i32 (EXTRACT_SUBREG (VEXTUWRX5099 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;5100def : Pat<(i32 (vector_extract v4i32:$S, 0)),5101 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>;5102def : Pat<(i32 (vector_extract v4i32:$S, 1)),5103 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>;5104// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX5105def : Pat<(i32 (vector_extract v4i32:$S, 2)),5106 (i32 VectorExtractions.LE_WORD_2)>;5107def : Pat<(i32 (vector_extract v4i32:$S, 3)),5108 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>;5109 5110// P9 Altivec instructions that can be used to build vectors.5111// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete5112// with complexities of existing build vector patterns in this file.5113def : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)),5114 (v2i64 (VEXTSW2D $A))>;5115def : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)),5116 (v2i64 (VEXTSH2D $A))>;5117def : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1,5118 HWordToWord.LE_A2, HWordToWord.LE_A3)),5119 (v4i32 (VEXTSH2W $A))>;5120def : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1,5121 ByteToWord.LE_A2, ByteToWord.LE_A3)),5122 (v4i32 (VEXTSB2W $A))>;5123def : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)),5124 (v2i64 (VEXTSB2D $A))>;5125} // HasVSX, HasP9Altivec, IsLittleEndian5126 5127// Big endian 64Bit VSX subtarget that supports additional direct moves from5128// ISA3.0.5129let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] in {5130def : Pat<(i64 (extractelt v2i64:$A, 1)),5131 (i64 (MFVSRLD $A))>;5132// Better way to build integer vectors if we have MTVSRDD. Big endian.5133def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),5134 (v2i64 (MTVSRDD $rB, $rA))>;5135def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),5136 (MTVSRDD5137 (RLDIMI AnyExts.B, AnyExts.A, 32, 0),5138 (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>;5139 5140def : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)),5141 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;5142} // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC645143 5144// Little endian VSX subtarget that supports direct moves from ISA3.0.5145let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in {5146def : Pat<(i64 (extractelt v2i64:$A, 0)),5147 (i64 (MFVSRLD $A))>;5148// Better way to build integer vectors if we have MTVSRDD. Little endian.5149def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),5150 (v2i64 (MTVSRDD $rB, $rA))>;5151def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),5152 (MTVSRDD5153 (RLDIMI AnyExts.C, AnyExts.D, 32, 0),5154 (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>;5155 5156def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)),5157 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;5158} // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian5159} // AddedComplexity = 4005160 5161//---------------------------- Instruction aliases ---------------------------//5162def : InstAlias<"xvmovdp $XT, $XB",5163 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;5164def : InstAlias<"xvmovsp $XT, $XB",5165 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;5166 5167// Certain versions of the AIX assembler may missassemble these mnemonics.5168let Predicates = [ModernAs] in {5169 def : InstAlias<"xxspltd $XT, $XB, 0",5170 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;5171 def : InstAlias<"xxspltd $XT, $XB, 1",5172 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;5173 def : InstAlias<"xxspltd $XT, $XB, 0",5174 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;5175 def : InstAlias<"xxspltd $XT, $XB, 1",5176 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;5177}5178 5179def : InstAlias<"xxmrghd $XT, $XA, $XB",5180 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;5181def : InstAlias<"xxmrgld $XT, $XA, $XB",5182 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;5183def : InstAlias<"xxswapd $XT, $XB",5184 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;5185def : InstAlias<"xxswapd $XT, $XB",5186 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;5187def : InstAlias<"mfvrd $rA, $XT",5188 (MFVRD g8rc:$rA, vrrc:$XT), 0>;5189def : InstAlias<"mffprd $rA, $src",5190 (MFVSRD g8rc:$rA, f8rc:$src)>;5191def : InstAlias<"mtvrd $XT, $rA",5192 (MTVRD vrrc:$XT, g8rc:$rA), 0>;5193def : InstAlias<"mtfprd $dst, $rA",5194 (MTVSRD f8rc:$dst, g8rc:$rA)>;5195def : InstAlias<"mfvrwz $rA, $XT",5196 (MFVRWZ gprc:$rA, vrrc:$XT), 0>;5197def : InstAlias<"mffprwz $rA, $src",5198 (MFVSRWZ gprc:$rA, f8rc:$src)>;5199def : InstAlias<"mtvrwa $XT, $rA",5200 (MTVRWA vrrc:$XT, gprc:$rA), 0>;5201def : InstAlias<"mtfprwa $dst, $rA",5202 (MTVSRWA f8rc:$dst, gprc:$rA)>;5203def : InstAlias<"mtvrwz $XT, $rA",5204 (MTVRWZ vrrc:$XT, gprc:$rA), 0>;5205def : InstAlias<"mtfprwz $dst, $rA",5206 (MTVSRWZ f8rc:$dst, gprc:$rA)>;5207