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1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12let Namespace = "PPC" in {13def sub_lt : SubRegIndex<1>;14def sub_gt : SubRegIndex<1, 1>;15def sub_eq : SubRegIndex<1, 2>;16def sub_un : SubRegIndex<1, 3>;17def sub_32 : SubRegIndex<32>;18def sub_32_hi_phony : SubRegIndex<32,32>;19def sub_64 : SubRegIndex<64>;20def sub_64_hi_phony : SubRegIndex<64,64>;21def sub_vsx0 : SubRegIndex<128>;22def sub_vsx1 : SubRegIndex<128, 128>;23def sub_gp8_x0 : SubRegIndex<64>;24def sub_gp8_x1 : SubRegIndex<64, 64>;25def sub_fp0 : SubRegIndex<64>;26def sub_fp1 : SubRegIndex<64, 64>;27}28 29 30class PPCReg<string n> : Register<n> {31 let Namespace = "PPC";32}33 34// We identify all our registers with a 5-bit ID, for consistency's sake.35 36// GPR - One of the 32 32-bit general-purpose registers37class GPR<bits<5> num, string n> : PPCReg<n> {38 let HWEncoding{4-0} = num;39}40 41// GP8 - One of the 32 64-bit general-purpose registers42class GP8<GPR SubReg, string n> : PPCReg<n> {43 let HWEncoding = SubReg.HWEncoding;44 let SubRegs = [SubReg];45 let SubRegIndices = [sub_32];46}47 48class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> {49 let HWEncoding{4-0} = Enc;50 let SubRegs = subregs;51 let SubRegIndices = [sub_32, sub_32_hi_phony];52 let CoveredBySubRegs = 1;53}54// SPR - One of the 32-bit special-purpose registers55class SPR<bits<10> num, string n> : PPCReg<n> {56 let HWEncoding{9-0} = num;57}58 59// FPR - One of the 32 64-bit floating-point registers60class FPR<bits<5> num, string n> : PPCReg<n> {61 let HWEncoding{4-0} = num;62}63 64// FPPair - A pair of 64-bit floating-point registers.65class FPPair<string n, bits<5> EvenIndex> : PPCReg<n> {66 assert !eq(EvenIndex{0}, 0), "Index should be even.";67 let HWEncoding{4-0} = EvenIndex;68 let SubRegs = [!cast<FPR>("F"#EvenIndex), !cast<FPR>("F"#!add(EvenIndex, 1))];69 let DwarfNumbers = [-1, -1];70 let SubRegIndices = [sub_fp0, sub_fp1];71}72 73// VF - One of the 32 64-bit floating-point subregisters of the vector74// registers (used by VSX).75class VF<bits<5> num, string n> : PPCReg<n> {76 let HWEncoding{4-0} = num;77 let HWEncoding{5} = 1;78}79 80// VR - One of the 32 128-bit vector registers81class VR<VF SubReg, VF SubRegH, string n> : PPCReg<n> {82 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};83 let HWEncoding{5} = 0;84 let SubRegs = [SubReg, SubRegH];85 let SubRegIndices = [sub_64, sub_64_hi_phony];86}87 88// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar89// floating-point registers.90class VSRL<FPR SubReg, FPR SubRegH, string n> : PPCReg<n> {91 let HWEncoding = SubReg.HWEncoding;92 let SubRegs = [SubReg, SubRegH];93 let SubRegIndices = [sub_64, sub_64_hi_phony];94}95 96// VSXReg - One of the VSX registers in the range vs32-vs63 with numbering97// and encoding to match.98class VSXReg<bits<6> num, string n> : PPCReg<n> {99 let HWEncoding{5-0} = num;100}101 102// CR - One of the 8 4-bit condition registers103class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {104 let HWEncoding{2-0} = num;105 let SubRegs = subregs;106}107 108// CRBIT - One of the 32 1-bit condition register fields109class CRBIT<bits<5> num, string n> : PPCReg<n> {110 let HWEncoding{4-0} = num;111}112 113// VSR Pairs - One of the 32 paired even-odd consecutive VSRs.114class VSRPair<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {115 let HWEncoding{4-0} = num;116 let SubRegs = subregs;117}118 119// GP8Pair - Consecutive even-odd paired GP8.120class GP8Pair<string n, bits<5> EvenIndex> : PPCReg<n> {121 assert !eq(EvenIndex{0}, 0), "Index should be even.";122 let HWEncoding{4-0} = EvenIndex;123 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))];124 let DwarfNumbers = [-1, -1];125 let SubRegIndices = [sub_gp8_x0, sub_gp8_x1];126}127 128// General-purpose registers129foreach Index = 0-31 in {130 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;131}132 133let isArtificial = 1 in {134 foreach Index = 0-31 in {135 def H#Index : GPR<-1,"">;136 }137}138 139// 64-bit General-purpose registers140foreach Index = 0-31 in {141 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,142 DwarfRegNum<[Index, -2]>;143}144 145// SPE registers146foreach Index = 0-31 in {147 def S#Index : SPE<"r"#Index, Index, [!cast<GPR>("R"#Index), !cast<GPR>("H"#Index)]>,148 DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;149 150}151 152 153// Floating-point registers154foreach Index = 0-31 in {155 def F#Index : FPR<Index, "f"#Index>,156 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;157}158 159// The FH and VFH registers have been marked as Artifical because there are no160// instructions on PowerPC that use those register classes. They only exist161// in order to ensure that the super registers (V and VSL) are covered by their162// subregisters and have correct subregister lane masks.163let isArtificial = 1 in {164 foreach Index = 0-31 in {165 def FH#Index : FPR<-1, "">;166 def VFH#Index : VF<-1, "">;167 }168}169 170let isAllocatable = 0, CopyCost = -1 in {171 def VFHRC : RegisterClass<"PPC", [f64], 64, (sequence "VFH%u", 0, 31)>;172 def FHRC : RegisterClass<"PPC", [f64], 64, (sequence "FH%u", 0, 31)>;173}174 175// Floating-point pair registers176foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {177 def Fpair#Index : FPPair<"fp"#Index, Index>;178}179 180// 64-bit Floating-point subregisters of Altivec registers181// Note: the register names are v0-v31 or vs32-vs63 depending on the use.182// Custom C++ code is used to produce the correct name and encoding.183foreach Index = 0-31 in {184 def VF#Index : VF<Index, "v" #Index>,185 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;186}187 188let CoveredBySubRegs = 1 in {189// Vector registers190foreach Index = 0-31 in {191 def V#Index : VR<!cast<VF>("VF"#Index), !cast<VF>("VFH"#Index), "v"#Index>,192 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;193}194 195// VSX registers196foreach Index = 0-31 in {197 def VSL#Index : VSRL<!cast<FPR>("F"#Index), !cast<FPR>("FH"#Index), "vs"#Index>,198 DwarfRegAlias<!cast<FPR>("F"#Index)>;199}200}201 202// Dummy VSX registers, this defines string: "vs32"-"vs63", and is only used for203// asm printing.204foreach Index = 32-63 in {205 def VSX#Index : VSXReg<Index, "vs"#Index>;206}207 208let SubRegIndices = [sub_vsx0, sub_vsx1] in {209 // VSR pairs 0 - 15 (corresponding to VSRs 0 - 30 paired with 1 - 31).210 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {211 def VSRp#!srl(Index, 1) : VSRPair<!srl(Index, 1), "vsp"#Index,212 [!cast<VSRL>("VSL"#Index), !cast<VSRL>("VSL"#!add(Index, 1))]>,213 DwarfRegNum<[-1, -1]>;214 }215 216 // VSR pairs 16 - 31 (corresponding to VSRs 32 - 62 paired with 33 - 63).217 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {218 def VSRp#!add(!srl(Index, 1), 16) :219 VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32),220 [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>,221 DwarfRegAlias<!cast<VR>("V"#Index)>;222 }223}224 225// 16 paired even-odd consecutive GP8s.226foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {227 def G8p#!srl(Index, 1) : GP8Pair<"r"#Index, Index>;228}229 230// The representation of r0 when treated as the constant 0.231let isConstant = true in {232def ZERO : GPR<0, "0">, DwarfRegAlias<R0>;233def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>;234} // isConstant = true235 236// Representations of the frame pointer used by ISD::FRAMEADDR.237def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;238def FP8 : GP8<FP, "**FRAME POINTER**">;239 240// Representations of the base pointer used by setjmp.241def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;242def BP8 : GP8<BP, "**BASE POINTER**">;243 244// Condition register bits245def CR0LT : CRBIT< 0, "0">;246def CR0GT : CRBIT< 1, "1">;247def CR0EQ : CRBIT< 2, "2">;248def CR0UN : CRBIT< 3, "3">;249def CR1LT : CRBIT< 4, "4">;250def CR1GT : CRBIT< 5, "5">;251def CR1EQ : CRBIT< 6, "6">;252def CR1UN : CRBIT< 7, "7">;253def CR2LT : CRBIT< 8, "8">;254def CR2GT : CRBIT< 9, "9">;255def CR2EQ : CRBIT<10, "10">;256def CR2UN : CRBIT<11, "11">;257def CR3LT : CRBIT<12, "12">;258def CR3GT : CRBIT<13, "13">;259def CR3EQ : CRBIT<14, "14">;260def CR3UN : CRBIT<15, "15">;261def CR4LT : CRBIT<16, "16">;262def CR4GT : CRBIT<17, "17">;263def CR4EQ : CRBIT<18, "18">;264def CR4UN : CRBIT<19, "19">;265def CR5LT : CRBIT<20, "20">;266def CR5GT : CRBIT<21, "21">;267def CR5EQ : CRBIT<22, "22">;268def CR5UN : CRBIT<23, "23">;269def CR6LT : CRBIT<24, "24">;270def CR6GT : CRBIT<25, "25">;271def CR6EQ : CRBIT<26, "26">;272def CR6UN : CRBIT<27, "27">;273def CR7LT : CRBIT<28, "28">;274def CR7GT : CRBIT<29, "29">;275def CR7EQ : CRBIT<30, "30">;276def CR7UN : CRBIT<31, "31">;277 278// Condition registers279let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {280def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;281def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;282def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;283def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;284def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;285def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;286def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;287def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;288}289 290// Link register291def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;292def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]> {293 let Aliases = [LR];294}295 296// Count register297def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;298def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]> {299 let Aliases = [CTR];300}301 302// VRsave register303def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;304 305// SPE extra registers306def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;307 308def XER: SPR<1, "xer">, DwarfRegNum<[76]>;309 310// Carry bit. In the architecture this is really bit 0 of the XER register311// (which really is SPR register 1); this is the only bit interesting to a312// compiler.313def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {314 let Aliases = [XER];315}316 317// FP rounding mode: bits 30 and 31 of the FP status and control register318// This is not allocated as a normal register; it appears only in319// Uses and Defs. The ABI says it needs to be preserved by a function,320// but this is not achieved by saving and restoring it as with321// most registers, it has to be done in code; to make this work all the322// return and call instructions are described as Uses of RM, so instructions323// that do nothing but change RM will not get deleted.324def RM: PPCReg<"**ROUNDING MODE**">;325 326let isAllocatable = 0 in327def GPRC32 : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "H%u", 2, 12),328 (sequence "H%u", 30, 13),329 H31, H0, H1)>;330 331/// Register classes332// Allocate volatiles first333// then nonvolatiles in reverse order since stmw/lmw save from rN to r31334def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),335 (sequence "R%u", 30, 13),336 R31, R0, R1, FP, BP)> {337 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so338 // put it at the end of the list.339 // On AIX, CSRs are allocated starting from R31 according to:340 // https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf.341 // This also helps setting the correct `NumOfGPRsSaved' in traceback table.342 let AltOrders = [(add (sub GPRC, R2), R2),343 (add (sequence "R%u", 2, 12),344 (sequence "R%u", 31, 13), R0, R1, FP, BP)];345 let AltOrderSelect = [{346 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();347 }];348}349 350def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),351 (sequence "X%u", 30, 14),352 X31, X13, X0, X1, FP8, BP8)> {353 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so354 // put it at the end of the list.355 let AltOrders = [(add (sub G8RC, X2), X2),356 (add (sequence "X%u", 2, 12),357 (sequence "X%u", 31, 13), X0, X1, FP8, BP8)];358 let AltOrderSelect = [{359 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();360 }];361}362 363// For some instructions r0 is special (representing the value 0 instead of364// the value in the r0 register), and we use these register subclasses to365// prevent r0 from being allocated for use by those instructions.366def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {367 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so368 // put it at the end of the list.369 let AltOrders = [(add (sub GPRC_NOR0, R2), R2),370 (add (sequence "R%u", 2, 12),371 (sequence "R%u", 31, 13), R1, FP, BP, ZERO)];372 let AltOrderSelect = [{373 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();374 }];375}376 377def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {378 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so379 // put it at the end of the list.380 let AltOrders = [(add (sub G8RC_NOX0, X2), X2),381 (add (sequence "X%u", 2, 12),382 (sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)];383 let AltOrderSelect = [{384 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();385 }];386}387 388def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),389 (sequence "S%u", 30, 13),390 S31, S0, S1)>;391 392// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4393// ABI the size of the Floating-point register save area is determined by the394// allocated non-volatile register with the lowest register number, as FP395// register N is spilled to offset 8 * (32 - N) below the back chain word of the396// previous stack frame. By allocating non-volatiles in reverse order we make397// sure that the Floating-point register save area is always as small as398// possible because there aren't any unused spill slots.399def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),400 (sequence "F%u", 31, 14))>;401def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;402 403// Floating point pair registers.404// Note that the type used for this register class is ppcf128. This is not405// completely correct. However, since we are not pattern matching any406// instructions for these registers and we are not register allocating or407// scheduling any of these instructions it should be safe to do this.408// The reason we didn't use the correct type (Decimal Floating Point) is that409// at the time of this implementation the correct type was not available.410def FpRC :411 RegisterClass<"PPC", [ppcf128], 128,412 (add Fpair0, Fpair2, Fpair4, Fpair6, Fpair8, Fpair10, Fpair12,413 Fpair14, Fpair16, Fpair18, Fpair20, Fpair22, Fpair24,414 Fpair26, Fpair28, Fpair30)> {415 let Size = 128;416}417 418def VRRC : RegisterClass<"PPC",419 [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],420 128,421 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,422 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,423 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;424 425// VSX register classes (the allocation order mirrors that of the corresponding426// subregister classes).427def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,428 (add (sequence "VSL%u", 0, 13),429 (sequence "VSL%u", 31, 14))>;430def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,431 (add VSLRC, VRRC)>;432 433// Register classes for the 64-bit "scalar" VSX subregisters.434def VFRC : RegisterClass<"PPC", [f64], 64,435 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,436 VF8, VF9, VF10, VF11, VF12, VF13, VF14,437 VF15, VF16, VF17, VF18, VF19, VF31, VF30,438 VF29, VF28, VF27, VF26, VF25, VF24, VF23,439 VF22, VF21, VF20)>;440def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;441 442// Allow spilling GPR's into caller-saved VSR's.443def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC,444 (sequence "VF%u", 31, 20),445 (sequence "F%u", 31, 14)))>;446 447// Register class for single precision scalars in VSX registers448def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;449 450def CRBITRC : RegisterClass<"PPC", [i1], 32,451 (add CR2LT, CR2GT, CR2EQ, CR2UN,452 CR3LT, CR3GT, CR3EQ, CR3UN,453 CR4LT, CR4GT, CR4EQ, CR4UN,454 CR5LT, CR5GT, CR5EQ, CR5UN,455 CR6LT, CR6GT, CR6EQ, CR6UN,456 CR7LT, CR7GT, CR7EQ, CR7UN,457 CR1LT, CR1GT, CR1EQ, CR1UN,458 CR0LT, CR0GT, CR0EQ, CR0UN)> {459 let Size = 32;460 let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT,461 CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)];462 let AltOrderSelect = [{463 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&464 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();465 }];466}467 468def CRRC : RegisterClass<"PPC", [i32], 32,469 (add CR0, CR1, CR5, CR6,470 CR7, CR2, CR3, CR4)> {471 let AltOrders = [(sub CRRC, CR2, CR3, CR4)];472 let AltOrderSelect = [{473 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&474 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();475 }];476}477// The CTR registers are not allocatable because they're used by the478// decrement-and-branch instructions, and thus need to stay live across479// multiple basic blocks.480def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {481 let isAllocatable = 0;482}483def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {484 let isAllocatable = 0;485}486 487def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {488 let isAllocatable = 0;489}490def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {491 let isAllocatable = 0;492}493 494def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;495def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {496 let CopyCost = -1;497 let isAllocatable = 0;498}499 500// Make AllocationOrder as similar as G8RC's to avoid potential spilling.501// Similarly, we have an AltOrder for 64-bit ELF ABI which r2 is allocated502// at last.503def G8pRC :504 RegisterClass<"PPC", [i128], 128,505 (add (sequence "G8p%u", 1, 5),506 (sequence "G8p%u", 14, 7),507 G8p15, G8p6, G8p0)> {508 let AltOrders = [(add (sub G8pRC, G8p1), G8p1)];509 let AltOrderSelect = [{510 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();511 }];512 let Size = 128;513}514 515include "PPCRegisterInfoMMA.td"516include "PPCRegisterInfoDMR.td"517 518//===----------------------------------------------------------------------===//519// PowerPC Operand Definitions.520 521// In the default PowerPC assembler syntax, registers are specified simply522// by number, so they cannot be distinguished from immediate values (without523// looking at the opcode). This means that the default operand matching logic524// for the asm parser does not work, and we need to specify custom matchers.525// Since those can only be specified with RegisterOperand classes and not526// directly on the RegisterClass, all instructions patterns used by the asm527// parser need to use a RegisterOperand (instead of a RegisterClass) for528// all their register operands.529// For this purpose, we define one RegisterOperand for each RegisterClass,530// using the same name as the class, just in lower case.531 532def PPCRegGPRCAsmOperand : AsmOperandClass {533 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";534}535def gprc : RegisterOperand<GPRC> {536 let ParserMatchClass = PPCRegGPRCAsmOperand;537}538def PPCRegG8RCAsmOperand : AsmOperandClass {539 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";540}541def g8rc : RegisterOperand<G8RC> {542 let ParserMatchClass = PPCRegG8RCAsmOperand;543}544def PPCRegG8pRCAsmOperand : AsmOperandClass {545 let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber";546}547def g8prc : RegisterOperand<G8pRC> {548 let ParserMatchClass = PPCRegG8pRCAsmOperand;549}550def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {551 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";552}553def gprc_nor0 : RegisterOperand<GPRC_NOR0> {554 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;555}556def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {557 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";558}559def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {560 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;561}562def PPCRegF8RCAsmOperand : AsmOperandClass {563 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";564}565def f8rc : RegisterOperand<F8RC> {566 let ParserMatchClass = PPCRegF8RCAsmOperand;567}568def PPCRegF4RCAsmOperand : AsmOperandClass {569 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";570}571def f4rc : RegisterOperand<F4RC> {572 let ParserMatchClass = PPCRegF4RCAsmOperand;573}574def PPCRegFpRCAsmOperand : AsmOperandClass {575 let Name = "RegFpRC"; let PredicateMethod = "isEvenRegNumber";576}577def fpairrc : RegisterOperand<FpRC> {578 let ParserMatchClass = PPCRegFpRCAsmOperand;579}580def PPCRegVRRCAsmOperand : AsmOperandClass {581 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";582}583def vrrc : RegisterOperand<VRRC> {584 let ParserMatchClass = PPCRegVRRCAsmOperand;585}586def PPCRegVFRCAsmOperand : AsmOperandClass {587 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";588}589def vfrc : RegisterOperand<VFRC> {590 let ParserMatchClass = PPCRegVFRCAsmOperand;591}592def PPCRegCRBITRCAsmOperand : AsmOperandClass {593 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";594}595def crbitrc : RegisterOperand<CRBITRC> {596 let ParserMatchClass = PPCRegCRBITRCAsmOperand;597}598def PPCRegCRRCAsmOperand : AsmOperandClass {599 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";600}601def crrc : RegisterOperand<CRRC> {602 let ParserMatchClass = PPCRegCRRCAsmOperand;603}604def PPCRegSPERCAsmOperand : AsmOperandClass {605 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber";606}607def sperc : RegisterOperand<SPERC> {608 let ParserMatchClass = PPCRegSPERCAsmOperand;609}610def PPCRegSPE4RCAsmOperand : AsmOperandClass {611 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";612}613def spe4rc : RegisterOperand<GPRC> {614 let ParserMatchClass = PPCRegSPE4RCAsmOperand;615}616 617def PPCU1ImmAsmOperand : AsmOperandClass {618 let Name = "U1Imm";619 let PredicateMethod = "isUImm<1>";620 let RenderMethod = "addImmOperands";621}622def u1imm : Operand<i32> {623 let PrintMethod = "printU1ImmOperand";624 let ParserMatchClass = PPCU1ImmAsmOperand;625 let DecoderMethod = "decodeUImmOperand<1>";626 let OperandType = "OPERAND_IMMEDIATE";627}628 629def PPCU2ImmAsmOperand : AsmOperandClass {630 let Name = "U2Imm";631 let PredicateMethod = "isUImm<2>";632 let RenderMethod = "addImmOperands";633}634def u2imm : Operand<i32> {635 let PrintMethod = "printU2ImmOperand";636 let ParserMatchClass = PPCU2ImmAsmOperand;637 let DecoderMethod = "decodeUImmOperand<2>";638 let OperandType = "OPERAND_IMMEDIATE";639}640 641def PPCATBitsAsHintAsmOperand : AsmOperandClass {642 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";643 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.644}645def atimm : Operand<i32> {646 let PrintMethod = "printATBitsAsHint";647 let ParserMatchClass = PPCATBitsAsHintAsmOperand;648 let OperandType = "OPERAND_IMMEDIATE";649}650 651def PPCU3ImmAsmOperand : AsmOperandClass {652 let Name = "U3Imm";653 let PredicateMethod = "isUImm<3>";654 let RenderMethod = "addImmOperands";655}656def u3imm : Operand<i32> {657 let PrintMethod = "printU3ImmOperand";658 let ParserMatchClass = PPCU3ImmAsmOperand;659 let DecoderMethod = "decodeUImmOperand<3>";660 let OperandType = "OPERAND_IMMEDIATE";661}662 663def PPCU4ImmAsmOperand : AsmOperandClass {664 let Name = "U4Imm";665 let PredicateMethod = "isUImm<4>";666 let RenderMethod = "addImmOperands";667}668def u4imm : Operand<i32> {669 let PrintMethod = "printU4ImmOperand";670 let ParserMatchClass = PPCU4ImmAsmOperand;671 let DecoderMethod = "decodeUImmOperand<4>";672 let OperandType = "OPERAND_IMMEDIATE";673}674def PPCS5ImmAsmOperand : AsmOperandClass {675 let Name = "S5Imm";676 let PredicateMethod = "isSImm<5>";677 let RenderMethod = "addImmOperands";678}679def s5imm : Operand<i32> {680 let PrintMethod = "printS5ImmOperand";681 let ParserMatchClass = PPCS5ImmAsmOperand;682 let DecoderMethod = "decodeSImmOperand<5>";683 let OperandType = "OPERAND_IMMEDIATE";684}685def PPCU5ImmAsmOperand : AsmOperandClass {686 let Name = "U5Imm";687 let PredicateMethod = "isUImm<5>";688 let RenderMethod = "addImmOperands";689}690def u5imm : Operand<i32> {691 let PrintMethod = "printU5ImmOperand";692 let ParserMatchClass = PPCU5ImmAsmOperand;693 let DecoderMethod = "decodeUImmOperand<5>";694 let OperandType = "OPERAND_IMMEDIATE";695}696def PPCU6ImmAsmOperand : AsmOperandClass {697 let Name = "U6Imm";698 let PredicateMethod = "isUImm<6>";699 let RenderMethod = "addImmOperands";700}701def u6imm : Operand<i32> {702 let PrintMethod = "printU6ImmOperand";703 let ParserMatchClass = PPCU6ImmAsmOperand;704 let DecoderMethod = "decodeUImmOperand<6>";705 let OperandType = "OPERAND_IMMEDIATE";706}707def PPCU7ImmAsmOperand : AsmOperandClass {708 let Name = "U7Imm";709 let PredicateMethod = "isUImm<7>";710 let RenderMethod = "addImmOperands";711}712def u7imm : Operand<i32> {713 let PrintMethod = "printU7ImmOperand";714 let ParserMatchClass = PPCU7ImmAsmOperand;715 let DecoderMethod = "decodeUImmOperand<7>";716 let OperandType = "OPERAND_IMMEDIATE";717}718def PPCU8ImmAsmOperand : AsmOperandClass {719 let Name = "U8Imm";720 let PredicateMethod = "isUImm<8>";721 let RenderMethod = "addImmOperands";722}723def u8imm : Operand<i32> {724 let PrintMethod = "printU8ImmOperand";725 let ParserMatchClass = PPCU8ImmAsmOperand;726 let DecoderMethod = "decodeUImmOperand<8>";727 let OperandType = "OPERAND_IMMEDIATE";728}729def PPCU10ImmAsmOperand : AsmOperandClass {730 let Name = "U10Imm";731 let PredicateMethod = "isUImm<10>";732 let RenderMethod = "addImmOperands";733}734def u10imm : Operand<i32> {735 let PrintMethod = "printU10ImmOperand";736 let ParserMatchClass = PPCU10ImmAsmOperand;737 let DecoderMethod = "decodeUImmOperand<10>";738 let OperandType = "OPERAND_IMMEDIATE";739}740def PPCU12ImmAsmOperand : AsmOperandClass {741 let Name = "U12Imm";742 let PredicateMethod = "isUImm<12>";743 let RenderMethod = "addImmOperands";744}745def u12imm : Operand<i32> {746 let PrintMethod = "printU12ImmOperand";747 let ParserMatchClass = PPCU12ImmAsmOperand;748 let DecoderMethod = "decodeUImmOperand<12>";749 let OperandType = "OPERAND_IMMEDIATE";750}751def PPCS16ImmAsmOperand : AsmOperandClass {752 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";753 let RenderMethod = "addS16ImmOperands";754}755def s16imm : Operand<i32> {756 let PrintMethod = "printS16ImmOperand";757 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";758 let ParserMatchClass = PPCS16ImmAsmOperand;759 let DecoderMethod = "decodeSImmOperand<16>";760 let OperandType = "OPERAND_IMMEDIATE";761}762def s16imm64 : Operand<i64> {763 let PrintMethod = "printS16ImmOperand";764 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";765 let ParserMatchClass = PPCS16ImmAsmOperand;766 let DecoderMethod = "decodeSImmOperand<16>";767 let OperandType = "OPERAND_IMMEDIATE";768}769def PPCU16ImmAsmOperand : AsmOperandClass {770 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";771 let RenderMethod = "addU16ImmOperands";772}773def u16imm : Operand<i32> {774 let PrintMethod = "printU16ImmOperand";775 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";776 let ParserMatchClass = PPCU16ImmAsmOperand;777 let DecoderMethod = "decodeUImmOperand<16>";778 let OperandType = "OPERAND_IMMEDIATE";779}780def u16imm64 : Operand<i64> {781 let PrintMethod = "printU16ImmOperand";782 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";783 let ParserMatchClass = PPCU16ImmAsmOperand;784 let DecoderMethod = "decodeUImmOperand<16>";785 let OperandType = "OPERAND_IMMEDIATE";786}787def PPCS17ImmAsmOperand : AsmOperandClass {788 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";789 let RenderMethod = "addS16ImmOperands";790}791def s17imm : Operand<i32> {792 // This operand type is used for addis/lis to allow the assembler parser793 // to accept immediates in the range -65536..65535 for compatibility with794 // the GNU assembler. The operand is treated as 16-bit otherwise.795 let PrintMethod = "printS16ImmOperand";796 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";797 let ParserMatchClass = PPCS17ImmAsmOperand;798 let DecoderMethod = "decodeSImmOperand<16>";799 let OperandType = "OPERAND_IMMEDIATE";800}801def s17imm64 : Operand<i64> {802 // This operand type is used for addis/lis to allow the assembler parser803 // to accept immediates in the range -65536..65535 for compatibility with804 // the GNU assembler. The operand is treated as 16-bit otherwise.805 let PrintMethod = "printS16ImmOperand";806 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";807 let ParserMatchClass = PPCS17ImmAsmOperand;808 let DecoderMethod = "decodeSImmOperand<16>";809 let OperandType = "OPERAND_IMMEDIATE";810}811def PPCS32ImmAsmOperand : AsmOperandClass {812 let Name = "S32Imm";813 let PredicateMethod = "isS32Imm";814 let RenderMethod = "addImmOperands";815}816def s32imm : Operand<i64> {817 let PrintMethod = "printS32ImmOperand";818 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>";819 let ParserMatchClass = PPCS32ImmAsmOperand;820 let DecoderMethod = "decodeSImmOperand<32>";821 let OperandType = "OPERAND_IMMEDIATE";822}823def s32imm_pcrel : Operand<i64> {824 let PrintMethod = "printS32ImmOperand";825 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>";826 let ParserMatchClass = PPCS32ImmAsmOperand;827 let DecoderMethod = "decodeSImmOperand<32>";828 let OperandType = "OPERAND_IMMEDIATE";829}830def PPCS34ImmAsmOperand : AsmOperandClass {831 let Name = "S34Imm";832 let PredicateMethod = "isS34Imm";833 let RenderMethod = "addImmOperands";834}835def s34imm : Operand<i64> {836 let PrintMethod = "printS34ImmOperand";837 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm34>";838 let ParserMatchClass = PPCS34ImmAsmOperand;839 let DecoderMethod = "decodeSImmOperand<34>";840 let OperandType = "OPERAND_IMMEDIATE";841}842def s34imm_pcrel : Operand<i64> {843 let PrintMethod = "printS34ImmOperand";844 let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel34>";845 let ParserMatchClass = PPCS34ImmAsmOperand;846 let DecoderMethod = "decodeSImmOperand<34>";847 let OperandType = "OPERAND_IMMEDIATE";848}849def PPCImmZeroAsmOperand : AsmOperandClass {850 let Name = "ImmZero";851 let PredicateMethod = "isImmZero";852 let RenderMethod = "addImmOperands";853}854def immZero : Operand<i32> {855 let PrintMethod = "printImmZeroOperand";856 let ParserMatchClass = PPCImmZeroAsmOperand;857 let DecoderMethod = "decodeImmZeroOperand";858 let OperandType = "OPERAND_IMMEDIATE";859}860 861def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;862def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;863 864def PPCDirectBrAsmOperand : AsmOperandClass {865 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";866 let RenderMethod = "addBranchTargetOperands";867}868def directbrtarget : Operand<OtherVT> {869 let PrintMethod = "printBranchOperand";870 let EncoderMethod = "getDirectBrEncoding";871 let DecoderMethod = "decodeDirectBrTarget";872 let ParserMatchClass = PPCDirectBrAsmOperand;873 let OperandType = "OPERAND_PCREL";874}875def absdirectbrtarget : Operand<OtherVT> {876 let PrintMethod = "printAbsBranchOperand";877 let EncoderMethod = "getAbsDirectBrEncoding";878 let DecoderMethod = "decodeDirectBrTarget";879 let ParserMatchClass = PPCDirectBrAsmOperand;880}881def PPCCondBrAsmOperand : AsmOperandClass {882 let Name = "CondBr"; let PredicateMethod = "isCondBr";883 let RenderMethod = "addBranchTargetOperands";884}885def condbrtarget : Operand<OtherVT> {886 let PrintMethod = "printBranchOperand";887 let EncoderMethod = "getCondBrEncoding";888 let DecoderMethod = "decodeCondBrTarget";889 let ParserMatchClass = PPCCondBrAsmOperand;890 let OperandType = "OPERAND_PCREL";891}892def abscondbrtarget : Operand<OtherVT> {893 let PrintMethod = "printAbsBranchOperand";894 let EncoderMethod = "getAbsCondBrEncoding";895 let DecoderMethod = "decodeCondBrTarget";896 let ParserMatchClass = PPCCondBrAsmOperand;897}898def calltarget : Operand<iPTR> {899 let PrintMethod = "printBranchOperand";900 let EncoderMethod = "getDirectBrEncoding";901 let DecoderMethod = "decodeDirectBrTarget";902 let ParserMatchClass = PPCDirectBrAsmOperand;903 let OperandType = "OPERAND_PCREL";904}905def abscalltarget : Operand<iPTR> {906 let PrintMethod = "printAbsBranchOperand";907 let EncoderMethod = "getAbsDirectBrEncoding";908 let DecoderMethod = "decodeDirectBrTarget";909 let ParserMatchClass = PPCDirectBrAsmOperand;910}911def PPCCRBitMaskOperand : AsmOperandClass {912 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";913}914def crbitm: Operand<i8> {915 let PrintMethod = "printcrbitm";916 let EncoderMethod = "get_crbitm_encoding";917 let DecoderMethod = "decodeCRBitMOperand";918 let ParserMatchClass = PPCCRBitMaskOperand;919}920// Address operands921// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).922def PPCRegGxRCNoR0Operand : AsmOperandClass {923 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";924}925 926def ppc_ptr_rc : RegClassByHwMode<927 [PPC32, PPC64],928 [GPRC, G8RC]>;929 930def ptr_rc_nor0_by_hwmode : RegClassByHwMode<931 [PPC32, PPC64],932 [GPRC_NOR0, G8RC_NOX0]>;933 934def ptr_rc_nor0 : RegisterOperand<ptr_rc_nor0_by_hwmode> {935 let ParserMatchClass = PPCRegGxRCNoR0Operand;936}937 938// New addressing modes with 34 bit immediates.939def PPCDispRI34Operand : AsmOperandClass {940 let Name = "DispRI34"; let PredicateMethod = "isS34Imm";941 let RenderMethod = "addImmOperands";942}943def dispRI34 : Operand<iPTR> {944 let ParserMatchClass = PPCDispRI34Operand;945 let EncoderMethod = "getDispRI34Encoding";946 let DecoderMethod = "decodeSImmOperand<34>";947}948def dispRI34_pcrel : Operand<iPTR> {949 let ParserMatchClass = PPCDispRI34Operand;950 let EncoderMethod = "getDispRI34PCRelEncoding";951 let DecoderMethod = "decodeSImmOperand<34>";952}953def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value.954 let PrintMethod = "printMemRegImm34";955 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg);956}957// memri, imm is a 34-bit value for pc-relative instructions where958// base register is set to zero.959def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.960 let PrintMethod = "printMemRegImm34PCRel";961 let MIOperandInfo = (ops dispRI34_pcrel:$imm, immZero:$reg);962}963 964// A version of ptr_rc usable with the asm parser.965def PPCRegGxRCOperand : AsmOperandClass {966 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";967}968 969def ptr_rc_idx_by_hwmode : RegClassByHwMode<[PPC32, PPC64],970 [GPRC, G8RC]>;971 972def ptr_rc_idx : RegisterOperand<ptr_rc_idx_by_hwmode> {973 let ParserMatchClass = PPCRegGxRCOperand;974}975 976def PPCDispRIOperand : AsmOperandClass {977 let Name = "DispRI"; let PredicateMethod = "isS16Imm";978 let RenderMethod = "addS16ImmOperands";979}980def dispRI : Operand<iPTR> {981 let ParserMatchClass = PPCDispRIOperand;982 let EncoderMethod = "getDispRIEncoding";983}984def PPCDispRIXOperand : AsmOperandClass {985 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";986 let RenderMethod = "addS16ImmOperands";987}988def dispRIX : Operand<iPTR> {989 let ParserMatchClass = PPCDispRIXOperand;990 let EncoderMethod = "getDispRIXEncoding";991 let DecoderMethod = "decodeDispRIXOperand";992}993def PPCDispRIHashOperand : AsmOperandClass {994 let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8";995 let RenderMethod = "addImmOperands";996}997def dispRIHash : Operand<iPTR> {998 let ParserMatchClass = PPCDispRIHashOperand;999 let EncoderMethod = "getDispRIHashEncoding";1000 let DecoderMethod = "decodeDispRIHashOperand";1001}1002def PPCDispRIX16Operand : AsmOperandClass {1003 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";1004 let RenderMethod = "addS16ImmOperands";1005}1006def dispRIX16 : Operand<iPTR> {1007 let ParserMatchClass = PPCDispRIX16Operand;1008 let EncoderMethod = "getDispRIX16Encoding";1009 let DecoderMethod = "decodeDispRIX16Operand";1010 1011}1012def PPCDispSPE8Operand : AsmOperandClass {1013 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";1014 let RenderMethod = "addImmOperands";1015}1016def dispSPE8 : Operand<iPTR> {1017 let ParserMatchClass = PPCDispSPE8Operand;1018 let DecoderMethod = "decodeDispSPE8Operand";1019 let EncoderMethod = "getDispSPE8Encoding";1020}1021def PPCDispSPE4Operand : AsmOperandClass {1022 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";1023 let RenderMethod = "addImmOperands";1024}1025def dispSPE4 : Operand<iPTR> {1026 let ParserMatchClass = PPCDispSPE4Operand;1027 let DecoderMethod = "decodeDispSPE4Operand";1028 let EncoderMethod = "getDispSPE4Encoding";1029}1030def PPCDispSPE2Operand : AsmOperandClass {1031 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";1032 let RenderMethod = "addImmOperands";1033}1034def dispSPE2 : Operand<iPTR> {1035 let ParserMatchClass = PPCDispSPE2Operand;1036 let DecoderMethod = "decodeDispSPE2Operand";1037 let EncoderMethod = "getDispSPE2Encoding";1038}1039 1040def memri : Operand<iPTR> {1041 let PrintMethod = "printMemRegImm";1042 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);1043 let OperandType = "OPERAND_MEMORY";1044}1045def memrr : Operand<iPTR> {1046 let PrintMethod = "printMemRegReg";1047 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);1048 let OperandType = "OPERAND_MEMORY";1049}1050def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.1051 let PrintMethod = "printMemRegImm";1052 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);1053 let OperandType = "OPERAND_MEMORY";1054}1055def memrihash : Operand<iPTR> {1056 // memrihash 8-aligned for ROP Protection Instructions.1057 let PrintMethod = "printMemRegImmHash";1058 let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg);1059 let OperandType = "OPERAND_MEMORY";1060}1061def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}1062 let PrintMethod = "printMemRegImm";1063 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);1064 let OperandType = "OPERAND_MEMORY";1065}1066def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.1067 let PrintMethod = "printMemRegImm";1068 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);1069 let OperandType = "OPERAND_MEMORY";1070}1071def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.1072 let PrintMethod = "printMemRegImm";1073 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);1074 let OperandType = "OPERAND_MEMORY";1075}1076def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.1077 let PrintMethod = "printMemRegImm";1078 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);1079 let OperandType = "OPERAND_MEMORY";1080}1081 1082// A single-register address. This is used with the SjLj1083// pseudo-instructions which translates to LD/LWZ. These instructions requires1084// G8RC_NOX0 registers.1085def memr : Operand<iPTR> {1086 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);1087 let OperandType = "OPERAND_MEMORY";1088}1089def PPCTLSRegOperand : AsmOperandClass {1090 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";1091 let RenderMethod = "addTLSRegOperands";1092}1093def tlsreg32 : Operand<i32> {1094 let EncoderMethod = "getTLSRegEncoding";1095 let ParserMatchClass = PPCTLSRegOperand;1096}1097def tlsgd32 : Operand<i32> {}1098def tlscall32 : Operand<i32> {1099 let PrintMethod = "printTLSCall";1100 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);1101 let EncoderMethod = "getTLSCallEncoding";1102}1103 1104// PowerPC Predicate operand.1105def pred : Operand<OtherVT> {1106 let PrintMethod = "printPredicateOperand";1107 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);1108}1109 1110def PPCRegVSRCAsmOperand : AsmOperandClass {1111 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";1112}1113def vsrc : RegisterOperand<VSRC> {1114 let ParserMatchClass = PPCRegVSRCAsmOperand;1115}1116 1117def PPCRegVSFRCAsmOperand : AsmOperandClass {1118 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";1119}1120def vsfrc : RegisterOperand<VSFRC> {1121 let ParserMatchClass = PPCRegVSFRCAsmOperand;1122}1123 1124def PPCRegVSSRCAsmOperand : AsmOperandClass {1125 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";1126}1127def vssrc : RegisterOperand<VSSRC> {1128 let ParserMatchClass = PPCRegVSSRCAsmOperand;1129}1130 1131def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass {1132 let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber";1133}1134 1135def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> {1136 let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand;1137}1138 1139def PPCRegVSRpRCAsmOperand : AsmOperandClass {1140 let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber";1141}1142 1143def vsrprc : RegisterOperand<VSRpRC> {1144 let ParserMatchClass = PPCRegVSRpRCAsmOperand;1145}1146 1147def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass {1148 let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber";1149}1150 1151def vsrpevenrc : RegisterOperand<VSRpRC> {1152 let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand;1153 let EncoderMethod = "getVSRpEvenEncoding";1154 let DecoderMethod = "decodeVSRpEvenOperands";1155}1156 1157def PPCRegACCRCAsmOperand : AsmOperandClass {1158 let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber";1159}1160 1161def acc : RegisterOperand<ACCRC> {1162 let ParserMatchClass = PPCRegACCRCAsmOperand;1163}1164 1165def uacc : RegisterOperand<UACCRC> {1166 let ParserMatchClass = PPCRegACCRCAsmOperand;1167}1168 1169// DMR Register Operands1170def PPCRegDMRROWRCAsmOperand : AsmOperandClass {1171 let Name = "RegDMRROWRC";1172 let PredicateMethod = "isDMRROWRegNumber";1173}1174 1175def dmrrow : RegisterOperand<DMRROWRC> {1176 let ParserMatchClass = PPCRegDMRROWRCAsmOperand;1177}1178 1179def PPCRegDMRROWpRCAsmOperand : AsmOperandClass {1180 let Name = "RegDMRROWpRC";1181 let PredicateMethod = "isDMRROWpRegNumber";1182}1183 1184def dmrrowp : RegisterOperand<DMRROWpRC> {1185 let ParserMatchClass = PPCRegDMRROWpRCAsmOperand;1186}1187 1188def wacc : RegisterOperand<WACCRC> {1189 let ParserMatchClass = PPCRegACCRCAsmOperand;1190}1191 1192def wacc_hi : RegisterOperand<WACC_HIRC> {1193 let ParserMatchClass = PPCRegACCRCAsmOperand;1194}1195 1196def PPCRegDMRRCAsmOperand : AsmOperandClass {1197 let Name = "RegDMRRC";1198 let PredicateMethod = "isDMRRegNumber";1199}1200 1201def dmr : RegisterOperand<DMRRC> {1202 let ParserMatchClass = PPCRegDMRRCAsmOperand;1203}1204 1205def PPCRegDMRpRCAsmOperand : AsmOperandClass {1206 let Name = "RegDMRpRC";1207 let PredicateMethod = "isDMRpRegNumber";1208}1209 1210def dmrp : RegisterOperand<DMRpRC> {1211 let ParserMatchClass = PPCRegDMRpRCAsmOperand;1212}1213