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1//===- PPCRegisterInfoDMR.td - The PowerPC Register File *- tablegen -*----===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Register info specific to Power PC Dense Math Registers(DMR).10//11// Register classes in this file are related to the Dense Math Registers (DMR).12// There are a total of 8 DMR registers numbered 0 to 7.13// The 4 different views of each DMR register.14//15// [ DMR0 ]16// | WACC0 | WACC_HI0 |17// | DMRROWp0 | DMRROWp1 | DMRROWp2 | DMRROWp3 |18// |DMRROW0|DMRROW1|DMRROW2|DMRROW3|DMRROW4|DMRROW5|DMRROW6|DMRROW7|19// [128bits|128bits|128bits|128bits|128bits|128bits|128bits|128bits]20//21// In addition to the above classes two consecutive DMR registers make a DMR22// DMR pair (DMRp) that is 2048 bits.23//===----------------------------------------------------------------------===//24 25let Namespace = "PPC" in {26def sub_dmrrow0 : SubRegIndex<128>;27def sub_dmrrow1 : SubRegIndex<128, 128>;28def sub_dmrrowp0 : SubRegIndex<256>;29def sub_dmrrowp1 : SubRegIndex<256, 256>;30def sub_wacc_lo : SubRegIndex<512>;31def sub_wacc_hi : SubRegIndex<512, 512>;32def sub_dmr0 : SubRegIndex<1024>;33def sub_dmr1 : SubRegIndex<1024, 1024>;34}35 36// A single row in a DMR register.37// There are 8 128 bit rows in each DMR register and 8 DMR registers so that38// makes 64 DMRROW registers in total.39class DMRROW<bits<6> num, string n> : PPCReg<n> {40 let HWEncoding{5-0} = num;41}42 43// A consecutive pair of DMR row registers.44class DMRROWp<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {45 let HWEncoding{4-0} = num;46 let SubRegs = subregs;47}48 49// WACC - Wide ACC registers. Accumulator registers that are subregs of DMR.50// These ACC registers no longer include VSR regs as subregs.51class WACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {52 let HWEncoding{2-0} = num;53 let SubRegs = subregs;54}55 56// High bits for the ACC registers.57// When the ACC register is used these bits are ignored.58// When the ACC register is the target, these bits are set to zero.59class WACC_HI<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {60 let HWEncoding{2-0} = num;61 let SubRegs = subregs;62}63 64class DMR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {65 let HWEncoding{2-0} = num;66 let SubRegs = subregs;67}68 69class DMRp<bits<2> num, string n, list<Register> subregs> : PPCReg<n> {70 let HWEncoding{1-0} = num;71 let SubRegs = subregs;72}73 74// The DMR Row type registers are the lowest level of registers and have no75// subregs.76foreach Index = 0-63 in {77 def DMRROW#Index : DMRROW<Index, "dmrrow"#Index>, DwarfRegNum<[-1, -1]>;78}79 80// DMRROW pairs are consecutive pairs.81// DMRROWp0 = DMRROW0, DMRROW182// DMRROWp1 = DMRROW2, DMRROW383// DMRROWp2 = DMRROW4, DMRROW584// etc...85let SubRegIndices = [sub_dmrrow0, sub_dmrrow1] in {86 foreach Index = 0-31 in {87 def DMRROWp#Index : DMRROWp<Index, "dmrrowp"#Index,88 [!cast<DMRROW>("DMRROW"#!mul(Index, 2)),89 !cast<DMRROW>("DMRROW"#!add(!mul(Index, 2), 1))]>, DwarfRegNum<[-1, -1]>;90 }91}92 93let SubRegIndices = [sub_dmrrowp0, sub_dmrrowp1] in {94 // WACC0 = DMRROWp0, DMRROWp195 // WACC1 = DMRROWp4, DMRROWp596 // WACC2 = DMRROWp8, DMRROWp997 // etc...98 foreach Index = 0-7 in {99 def WACC#Index : WACC<Index, "wacc"#Index,100 [!cast<DMRROWp>("DMRROWp"#!mul(Index, 4)),101 !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 1))]>, DwarfRegNum<[-1, -1]>;102 }103 104 // WACC_HI0 = DMRROWp2, DMRROWp3105 // WACC_HI1 = DMRROWp6, DMRROWp7106 // WACC_HI2 = DMRROWp10, DMRROWp11107 // etc...108 foreach Index = 0-7 in {109 def WACC_HI#Index : WACC_HI<Index, "wacc_hi"#Index,110 [!cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 2)),111 !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 3))]>, DwarfRegNum<[-1, -1]>;112 }113}114 115// DMR0 = WACC0, WACC_HI0116// DMR1 = WACC1, WACC_HI1117// DMR2 = WACC2, WACC_HI2118// etc...119let SubRegIndices = [sub_wacc_lo, sub_wacc_hi] in {120 foreach Index = 0-7 in {121 def DMR#Index : DMR<Index, "dmr"#Index, [!cast<WACC>("WACC"#Index), !cast<WACC_HI>("WACC_HI"#Index)]>, DwarfRegNum<[-1, -1]>;122 }123}124 125// DMRp0 = DMR0, DMR1126// DMRp1 = DMR2, DMR3127// DMRp2 = DMR4, DMR5128// DMRp3 = DMR6, DMR7129let SubRegIndices = [sub_dmr0, sub_dmr1] in {130 def DMRp0 : DMRp<0, "dmrp0", [DMR0, DMR1]>, DwarfRegNum<[-1, -1]>;131 def DMRp1 : DMRp<1, "dmrp1", [DMR2, DMR3]>, DwarfRegNum<[-1, -1]>;132 def DMRp2 : DMRp<2, "dmrp2", [DMR4, DMR5]>, DwarfRegNum<[-1, -1]>;133 def DMRp3 : DMRp<3, "dmrp3", [DMR6, DMR7]>, DwarfRegNum<[-1, -1]>;134}135 136def DMRROWRC : RegisterClass<"PPC", [v128i1], 128,137 (add (sequence "DMRROW%u", 0, 63))> {138 let Size = 128;139}140 141def DMRROWpRC : RegisterClass<"PPC", [v256i1], 128,142 (add (sequence "DMRROWp%u", 0, 31))> {143 let Size = 256;144}145 146def WACCRC : RegisterClass<"PPC", [v512i1], 128,147 (add (sequence "WACC%u", 0, 7))> {148 let Size = 512;149}150 151def WACC_HIRC : RegisterClass<"PPC", [v512i1], 128,152 (add (sequence "WACC_HI%u", 0, 7))> {153 let Size = 512;154}155 156def DMRRC : RegisterClass<"PPC", [v1024i1], 128,157 (add (sequence "DMR%u", 0, 7))> {158 let Size = 1024;159}160 161def DMRpRC : RegisterClass<"PPC", [v2048i1], 128,162 (add DMRp0, DMRp1, DMRp2, DMRp3)> {163 let Size = 2048;164}165