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1//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the itinerary class data for the Freescale e500mc 32-bit10// Power processor.11//12// All information is derived from the "e500mc Core Reference Manual",13// Freescale Document Number E500MCRM, Rev. 1, 03/2012.14//15//===----------------------------------------------------------------------===//16// Relevant functional units in the Freescale e500mc core:17//18// * Decode & Dispatch19// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue20// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).21def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 122def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 223 24// * Execute25// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.26// Some instructions can only execute in SFX0 but not SFX1.27// The CFX has a bypass path, allowing non-divide instructions to execute28// while a divide instruction is executed.29def E500mc_SFX0 : FuncUnit; // Simple unit 030def E500mc_SFX1 : FuncUnit; // Simple unit 131def E500mc_BU : FuncUnit; // Branch unit32def E500mc_CFX_DivBypass33 : FuncUnit; // CFX divide bypass path34def E500mc_CFX_0 : FuncUnit; // CFX pipeline35def E500mc_LSU_0 : FuncUnit; // LSU pipeline36def E500mc_FPU_0 : FuncUnit; // FPU pipeline37 38def E500mc_GPR_Bypass : Bypass;39def E500mc_FPR_Bypass : Bypass;40def E500mc_CR_Bypass : Bypass;41 42def PPCE500mcItineraries : ProcessorItineraries<43 [E500mc_DIS0, E500mc_DIS1, E500mc_SFX0, E500mc_SFX1, E500mc_BU, E500mc_CFX_DivBypass,44 E500mc_CFX_0, E500mc_LSU_0, E500mc_FPU_0],45 [E500mc_CR_Bypass, E500mc_GPR_Bypass, E500mc_FPR_Bypass], [46 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,47 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],48 [4, 1, 1], // Latency = 149 [E500mc_GPR_Bypass,50 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,51 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,52 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],53 [4, 1, 1], // Latency = 154 [E500mc_GPR_Bypass,55 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,56 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,57 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],58 [4, 1, 1, 1], // Latency = 159 [E500mc_GPR_Bypass,60 E500mc_GPR_Bypass, E500mc_GPR_Bypass,61 E500mc_CR_Bypass]>,62 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,63 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],64 [5, 1, 1], // Latency = 1 or 265 [E500mc_CR_Bypass,66 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,67 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,68 InstrStage<1, [E500mc_CFX_0], 0>,69 InstrStage<14, [E500mc_CFX_DivBypass]>],70 [17, 1, 1], // Latency=4..35, Repeat= 4..3571 [E500mc_GPR_Bypass,72 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,73 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,74 InstrStage<8, [E500mc_FPU_0]>],75 [11], // Latency = 876 [E500mc_FPR_Bypass]>,77 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,78 InstrStage<8, [E500mc_FPU_0]>],79 [11, 1, 1], // Latency = 880 [NoBypass, NoBypass, NoBypass]>,81 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,82 InstrStage<1, [E500mc_CFX_0]>],83 [7, 1, 1], // Latency = 4, Repeat rate = 184 [E500mc_GPR_Bypass,85 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,86 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,87 InstrStage<1, [E500mc_CFX_0]>],88 [7, 1, 1], // Latency = 4, Repeat rate = 189 [E500mc_GPR_Bypass,90 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,91 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,92 InstrStage<1, [E500mc_CFX_0]>],93 [7, 1, 1], // Latency = 4, Repeat rate = 194 [E500mc_GPR_Bypass,95 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,96 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,97 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],98 [4, 1, 1], // Latency = 199 [E500mc_GPR_Bypass,100 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,101 InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,102 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],103 [4, 1, 1], // Latency = 1104 [E500mc_GPR_Bypass,105 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,106 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,107 InstrStage<2, [E500mc_SFX0]>],108 [5, 1], // Latency = 2, Repeat rate = 2109 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,110 InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,111 InstrStage<1, [E500mc_BU]>],112 [4, 1], // Latency = 1113 [NoBypass, E500mc_GPR_Bypass]>,114 InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,115 InstrStage<1, [E500mc_BU]>],116 [4, 1, 1], // Latency = 1117 [E500mc_CR_Bypass,118 E500mc_CR_Bypass, E500mc_CR_Bypass]>,119 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,120 InstrStage<1, [E500mc_BU]>],121 [4, 1], // Latency = 1122 [E500mc_CR_Bypass, E500mc_CR_Bypass]>,123 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,124 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],125 [4, 1, 1], // Latency = 1126 [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,127 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,128 InstrStage<1, [E500mc_LSU_0]>],129 [6, 1], // Latency = 3, Repeat rate = 1130 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,131 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,132 InstrStage<1, [E500mc_LSU_0]>],133 [6, 1], // Latency = 3134 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,135 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,136 InstrStage<1, [E500mc_LSU_0]>],137 [6, 1], // Latency = 3138 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,139 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,140 InstrStage<1, [E500mc_LSU_0]>],141 [6, 1], // Latency = 3142 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,143 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,144 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,145 InstrStage<1, [E500mc_LSU_0]>],146 [6, 1], // Latency = 3147 [E500mc_GPR_Bypass, E500mc_GPR_Bypass],148 2>, // 2 micro-ops149 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,150 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,151 InstrStage<1, [E500mc_LSU_0]>],152 [6, 1], // Latency = 3153 [E500mc_GPR_Bypass, E500mc_GPR_Bypass],154 2>, // 2 micro-ops155 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,156 InstrStage<1, [E500mc_LSU_0]>],157 [6, 1], // Latency = 3158 [NoBypass, E500mc_GPR_Bypass]>,159 InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,160 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,161 InstrStage<1, [E500mc_LSU_0]>],162 [6, 1], // Latency = 3163 [NoBypass, E500mc_GPR_Bypass],164 2>, // 2 micro-ops165 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,166 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,167 InstrStage<1, [E500mc_LSU_0]>],168 [6, 1], // Latency = 3169 [NoBypass, E500mc_GPR_Bypass],170 2>, // 2 micro-ops171 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,172 InstrStage<1, [E500mc_LSU_0]>],173 [6, 1], // Latency = 3174 [NoBypass, E500mc_GPR_Bypass]>,175 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,176 InstrStage<1, [E500mc_LSU_0]>],177 [6, 1, 1], // Latency = 3178 [E500mc_GPR_Bypass,179 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,180 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,181 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,182 InstrStage<1, [E500mc_LSU_0]>],183 [6, 1, 1], // Latency = 3184 [E500mc_GPR_Bypass,185 E500mc_GPR_Bypass, E500mc_GPR_Bypass],186 2>, // 2 micro-ops187 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,188 InstrStage<1, [E500mc_LSU_0]>],189 [7, 1, 1], // Latency = 4190 [E500mc_FPR_Bypass,191 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,192 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,193 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,194 InstrStage<1, [E500mc_LSU_0]>],195 [7, 1, 1], // Latency = 4196 [E500mc_FPR_Bypass,197 E500mc_GPR_Bypass, E500mc_GPR_Bypass],198 2>, // 2 micro-ops199 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,200 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,201 InstrStage<1, [E500mc_LSU_0]>],202 [7, 1, 1], // Latency = 4203 [E500mc_FPR_Bypass,204 E500mc_GPR_Bypass, E500mc_GPR_Bypass],205 2>, // 2 micro-ops206 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,207 InstrStage<1, [E500mc_LSU_0]>],208 [6, 1], // Latency = 3209 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,210 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,211 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,212 InstrStage<1, [E500mc_LSU_0]>],213 [6, 1], // Latency = 3214 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,215 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,216 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,217 InstrStage<1, [E500mc_LSU_0]>],218 [6, 1], // Latency = 3219 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,220 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,221 InstrStage<1, [E500mc_LSU_0]>],222 [7, 1], // Latency = r+3223 [NoBypass, E500mc_GPR_Bypass]>,224 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,225 InstrStage<3, [E500mc_LSU_0]>],226 [6, 1, 1], // Latency = 3, Repeat rate = 3227 [E500mc_GPR_Bypass,228 E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,229 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,230 InstrStage<1, [E500mc_LSU_0]>],231 [6, 1], // Latency = 3232 [NoBypass, E500mc_GPR_Bypass]>,233 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,234 InstrStage<1, [E500mc_LSU_0]>]>,235 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,236 InstrStage<4, [E500mc_SFX0]>],237 [7, 1],238 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,239 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,240 InstrStage<2, [E500mc_SFX0, E500mc_SFX1]>],241 [5, 1], // Latency = 2, Repeat rate = 4242 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,243 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,244 InstrStage<1, [E500mc_SFX0]>],245 [5, 1],246 [NoBypass, E500mc_GPR_Bypass]>,247 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,248 InstrStage<1, [E500mc_LSU_0], 0>]>,249 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,250 InstrStage<5, [E500mc_SFX0]>],251 [8, 1],252 [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,253 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,254 InstrStage<5, [E500mc_SFX0]>],255 [8, 1],256 [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,257 InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,258 InstrStage<4, [E500mc_SFX0]>],259 [7, 1], // Latency = 4, Repeat rate = 4260 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,261 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,262 InstrStage<4, [E500mc_SFX0]>],263 [7, 1], // Latency = 4, Repeat rate = 4264 [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,265 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,266 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],267 [4, 1], // Latency = 1, Repeat rate = 1268 [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,269 InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,270 InstrStage<1, [E500mc_SFX0]>],271 [4, 1], // Latency = 1, Repeat rate = 1272 [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,273 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,274 InstrStage<4, [E500mc_SFX0]>],275 [7, 1], // Latency = 4, Repeat rate = 4276 [NoBypass, E500mc_GPR_Bypass]>,277 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,278 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],279 [4, 1], // Latency = 1, Repeat rate = 1280 [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,281 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,282 InstrStage<1, [E500mc_SFX0]>],283 [4, 1],284 [NoBypass, E500mc_GPR_Bypass]>,285 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,286 InstrStage<2, [E500mc_FPU_0]>],287 [11, 1, 1], // Latency = 8, Repeat rate = 2288 [E500mc_FPR_Bypass,289 E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,290 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,291 InstrStage<4, [E500mc_FPU_0]>],292 [13, 1, 1], // Latency = 10, Repeat rate = 4293 [E500mc_FPR_Bypass,294 E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,295 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,296 InstrStage<2, [E500mc_FPU_0]>],297 [11, 1, 1], // Latency = 8, Repeat rate = 2298 [E500mc_CR_Bypass,299 E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,300 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,301 InstrStage<68, [E500mc_FPU_0]>],302 [71, 1, 1], // Latency = 68, Repeat rate = 68303 [E500mc_FPR_Bypass,304 E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,305 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,306 InstrStage<38, [E500mc_FPU_0]>],307 [41, 1, 1], // Latency = 38, Repeat rate = 38308 [E500mc_FPR_Bypass,309 E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,310 InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,311 InstrStage<4, [E500mc_FPU_0]>],312 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4313 [E500mc_FPR_Bypass,314 E500mc_FPR_Bypass, E500mc_FPR_Bypass,315 E500mc_FPR_Bypass]>,316 InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,317 InstrStage<38, [E500mc_FPU_0]>],318 [41, 1], // Latency = 38, Repeat rate = 38319 [E500mc_FPR_Bypass, E500mc_FPR_Bypass]>320]>;321 322// ===---------------------------------------------------------------------===//323// e500mc machine model for scheduling and other instruction cost heuristics.324 325def PPCE500mcModel : SchedMachineModel {326 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.327 let LoadLatency = 5; // Optimistic load latency assuming bypass.328 // This is overriden by OperandCycles if the329 // Itineraries are queried instead.330 331 let CompleteModel = 0;332 333 let Itineraries = PPCE500mcItineraries;334}335