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1//===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the itinerary class data for the Freescale e5500 64-bit10// Power processor.11//12// All information is derived from the "e5500 Core Reference Manual",13// Freescale Document Number e5500RM, Rev. 1, 03/2012.14//15//===----------------------------------------------------------------------===//16// Relevant functional units in the Freescale e5500 core17// (These are the same as for the e500mc)18//19// * Decode & Dispatch20// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue21// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).22def E5500_DIS0 : FuncUnit;23def E5500_DIS1 : FuncUnit;24 25// * Execute26// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.27// The CFX has a bypass path, allowing non-divide instructions to execute28// while a divide instruction is being executed.29def E5500_SFX0 : FuncUnit; // Simple unit 030def E5500_SFX1 : FuncUnit; // Simple unit 131def E5500_BU : FuncUnit; // Branch unit32def E5500_CFX_DivBypass33 : FuncUnit; // CFX divide bypass path34def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 035 36def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 137 38def E5500_LSU_0 : FuncUnit; // LSU pipeline39def E5500_FPU_0 : FuncUnit; // FPU pipeline40 41def E5500_GPR_Bypass : Bypass;42def E5500_FPR_Bypass : Bypass;43def E5500_CR_Bypass : Bypass;44 45def PPCE5500Itineraries : ProcessorItineraries<46 [E5500_DIS0, E5500_DIS1, E5500_SFX0, E5500_SFX1, E5500_BU,47 E5500_CFX_DivBypass, E5500_CFX_0, E5500_CFX_1,48 E5500_LSU_0, E5500_FPU_0],49 [E5500_CR_Bypass, E5500_GPR_Bypass, E5500_FPR_Bypass], [50 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,51 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],52 [5, 2, 2], // Latency = 153 [E5500_GPR_Bypass,54 E5500_GPR_Bypass, E5500_GPR_Bypass]>,55 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,56 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],57 [5, 2, 2], // Latency = 158 [E5500_GPR_Bypass,59 E5500_GPR_Bypass, E5500_GPR_Bypass]>,60 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,61 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],62 [5, 2, 2, 2], // Latency = 163 [E5500_GPR_Bypass,64 E5500_GPR_Bypass, E5500_GPR_Bypass,65 E5500_CR_Bypass]>,66 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,67 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],68 [6, 2, 2], // Latency = 1 or 269 [E5500_CR_Bypass,70 E5500_GPR_Bypass, E5500_GPR_Bypass]>,71 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,72 InstrStage<1, [E5500_CFX_0], 0>,73 InstrStage<26, [E5500_CFX_DivBypass]>],74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..2675 [E5500_GPR_Bypass,76 E5500_GPR_Bypass, E5500_GPR_Bypass]>,77 InstrItinData<IIC_IntDivW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,78 InstrStage<1, [E5500_CFX_0], 0>,79 InstrStage<16, [E5500_CFX_DivBypass]>],80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..1681 [E5500_GPR_Bypass,82 E5500_GPR_Bypass, E5500_GPR_Bypass]>,83 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,84 InstrStage<1, [E5500_FPU_0]>],85 [11], // Latency = 7, Repeat rate = 186 [E5500_FPR_Bypass]>,87 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,88 InstrStage<7, [E5500_FPU_0]>],89 [11, 2, 2], // Latency = 7, Repeat rate = 790 [NoBypass, NoBypass, NoBypass]>,91 InstrItinData<IIC_IntMulHD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,92 InstrStage<1, [E5500_CFX_0], 0>,93 InstrStage<2, [E5500_CFX_1]>],94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..495 [E5500_GPR_Bypass,96 E5500_GPR_Bypass, E5500_GPR_Bypass]>,97 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,98 InstrStage<1, [E5500_CFX_0], 0>,99 InstrStage<1, [E5500_CFX_1]>],100 [8, 2, 2], // Latency = 4, Repeat rate = 1101 [E5500_GPR_Bypass,102 E5500_GPR_Bypass, E5500_GPR_Bypass]>,103 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,104 InstrStage<1, [E5500_CFX_0], 0>,105 InstrStage<1, [E5500_CFX_1]>],106 [8, 2, 2], // Latency = 4, Repeat rate = 1107 [E5500_GPR_Bypass,108 E5500_GPR_Bypass, E5500_GPR_Bypass]>,109 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,110 InstrStage<1, [E5500_CFX_0], 0>,111 InstrStage<2, [E5500_CFX_1]>],112 [8, 2, 2], // Latency = 4 or 5, Repeat = 2113 [E5500_GPR_Bypass,114 E5500_GPR_Bypass, E5500_GPR_Bypass]>,115 InstrItinData<IIC_IntRotate, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,116 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],117 [5, 2, 2], // Latency = 1118 [E5500_GPR_Bypass,119 E5500_GPR_Bypass, E5500_GPR_Bypass]>,120 InstrItinData<IIC_IntRotateD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,121 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],122 [6, 2, 2], // Latency = 2, Repeat rate = 2123 [E5500_GPR_Bypass,124 E5500_GPR_Bypass, E5500_GPR_Bypass]>,125 InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,126 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],127 [5, 2, 2], // Latency = 1, Repeat rate = 1128 [E5500_GPR_Bypass,129 E5500_GPR_Bypass, E5500_GPR_Bypass]>,130 InstrItinData<IIC_IntShift, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,131 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],132 [6, 2, 2], // Latency = 2, Repeat rate = 2133 [E5500_GPR_Bypass,134 E5500_GPR_Bypass, E5500_GPR_Bypass]>,135 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,136 InstrStage<2, [E5500_SFX0]>],137 [6, 2], // Latency = 2, Repeat rate = 2138 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,139 InstrItinData<IIC_BrB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,140 InstrStage<1, [E5500_BU]>],141 [5, 2], // Latency = 1142 [NoBypass, E5500_GPR_Bypass]>,143 InstrItinData<IIC_BrCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,144 InstrStage<1, [E5500_BU]>],145 [5, 2, 2], // Latency = 1146 [E5500_CR_Bypass,147 E5500_CR_Bypass, E5500_CR_Bypass]>,148 InstrItinData<IIC_BrMCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,149 InstrStage<1, [E5500_BU]>],150 [5, 2], // Latency = 1151 [E5500_CR_Bypass, E5500_CR_Bypass]>,152 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,153 InstrStage<1, [E5500_CFX_0]>],154 [5, 2, 2], // Latency = 1155 [E5500_CR_Bypass, E5500_GPR_Bypass]>,156 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,157 InstrStage<1, [E5500_LSU_0]>],158 [7, 2], // Latency = 3, Repeat rate = 1159 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,160 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,161 InstrStage<1, [E5500_LSU_0]>],162 [7, 2], // Latency = 3, Repeat rate = 1163 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,164 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,165 InstrStage<1, [E5500_LSU_0]>],166 [7, 2], // Latency = 3, Repeat rate = 1167 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,168 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,169 InstrStage<1, [E5500_LSU_0]>],170 [7, 2], // Latency = 3171 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,172 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,173 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,174 InstrStage<1, [E5500_LSU_0]>],175 [7, 2], // Latency = 3, Repeat rate = 1176 [E5500_GPR_Bypass, E5500_GPR_Bypass],177 2>, // 2 micro-ops178 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,179 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,180 InstrStage<1, [E5500_LSU_0]>],181 [7, 2], // Latency = 3, Repeat rate = 1182 [E5500_GPR_Bypass, E5500_GPR_Bypass],183 2>, // 2 micro-ops184 InstrItinData<IIC_LdStLD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,185 InstrStage<1, [E5500_LSU_0]>],186 [7, 2], // Latency = 3, Repeat rate = 1187 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,188 InstrItinData<IIC_LdStLDARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,189 InstrStage<3, [E5500_LSU_0]>],190 [7, 2], // Latency = 3, Repeat rate = 3191 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,192 InstrItinData<IIC_LdStLDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,193 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,194 InstrStage<1, [E5500_LSU_0]>],195 [7, 2], // Latency = 3, Repeat rate = 1196 [E5500_GPR_Bypass, E5500_GPR_Bypass],197 2>, // 2 micro-ops198 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,199 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,200 InstrStage<1, [E5500_LSU_0]>],201 [7, 2], // Latency = 3, Repeat rate = 1202 [E5500_GPR_Bypass, E5500_GPR_Bypass],203 2>, // 2 micro-ops204 InstrItinData<IIC_LdStStore, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,205 InstrStage<1, [E5500_LSU_0]>],206 [7, 2], // Latency = 3, Repeat rate = 1207 [NoBypass, E5500_GPR_Bypass]>,208 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,209 InstrStage<1, [E5500_LSU_0]>],210 [7, 2], // Latency = 3, Repeat rate = 1211 [NoBypass, E5500_GPR_Bypass]>,212 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,213 InstrStage<1, [E5500_LSU_0]>],214 [7, 2, 2], // Latency = 3, Repeat rate = 1215 [E5500_GPR_Bypass,216 E5500_GPR_Bypass, E5500_GPR_Bypass]>,217 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,218 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,219 InstrStage<1, [E5500_LSU_0]>],220 [7, 2, 2], // Latency = 3, Repeat rate = 1221 [E5500_GPR_Bypass,222 E5500_GPR_Bypass, E5500_GPR_Bypass],223 2>, // 2 micro-ops224 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,225 InstrStage<1, [E5500_LSU_0]>],226 [8, 2, 2], // Latency = 4, Repeat rate = 1227 [E5500_FPR_Bypass,228 E5500_GPR_Bypass, E5500_GPR_Bypass],229 2>, // 2 micro-ops230 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,231 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,232 InstrStage<1, [E5500_LSU_0]>],233 [8, 2, 2], // Latency = 4, Repeat rate = 1234 [E5500_FPR_Bypass,235 E5500_GPR_Bypass, E5500_GPR_Bypass],236 2>, // 2 micro-ops237 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,238 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,239 InstrStage<1, [E5500_LSU_0]>],240 [8, 2, 2], // Latency = 4, Repeat rate = 1241 [E5500_FPR_Bypass,242 E5500_GPR_Bypass, E5500_GPR_Bypass],243 2>, // 2 micro-ops244 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,245 InstrStage<1, [E5500_LSU_0]>],246 [7, 2], // Latency = 3247 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,248 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,249 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,250 InstrStage<1, [E5500_LSU_0]>],251 [7, 2], // Latency = 3, Repeat rate = 1252 [E5500_GPR_Bypass, E5500_GPR_Bypass],253 2>, // 2 micro-ops254 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,255 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,256 InstrStage<1, [E5500_LSU_0]>],257 [7, 2], // Latency = 3, Repeat rate = 1258 [E5500_GPR_Bypass, E5500_GPR_Bypass],259 2>, // 2 micro-ops260 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,261 InstrStage<4, [E5500_LSU_0]>],262 [8, 2], // Latency = r+3, Repeat rate = r+3263 [NoBypass, E5500_GPR_Bypass]>,264 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,265 InstrStage<3, [E5500_LSU_0]>],266 [7, 2, 2], // Latency = 3, Repeat rate = 3267 [E5500_GPR_Bypass,268 E5500_GPR_Bypass, E5500_GPR_Bypass]>,269 InstrItinData<IIC_LdStSTD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,270 InstrStage<1, [E5500_LSU_0]>],271 [7, 2], // Latency = 3, Repeat rate = 1272 [NoBypass, E5500_GPR_Bypass]>,273 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,274 InstrStage<1, [E5500_LSU_0]>],275 [7, 2], // Latency = 3, Repeat rate = 1276 [NoBypass, E5500_GPR_Bypass]>,277 InstrItinData<IIC_LdStSTU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,278 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,279 InstrStage<1, [E5500_LSU_0]>],280 [7, 2], // Latency = 3, Repeat rate = 1281 [NoBypass, E5500_GPR_Bypass],282 2>, // 2 micro-ops283 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,284 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,285 InstrStage<1, [E5500_LSU_0]>],286 [7, 2], // Latency = 3, Repeat rate = 1287 [NoBypass, E5500_GPR_Bypass],288 2>, // 2 micro-ops289 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,290 InstrStage<1, [E5500_LSU_0]>],291 [7, 2], // Latency = 3, Repeat rate = 1292 [NoBypass, E5500_GPR_Bypass]>,293 InstrItinData<IIC_LdStSync, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,294 InstrStage<1, [E5500_LSU_0]>]>,295 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,296 InstrStage<2, [E5500_CFX_0]>],297 [6, 2], // Latency = 2, Repeat rate = 4298 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,299 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,300 InstrStage<1, [E5500_LSU_0], 0>]>,301 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,302 InstrStage<5, [E5500_CFX_0]>],303 [9, 2], // Latency = 5, Repeat rate = 5304 [E5500_GPR_Bypass, E5500_CR_Bypass]>,305 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,306 InstrStage<5, [E5500_CFX_0]>],307 [9, 2], // Latency = 5, Repeat rate = 5308 [E5500_GPR_Bypass, E5500_CR_Bypass]>,309 InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,310 InstrStage<4, [E5500_CFX_0]>],311 [8, 2], // Latency = 4, Repeat rate = 4312 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,313 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,314 InstrStage<1, [E5500_CFX_0]>],315 [5], // Latency = 1, Repeat rate = 1316 [E5500_GPR_Bypass]>,317 InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,318 InstrStage<1, [E5500_CFX_0]>],319 [5], // Latency = 1, Repeat rate = 1320 [E5500_GPR_Bypass]>,321 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,322 InstrStage<4, [E5500_CFX_0]>],323 [8, 2], // Latency = 4, Repeat rate = 4324 [NoBypass, E5500_GPR_Bypass]>,325 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,326 InstrStage<1, [E5500_CFX_0]>],327 [5], // Latency = 1, Repeat rate = 1328 [E5500_GPR_Bypass]>,329 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,330 InstrStage<1, [E5500_FPU_0]>],331 [11, 2, 2], // Latency = 7, Repeat rate = 1332 [E5500_FPR_Bypass,333 E5500_FPR_Bypass, E5500_FPR_Bypass]>,334 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,335 InstrStage<1, [E5500_FPU_0]>],336 [11, 2, 2], // Latency = 7, Repeat rate = 1337 [E5500_FPR_Bypass,338 E5500_FPR_Bypass, E5500_FPR_Bypass]>,339 InstrItinData<IIC_FPCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,340 InstrStage<1, [E5500_FPU_0]>],341 [11, 2, 2], // Latency = 7, Repeat rate = 1342 [E5500_CR_Bypass,343 E5500_FPR_Bypass, E5500_FPR_Bypass]>,344 InstrItinData<IIC_FPDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,345 InstrStage<31, [E5500_FPU_0]>],346 [39, 2, 2], // Latency = 35, Repeat rate = 31347 [E5500_FPR_Bypass,348 E5500_FPR_Bypass, E5500_FPR_Bypass]>,349 InstrItinData<IIC_FPDivS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,350 InstrStage<16, [E5500_FPU_0]>],351 [24, 2, 2], // Latency = 20, Repeat rate = 16352 [E5500_FPR_Bypass,353 E5500_FPR_Bypass, E5500_FPR_Bypass]>,354 InstrItinData<IIC_FPFused, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,355 InstrStage<1, [E5500_FPU_0]>],356 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1357 [E5500_FPR_Bypass,358 E5500_FPR_Bypass, E5500_FPR_Bypass,359 E5500_FPR_Bypass]>,360 InstrItinData<IIC_FPRes, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,361 InstrStage<2, [E5500_FPU_0]>],362 [12, 2], // Latency = 8, Repeat rate = 2363 [E5500_FPR_Bypass, E5500_FPR_Bypass]>364]>;365 366// ===---------------------------------------------------------------------===//367// e5500 machine model for scheduling and other instruction cost heuristics.368 369def PPCE5500Model : SchedMachineModel {370 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.371 let LoadLatency = 6; // Optimistic load latency assuming bypass.372 // This is overriden by OperandCycles if the373 // Itineraries are queried instead.374 375 let CompleteModel = 0;376 377 let Itineraries = PPCE5500Itineraries;378}379